KR950011554B1 - Multi-layer metalizing method of semiconductor device - Google Patents
Multi-layer metalizing method of semiconductor device Download PDFInfo
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- KR950011554B1 KR950011554B1 KR1019920010443A KR920010443A KR950011554B1 KR 950011554 B1 KR950011554 B1 KR 950011554B1 KR 1019920010443 A KR1019920010443 A KR 1019920010443A KR 920010443 A KR920010443 A KR 920010443A KR 950011554 B1 KR950011554 B1 KR 950011554B1
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 14
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 67
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1a도 내지 제1d도는 종래 기술에 따른 다층금속배선 형성공정을 도시한 단면도.1A to 1D are cross-sectional views showing a process for forming a multi-layer metal wiring according to the prior art.
제2a도 내지 2f도는 본 발명의 실시예에 따른 다층금속배선 형성 공정을 도시한 단면도.2a to 2f are cross-sectional views showing a multi-layer metal wiring forming process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 피드 산화막1: semiconductor substrate 2: feed oxide film
3 : 제1금속층 4 : 제1절연막3: first metal layer 4: first insulating film
4A : 제1절연막 스페이서 5 : 제1감광막4A: first insulating film spacer 5: first photosensitive film
6 : 제2절연막 7 : 제2감광막6: second insulating film 7: second photosensitive film
8 : 제2금속층8: second metal layer
본 발명은 다층금속배선 형성방법에 관한 것으로, 특히 제1금속층패턴을 형성하고 상기 제1금속층패턴 측벽에 절연막 스페이서를 형성한 다음, 전체표면상부에 일정두께 다른 절연막을 형성하고 콘택공정으로 상기 제1금속층패턴에 접속되는 제2금속층을 형성하는 기술에 관한 것이다.The present invention relates to a method for forming a multi-layer metal wiring, and in particular, forming a first metal layer pattern, forming an insulating film spacer on the sidewalls of the first metal layer pattern, and then forming an insulating film having a predetermined thickness on the entire surface thereof, A technique for forming a second metal layer connected to a first metal layer pattern is provided.
일반적으로, 다층 금속 배선 기술에서 가장 필수적인 공정이 금속층간 절연막의 평탄화 방법이다.In general, the most essential process in the multilayer metallization technique is a planarization method of the interlayer insulating film.
종래의 금속층간 절연막을 평탄화 시키기 위한 방법에 있어서는, 먼저 제1금속 배선층 상부에 제1절 연막을 증착시키고, 제1절연막 상부에 포토레지스트층을 도포하면, 포토레지스트층의 점성에 의해 포토레지스트층의 상부면이 평탄화된다. 상기 포토레지스트층을 에치백(Etch Back)한 후 잔존하는 포토레지스트층을 제거한다. 그 후, 금속층 사이의 절연 가능한 두께를 고려하여 제2절연막을 증착하면 평탄화된 절연막이 형성된다.In the conventional method for planarizing an intermetallic insulating film, first, when the first insulation film is deposited on the first metal wiring layer, and the photoresist layer is applied on the first insulating film, the photoresist layer is formed by the viscosity of the photoresist layer. The top surface of is planarized. After etching the photoresist layer, the remaining photoresist layer is removed. After that, when the second insulating film is deposited in consideration of the insulating thickness between the metal layers, the planarized insulating film is formed.
그러나, 제1금속층을 증착하기 전의 공정인 필드 산화막 또는 게이트 폴리층 등에 의한 굴곡으로, 금속층간 콘택식각시 식각되는 금속층간 절연막의 두께가 금속층간의 콘택 위치에 따라 다르게 되므로, 식각공정을 하게 되면, 제1금속층이 과도한 충역을 받게 되어, 홀이 형성되는데, 여기서 제2금속층을 증착하면, 제1금속층과 제2금속층의 콘택이 단락되거나, 완전한 접합이 되지 않아 반도체소자의 신뢰성이 저하되는 문제점이 있다.However, since the thickness of the interlayer insulating film to be etched during the contact etching between the metal layers due to the bending by the field oxide film or the gate poly layer, which is a process before the first metal layer is deposited, the etching process is performed. When the first metal layer is subjected to excessive impulse, holes are formed. When the second metal layer is deposited, the contact between the first metal layer and the second metal layer is short-circuited, or a complete bonding is not performed, thereby deteriorating reliability of the semiconductor device. There is this.
제1a도 내지 제1d도는 종래기술에 따른 다층금속배선형성공정을 도시한 단면도이다.1A to 1D are cross-sectional views showing a multi-layer metal wiring forming process according to the prior art.
제1a도를 참조하면, 반도체기판(1)상부에 필드산화막(2)을 형성한다. 그리고, 상기 반도체기판(1)과 필드산화막(2)상부에 제1금속층(3)패턴을 형성한다. 그리고, 전체표면상부에 제1절연막(4)을 일정두께 형성한다.Referring to FIG. 1A, a field oxide film 2 is formed on the semiconductor substrate 1. The first metal layer 3 pattern is formed on the semiconductor substrate 1 and the field oxide film 2. Then, the first insulating film 4 is formed on the entire surface at a constant thickness.
제1b도를 참조하면, 전체표면상부에 제1감광막(5)을 형성한다. 이때 상기 제1감광막(5)은 점성에 의하여 평탄화된다.Referring to FIG. 1B, the first photosensitive film 5 is formed over the entire surface. At this time, the first photosensitive film 5 is planarized by viscosity.
제1c도를 참조하면, 상기 제1감광막(5)을 에치백(etch back)하고 잔존하는 상기 제1감광막(5)을 제거하여 상부면을 평탄화된 제1절연막(4)을 형성한다. 이때, 상기 평탄화된 제1절연막(4)형성 공정은 상기 제1감광막(5)과 제1절연막(4)의 식각비 차이를 고려하여 실시된 것이다. 그 다음에, 상기 제1절연막(4) 상부에 제2절연막(6)을 형성한다. 이때 상기 제2절연막(6)은 금속층간절연이 가능한 두께를 고려하여 형성된 것이다. 그 다음에, 상기 제2절연막(6)상부에 제2감광막(7)패턴을 형성한다. 이때, 상기 제2감광막(7)패턴은 상기 제1금속층(3)패턴을 노출시킬 수 있는 비아콘택마스크(via contack mask)(도시안됨)를 이용한 노광 및 현상공정으로 형성된 것이다.Referring to FIG. 1C, the first photoresist film 5 is etched back and the remaining first photoresist film 5 is removed to form a first insulating film 4 having a flat top surface. In this case, the process of forming the planarized first insulating layer 4 is performed in consideration of the difference in etching ratio between the first photosensitive layer 5 and the first insulating layer 4. Next, a second insulating film 6 is formed on the first insulating film 4. At this time, the second insulating film 6 is formed in consideration of the thickness of the metal interlayer insulation. Next, a second photosensitive film 7 pattern is formed on the second insulating film 6. In this case, the second photoresist layer 7 pattern is formed by an exposure and development process using a via contact mask (not shown) that may expose the first metal layer 3 pattern.
여기서, 상기 필드산화막(3)상부에 형성된, 제1, 2절연막(4,6)두께 "t1"은 상기 반도체기판(1)상부에 형성된 제1, 2절연막(4,6)두께 "t2"보다 얇게 형성된 것이다.Here, the thickness "t1" of the first and second insulating films 4 and 6 formed on the field oxide film 3 is the thickness "t2" of the first and second insulating films 4 and 6 formed on the semiconductor substrate 1. It is formed thinner.
제1d도를 참조하면, 상기 제2감광막(7)패턴을 마스크로하여 상기 제2절연막(6)과 제1절연막(4)을 식각하여 상기 제1금속층(3)패턴을 노출시키고 상기 제1금속층(3)패턴에 접속되는 제2금속층(8)을 형성함으로써 다층금속배선을 형성한다. 이때, 상기 식각공정은 상기 반도체기판(1)상부에 형성된 절연막(4,6)의 두께를 기준으로 하여 실시된 것이다.Referring to FIG. 1D, the second insulating layer 6 and the first insulating layer 4 are etched using the second photoresist layer 7 as a mask to expose the first metal layer 3 pattern and to expose the first metal layer 3 pattern. Multilayer metal wiring is formed by forming the second metal layer 8 connected to the metal layer 3 pattern. In this case, the etching process is performed based on the thicknesses of the insulating films 4 and 6 formed on the semiconductor substrate 1.
그러나, 상기 필드산화막(2) 상부의 제1금속층(3)패턴은 상기 절연막(4,6)식각공정시 과도식각되어 "A"와 같이 제1금속층(3)패턴과 제2금속층(8)이 단락되거나 또는 완전한 접합이 되지 않는 결함이 있다.However, the first metal layer 3 pattern on the field oxide layer 2 is over-etched during the etching process of the insulating layers 4 and 6, so that the first metal layer 3 pattern and the second metal layer 8 are formed as shown in “A”. There are short circuits or defects that do not result in complete bonding.
따라서, 본 발명은 종래기술의 문제점을 해결하기위하여, 콘택 특성을 향상시키고 콘택공정을 단순화시켜 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 다층금속배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a multi-layered metal wiring which can improve the characteristics and reliability of a semiconductor device by improving contact characteristics and simplifying a contact process.
이상의 목적을 달성하기위한 본 발명의 다층금속배선 형성방법의 특징은, 반도체기판 상부에 필드산화막을 형성하는 단계과, 상기 필드산화막과 반도체기판 상부에 각각 제1금속층패턴을 형성하는 단계과, 상기 제1금속층패턴 측벽에 제1절연막 스페이서를 형성하는 단계과, 전체표면상부에 일정두께 제2절연막을 화학기상증착(CVD : Chemical Vapor Deposition)방법으로 형성하는 단계과, 비아콘택마스크를 이용한 식각공정으로 상기 제2절연막을 식각하여 상기 제1금속층패턴을 노출시키는 단계과, 상기 제1금속층패턴에 접속되는 제2금속층패턴을 형성하는 단계를 포함하는데 있다.In order to achieve the above object, there is provided a method of forming a multilayer metal wiring according to the present invention, comprising: forming a field oxide film on an upper surface of a semiconductor substrate, forming a first metal layer pattern on the field oxide film and an upper surface of the semiconductor substrate, respectively, Forming a first insulating layer spacer on the sidewall of the metal layer pattern, forming a second insulating layer having a predetermined thickness on the entire surface by a chemical vapor deposition (CVD) method, and etching the second contact layer by an etching process using a via contact mask. And etching the insulating film to expose the first metal layer pattern, and forming a second metal layer pattern connected to the first metal layer pattern.
또한, 상기 제1절연막 스페이서와 제2절연막은 실리콘산화막으로 형성되는 것과, 상기 제1절연막 스페이서와 제2절연막을 실리콘질화막으로 형성되는 것과, 상기 제2절연막은 화학기상증착방법 대신에 물리기상증착(PVD : Physical Vapor Deposition)방법으로 형성되는 것이다.In addition, the first insulating film spacer and the second insulating film is formed of a silicon oxide film, the first insulating film spacer and the second insulating film is formed of a silicon nitride film, and the second insulating film is a physical vapor deposition instead of a chemical vapor deposition method It is formed by (PVD: Physical Vapor Deposition) method.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도를 참조하면, 반도체기판(1)상부에 펄드산화막(2)을 형성한다. 그리고 상기 반도체기판(1)과 필드산화막(2)의 상부에 각각 제1금속층(3)패턴을 형성한다.Referring to FIG. 2A, a pulp oxide film 2 is formed on the semiconductor substrate 1. The first metal layer 3 pattern is formed on the semiconductor substrate 1 and the field oxide film 2, respectively.
제2b도를 참조하면, 전체표면상부에 제1절연막(4)을 일정두께 형성한다. 이때, 상기 제1절연막(4)은 실리콘산화막이나 실리콘질화막으로 형성된 것이다. 그리고, 상기 제1절연막(4)은 물리기상증착(PVD : Physical Vapor Deposition)방법으로 형성된 것이다.Referring to FIG. 2B, a first insulating film 4 is formed on the entire surface at a predetermined thickness. In this case, the first insulating film 4 is formed of a silicon oxide film or a silicon nitride film. In addition, the first insulating layer 4 is formed by a physical vapor deposition (PVD) method.
제2c도를 참조하면, 상기 제1절연막(4)을 비등방성식각하여 상기 제1금속층(4)패턴 측벽에 제1절연막 스페이서(4A)를 형성한다.Referring to FIG. 2C, the first insulating layer 4 is anisotropically etched to form first insulating layer spacers 4A on the sidewalls of the first metal layer 4 pattern.
제2d도를 참조하면, 전체표면상부에 물리기상증착방법이나 화학 기상증착방법으로 제2절연막(6)을 일정두께 형성한다. 이때, 상기 제2절연막(6)은 실리콘질화막이나 실리콘산화막으로 형성된 것이다.Referring to FIG. 2D, the second insulating film 6 is formed on the entire surface by a physical vapor deposition method or a chemical vapor deposition method. In this case, the second insulating film 6 is formed of a silicon nitride film or a silicon oxide film.
여기서, 사이 제2절연막(6)은 상기 제1절연막 스페이서(4A)로 인하여 상기 제2b도의 제1절연막(4)을 형성했을때와 달리 굴곡이 심하지 않고 완만하여 후공정에서 별도의 평탄화공정을 실시하지 않아도 된다.Here, the second insulating film 6 is not smoothly bent, unlike the case of forming the first insulating film 4 of FIG. 2B due to the first insulating film spacer 4A. You do not have to do it.
일반적으로, 상기 평탄화공정은 감광막을 이용한 식각공정후에 상기 감광막을 제거할때 상기 감광막의 잔유물이 남는 것을 방지하고 후공정으로 형성된 물질의 단차피복성을 향상시키기 위하여 사용된다.In general, the planarization process is used to prevent the residue of the photoresist film from remaining after removing the photoresist film after the etching process using the photoresist film and to improve the step coverage of the material formed by the post process.
제2e도를 참조하면, 상기 제2절연막(6)상부에 감광막패턴(7)을 형성한다. 이때, 상기 감광막패턴(7)은 상기 제1금속층(3)패턴을 노출시키는 비아콘택마스크(도시안됨)를 이용한 식각공정으로 형성된 것이다.Referring to FIG. 2E, a photosensitive film pattern 7 is formed on the second insulating film 6. In this case, the photoresist pattern 7 is formed by an etching process using a via contact mask (not shown) exposing the pattern of the first metal layer 3.
여기서, 상기 필드산화막(2)상부에 형성된 제1금속층(3)패턴상부의 제2절연막(6) 두께 "t1"은 상기 반도체기판(1)상부에 형성된 제1금속층(3)패턴 상부의 제2절연막(6)두께 "t2, t3"와 같게 형성된 것이다.Here, the thickness “t1” of the second insulating film 6 on the patterned first metal layer 3 formed on the field oxide film 2 is formed on the first metal layer 3 formed on the semiconductor substrate 1. 2 The insulating film 6 is formed to have the same thickness "t2, t3".
제2f도를 참조하면, 상기 감광막패턴(7)을 마스크로하여 상기 제2절연막(6)을 식각함으로써 상기 제1금속층(3)패턴을 노출시키고 제1금속층(3)패턴에 접속되는 제2금속층(8)을 형성하여 다층 금속배선을 형성한다.Referring to FIG. 2F, a second insulating layer 6 is etched using the photoresist pattern 7 as a mask to expose the first metal layer 3 pattern and to be connected to the first metal layer 3 pattern. The metal layer 8 is formed to form a multilayer metal wiring.
이상에서 설명한 바와같이 본 발명에 따른 다층금속배선 형성방법은, 제1금속층배턴의 측벽에 제1절연막 스페이서를 형성하여 후공정에서 별도의 평탄화공정없이 제2절연막을 일정두께 형성하고 비아콘택마스크를 이용한 식각공정으로 콘택을 형성한 다음, 상기 제1금속층패턴에 접속되는 제2금속층을 형성함으로써 안정된 다층 금속배선을 형성하고 공정을 단순화시켜 반도체소자의 특성, 생산성 및 신뢰성을 향상시키는 잇점이 있다.As described above, in the method of forming the multi-layered metal wiring according to the present invention, the first insulating layer spacer is formed on the sidewall of the first metal layer baton, and the second insulating layer is formed to have a predetermined thickness without a planarization step in a later step, and a via contact mask is formed. After forming the contact by the etching process, a second metal layer connected to the first metal layer pattern is formed to form a stable multilayer metal wiring and to simplify the process, thereby improving the characteristics, productivity and reliability of the semiconductor device.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019920010443A KR950011554B1 (en) | 1992-06-16 | 1992-06-16 | Multi-layer metalizing method of semiconductor device |
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| KR1019920010443A KR950011554B1 (en) | 1992-06-16 | 1992-06-16 | Multi-layer metalizing method of semiconductor device |
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| KR950011554B1 true KR950011554B1 (en) | 1995-10-06 |
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