JP2000031271A - Manufacture of multi-layer interconnection semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a normal operation for a semiconductor device even if misalignment occurs in a lithography process. SOLUTION: A first insulating film 12 is deposited on a substrate wafer 11, a second insulating film 13 lower in etching rate than the first insulating film 12 is deposited on the first insulating film 12, a contact hole is provided, and a first wiring 15 is formed. A first insulating film 16 is deposited on the second insulating film 13 where the first wiring 15 is provided, and a second insulating film 17 lower in etching rate than the first insulating film 12 is formed on the first insulating film 16. Resist 18 is applied onto the second insulating film 17 and then patterned. The second insulating film 17 is etched through an RIE method for the formation of a contact hole. The first insulating film 16 is etched through an RIE method for the formation of a contact hole. The resist 18 is removed, and a second wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an insulating film formed between multilayer wiring layers.

[0002]

2. Description of the Related Art In the prior art, an insulating film having a small difference in etching rate with respect to etching conditions is used as an insulating film between multilayer wiring layers. FIG. 2 is a cross-sectional view of a manufacturing process of a conventional semiconductor device having a multilayer wiring. A first silicon oxide film 22 is deposited on a substrate wafer 21 (see FIG. 2).
(A)). Resist 23 on first silicon oxide film 22
Is applied to form a pattern (FIG. 2B). Etching is performed to form a contact hole (FIG. 2C).
The resist 23 is removed, and a first wiring 24 is formed (FIG. 2D). A second silicon oxide film 25 is deposited on the first silicon oxide film 22 on which the first wiring 24 is formed (FIG. 2E). A resist 26 is applied on the second silicon oxide film 25 to form a pattern (FIG. 2F).
Etching is performed to form a contact hole. The resist 26 is removed, and a second wiring 27 is formed. The second wiring 27 is connected to only the lower first wiring 24 to be electrically connected through the formed contact hole. However, when the pattern is displaced from the first wiring 24 and etching is performed, a contact hole is formed up to the lower first silicon oxide film 22 (FIG. 2G). When the resist 26 is removed and the second wiring 27 is formed, it is also electrically connected to the underlying substrate wafer 21 (FIG. 2 (h)).

[0003]

As described above, in a method of manufacturing a semiconductor device of a multi-layer wiring using an insulating film having a small difference in etching rate as an insulating film between the multi-layer wiring layers, the lithography for forming a contact hole is performed by an electric lithography. If the lower wiring metal that is to be electrically conductive is misaligned and etched, a contact hole is further formed to the lower insulating film, and wiring and wiring or wiring that should not normally be electrically conductive And the substrate wafer conducts. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a multi-layer wiring semiconductor device in which normal operation is ensured even when misalignment occurs in lithography.

[0004]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a multilayer wiring, comprising: depositing a first insulating film on a substrate wafer; and forming the first insulating film on the first insulating film. Depositing a second insulating film having a lower etching rate, applying a resist on the second insulating film to form a pattern, etching the first and second insulating films, Forming a hole, removing a resist, forming a first wiring, and depositing a third insulating film on the second insulating film on which the first wiring is formed; A step of applying a resist on the third insulating film to form a pattern, a step of etching the third insulating film to form a contact hole, and a step of removing the resist and forming a second wiring It is characterized by having.

A step of depositing a first insulating film on the substrate wafer; a step of depositing a second insulating film having a lower etching rate than the first insulating film on the first insulating film; Applying a resist on the second insulating film to form a pattern, etching the first and second insulating films to form a contact hole, removing the resist, and forming a first wiring Forming, depositing a third insulating film on the second insulating film on which the first wiring is formed, and etching on the third insulating film more than the third insulating film. Depositing a fourth insulating film having a low rate, applying a resist on the fourth insulating film to form a pattern, and etching the fourth insulating film to form a contact hole; , Etching the third insulating film to form a contact hole A step of, the resist is removed, it is characterized by comprising a step of forming a second wiring.

Further, the third insulating film is etched,
The step of forming the contact hole stops on the second insulating film. According to the present invention, in forming an insulating film between multilayer wiring layers, after depositing the first insulating film, depositing a second insulating film having a lower etching rate than the first insulating film with respect to contact etching conditions. Accordingly, even when misalignment in lithography occurs, it is possible to prevent further etching of the lower insulating film, so that a multi-layered wiring semiconductor device in which normal operation is ensured can be obtained.

[0007]

Embodiments of the present invention will be described below. FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device having a multilayer wiring according to a first embodiment of the present invention.
A silicon oxide film 12 as a first insulating film is formed on a substrate wafer 11 by CVD (Chemical Vapor Depletion).
A silicon nitride film 13, which is a second insulating film, is deposited on the silicon oxide film 12 by a plasma CVD method or the like (FIG. 1A). A resist 14 is applied on the silicon nitride film 13 to form a pattern (FIG. 1B). RIE (Reactive I
The silicon nitride film 13 is etched by “on etching” (FIG. 1C). Next, the silicon oxide film 12 is etched by RIE (FIG. 1D).
The resist 14 is removed, and a first aluminum wiring 15 is formed by sputtering or the like (FIG. 1E). The wiring may be made of any conductor other than aluminum, such as tungsten. On the silicon nitride film 13 on which the first aluminum wiring 15 is formed, a silicon oxide film 16 as a third insulating film is deposited by a CVD method or the like (FIG. 1F). A resist 18 is applied on the silicon oxide film 16 to form a pattern (FIG. 1G). The silicon oxide film 16 is etched by RIE (FIG. 1H). No contact hole is formed in the silicon nitride film 13, which is the lower second insulating film. The resist 18 is removed. A second aluminum wiring 19 is formed by sputtering or the like (FIG. 1).
(I)). In FIG. 1 (g), there is a misalignment with the pattern of the lower first aluminum wiring 15 to be conducted.

[0008] By depositing a silicon nitride film 13 as a second insulating film on a silicon oxide film 12 as a first insulating film, a silicon oxide film as a third insulating film deposited on the silicon nitride film 13 is formed. When the film 16 is etched, the underlying silicon nitride film 13 is not etched, and no contact hole is formed. Therefore, conduction with the substrate wafer 11 that is not normally electrically conducted can be prevented, and normal operation can be ensured. Also, since the width of the wiring can be reduced,
Fine wiring processing becomes possible, and the chip size can be reduced.

A description will be given of a manufacturing process of the semiconductor device according to the second embodiment of the present invention. The silicon oxide film 16 as the third insulating film is replaced with the first aluminum wiring 15
The steps up to the step of depositing on the silicon nitride film 13 as the second insulating film on which is formed (FIG. 1F) are the same as the steps of manufacturing the semiconductor device according to the first embodiment.

A silicon nitride film as a fourth insulating film is deposited on the silicon oxide film as a third insulating film by a plasma CVD method or the like. A resist is applied on the silicon nitride film as the fourth insulating film to form a pattern. The silicon nitride film serving as the fourth insulating film is etched by RIE. The silicon oxide film as the third insulating film is etched by RIE. No contact hole is formed in the second silicon nitride film, which is the lower second insulating film. The resist is removed. A second aluminum wiring is formed by sputtering or the like.

When the third and fourth insulating films are etched by depositing a silicon nitride film as a second insulating film on a silicon oxide film as a first insulating film,
Since the lower second silicon nitride film is not etched and no contact hole is formed, conduction with a substrate wafer which is not normally electrically conducted can be prevented, and normal operation can be ensured. Further, since the width of the wiring can be reduced, fine wiring processing can be performed, and the chip size can be reduced.

In a second embodiment of the present invention,
By repeating the step of depositing the silicon nitride film on the silicon oxide film, a semiconductor device with more multilayer wiring can be manufactured. It is possible to prevent conduction with a lower wiring that is not normally electrically conducted, and normal operation can be ensured.

[0013]

According to the present invention, after depositing a first insulating film, a second insulating film having an etching rate lower than that of the first insulating film with respect to contact etching conditions is deposited.
By etching each of the insulating film and the first insulating film, no contact hole is formed up to the underlying insulating film,
It is possible to prevent conduction with a lower layer wiring or a substrate wafer which is not normally electrically conducted, and a semiconductor device in which normal operation is ensured can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device having a multilayer wiring according to the present invention.

FIG. 2 is a sectional view of a manufacturing process of a semiconductor device having a multilayer wiring according to a conventional technique.

[Description of Signs] 11 ... Substrate wafer 12, 16 ... Silicon oxide film 13 ... Silicon nitride film 14, 17 ... Resist 15 ... First aluminum wiring 18 ... Second aluminum wiring 21 ... Substrate wafer 22 ... First oxidation Silicon film 23, 26 resist 24 first aluminum wiring 25 second silicon oxide film 27 second aluminum wiring

Claims (3)

[Claims] A step of depositing a first insulating film on a substrate wafer; a step of depositing a second insulating film having a lower etching rate than the first insulating film on the first insulating film; A step of applying a resist on the second insulating film to form a pattern; a step of etching the second insulating film to form a contact hole; and a step of etching the first insulating film to form a contact hole. Removing the resist to form a first wiring; and forming a third wiring on the second insulating film on which the first wiring is formed.
Depositing an insulating film, applying a resist on the third insulating film to form a pattern, etching the third insulating film to form a contact hole, and removing the resist. Forming a second wiring, and a method of manufacturing a semiconductor device having a multilayer wiring. A step of depositing a first insulating film on the substrate wafer; a step of depositing a second insulating film having a lower etching rate than the first insulating film on the first insulating film; A step of applying a resist on the second insulating film to form a pattern; a step of etching the second insulating film to form a contact hole; and a step of etching the first insulating film to form a contact hole. Removing the resist to form a first wiring; and forming a third wiring on the second insulating film on which the first wiring is formed.
Depositing a fourth insulating film having a lower etching rate than the third insulating film on the third insulating film; and depositing a resist on the fourth insulating film. Applying, forming a pattern; etching a fourth insulating film to form a contact hole; etching a third insulating film to form a contact hole; removing the resist; Forming a second wiring. 2. A method of manufacturing a semiconductor device having a multilayer wiring, comprising: 3. The semiconductor of claim 1 or 2, wherein the step of etching the third insulating film to form a contact hole stops on the second insulating film. Device manufacturing method.