JP2001127154A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device which reduces an inter-wiring capacitance, and which is hard to generate a short-circuit failure between adjacent wirings or a connection failure of the wiring to an interlayer connecting metal plug, if misalignment occurs. SOLUTION: A first metal layer 103 for a first wiring and a second metal layer 104 for forming an interlayer connecting metal plug are deposited on an insulation film 2, and they are etched by using the same first resist as a mask, to form a shape of the first wiring, by using a second resist as a mask, only the second metal layer 104 is etched to form the interlayer connecting metal plug, whereby the interlayer connecting metal plug is reliably formed on the first wiring. Next, an interlayer insulation film 108 is formed so as to form porosities 107 relative to the first metal layer 103 as the first wiring, and the surface is flattened to form a second wiring connected to a plug composed of the second metal layer 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Recently, semiconductor processing techniques for fine processing of wiring and elements have been advanced, and the performance of integrated circuit devices has been improved. However, with the integration of the wiring, the delay of the signal line in the wiring has come to control the speed of the device. Therefore, for example, as a material of an interlayer insulating film used for a device having a design rule of 0.25 μm or later, a material having a low relative dielectric constant, for example, fluorine is doped instead of the conventional SiO ₂ (relative dielectric constant ε = 4.3). SiOF
(Ε = 3.5) and SiO: C containing organic matter (ε = 2.
8 to 3.2) have been proposed. However, these materials have problems in terms of hygroscopicity and heat resistance, so that it is difficult to actually manufacture a device.

[0003] For this reason, air (ε
= 1.0), for example, Japanese Unexamined Patent Publication No. Sho 62-5643 discloses a technique for intentionally providing holes formed by the method to lower the relative dielectric constant between wirings. Such a device using holes is promising because the capacitance between wirings, which is particularly affected by the delay of the signal line, can be significantly reduced. FIG. 13 shows this technique.
This will be described with reference to FIG.

FIG. 13 is a sectional view showing the structure of a conventional semiconductor device. In FIG. 13, holes 6 are formed between wirings 3 and 4 in insulating substance 2 provided on semiconductor substrate 1.
Are provided between the wirings 4 and 5, respectively. As a material of the insulating substance 2, SiO ₂ is used. Wiring 3
The capacitance between the wiring 3 and the wiring 4 can be regarded as a series capacitance of the capacitance between the wiring 3 and the hole 6, the capacitance of the hole 6, and the capacitance between the hole 6 and the wiring 4. Compared to the relative dielectric constant of the material SiO ₂ of the insulating substance 2 other than the holes 6 and 7,
The relative permittivity of the air holes 6 and 7 formed by air is about 1/4.

[0005] Therefore, by providing holes, the capacitance between adjacent wirings can be reduced, and signal delay between adjacent wirings can be suppressed, so that a semiconductor device that can operate at high speed can be realized.

[0006]

However, when the structure shown in FIG. 13 is applied to a semiconductor device having a multilayer wiring structure, a problem arises according to the conventional manufacturing method. This problem will be described together with the conventional manufacturing method with reference to FIGS. FIGS. 14A and 14B and FIGS. 15A to 15C are process cross-sectional views illustrating a method for manufacturing a conventional semiconductor device having a multilayer wiring structure.

First, as shown in FIG. 14A, an insulating film 12, a first wiring 13, and an interlayer insulating film 14 are sequentially formed on a semiconductor substrate 11. Plasma C as interlayer insulating film 14
Since SiO ₂ deposited by the VD method is used, the step coverage is poor. That is, the ratio of the deposited film thickness of the wiring gap 15 which is the region between the first wirings 13 to the deposited film thickness of the flat portion is low. As a result, holes 16 are formed in the interlayer insulating film 14 in the wiring gap 15.

However, since the step coverage (the above-mentioned ratio) does not become 0%, not all of the wiring gaps 15 become voids, and the interlayer insulating film 14 exists between the wirings. Therefore, for the purpose of reducing the relative dielectric constant between the wirings, a method of further lowering the deposition rate of the interlayer insulating film 14 in the wiring gap 15 to lower the relative dielectric constant can be considered. In this case, the holes 16 occupy a larger area.

Next, as shown in FIG. 14B, a part of the interlayer insulating film 14 is removed by using a resist etch back method, a chemical mechanical polishing (CMP) method, or the like, thereby forming an interlayer insulating film. 14 is flattened.

Next, as shown in FIG. 15A, an interlayer connection hole 17 is formed using photolithography and dry etching. Here, the wiring width 1 of the first wiring 13
8 and the diameter 19 of the interlayer connection hole 17 are the same size,
Consider a case where an alignment shift of only the shift size 20 occurs in photolithography. In this case,
The interlayer connection hole 17 at a portion shifted from the upper surface of the first wiring 13 due to the alignment shift is formed deeper than the position of the upper surface of the first wiring 13. Therefore, the interlayer connection holes 17 are integrated with the holes 16.

Next, as shown in FIG. 15 (b), an interlayer connection metal 21 made of tungsten is formed as a plug in the interlayer connection hole 17 by using the CVD method. Since tungsten formed by CVD as the interlayer connection metal 21 has a good step coverage, the tungsten shown in FIG.
Not only the interlayer connection holes 17 in FIG.
Also fill in.

As a result, the adjacent first wirings 13 are connected to each other via the interlayer connection metal 21 formed in the portion where the holes 16 were formed, thereby causing a short circuit failure.
If the relative dielectric constant in the wiring gap 15 is to be further reduced, the holes 16 occupy a larger area, so that a short circuit failure is more likely to occur.

On the other hand, the displacement dimension 20 in FIG.
Is larger, the connection area between the first wiring 13 and the metal 21 for interlayer connection buried in the interlayer connection hole 17 becomes smaller, so that the first wiring 13 and the metal 21 for interlayer connection become smaller. Connection failure occurs. In particular, interlayer insulating film 1
In the case where an organic material is used as the material No. 4, the above connection failure is likely to occur.

If an alignment shift occurs and the interlayer connection hole 17 is deeply etched, the first wiring 13 and the semiconductor substrate 11 are connected by the formed interlayer connection metal 21, resulting in a short circuit. Will also occur.

Next, as shown in FIG. 15C, a second wiring 22 connected to the first wiring 13 via the metal 21 for interlayer connection is formed by the metal 21 for interlayer connection and the interlayer insulating film 14. To form on.

In the above-described manufacturing method, when an alignment shift occurs in the photolithography process, the first
As a problem of the above, there is a problem that a connection area between the metal for interlayer connection and the wiring is reduced and a connection failure occurs. As a second problem, when the interlayer connection hole is opened, the interlayer connection hole and the hole are integrated, and a short circuit between the wirings occurs due to the metal for interlayer connection entering the region. Further, when the misalignment occurs and the interlayer connection hole is etched deeply, the wiring is connected to the semiconductor substrate or the lower layer wiring therebelow by the metal for interlayer connection, which causes a problem of short circuit. Occurs. The above problem is
This is likely to occur in the case of devices having design rules in which the wiring width and the interlayer connection hole diameter are the same.

One of the methods for avoiding this problem is as follows:
A method has been proposed in which the metal for interlayer connection is formed before the metal for wiring, and the wiring is formed in a self-aligned manner (Reference: Symp. VLSI Tech. Dig. Tech. Papers.
1999). According to this method, even if the alignment is displaced and slightly protrudes from the wiring, no wiring is formed at that time, so the interlayer connection metal is formed at the displaced position, and the connection with the lower wiring is sufficiently performed. (FIG. 3 (a) of the same document).

However, in this method, when the distance between the wirings is reduced, there is a problem that the distance between the protruding interlayer connection metal and the adjacent wiring is locally reduced, and the reliability is adversely affected. There is.

In order to solve this problem, it is necessary to form an alignment-free metal for interlayer connection with the lower wiring.

In view of the above problems, the present invention can prevent poor connection between wiring and a metal plug for interlayer connection, can prevent short-circuiting between adjacent wirings due to misalignment, and can reduce the capacitance between wirings. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of suppressing the size of the semiconductor device.

[0021]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a second wiring on a first wiring via an interlayer insulating film; A method of manufacturing a semiconductor device in which a first wiring and a second wiring are connected by a metal plug for connection, wherein the first wiring is formed on an insulating film.
Depositing a first metal layer for wiring, depositing a second metal layer on the first metal layer, and applying a first resist to the surface of the second metal layer to form a first metal layer. Patterning into the shape of the wiring of the second, and the second using the first resist as a mask
Forming a first wiring by etching the first metal layer and etching the first metal layer, and after removing the first resist, applying a second resist and processing into a shape of the first wiring Patterning so as to cover the region of the formed second metal layer where the metal plug for interlayer connection is to be formed, and etching the second metal layer only using the second resist as a mask to leave the second metal layer. A step of forming an interlayer connection metal plug made of a metal layer, a step of forming an interlayer insulating film over the entire surface after removing the second resist, a step of exposing an upper surface of the interlayer connection metal plug, Forming a third metal layer on the entire surface after exposing an upper surface of the metal plug for use, and etching the third metal layer into a desired shape to form a second wiring. I do.

According to this manufacturing method, a first metal layer for a first wiring and a second metal layer for forming a metal plug for interlayer connection are deposited, and the same first resist is used as a mask. Then, only the second metal layer is etched using the second resist as a mask to form the metal plug for interlayer connection, thereby forming the metal plug for interlayer connection. The first metal wiring is securely formed on the first wiring without being displaced from the first wiring, and the metal plug for interlayer connection and the first wiring are formed.
Connection failure with the other wiring can be prevented. Further, since the interlayer insulating film is formed after the formation of the metal plug for interlayer connection, there is no need to open an interlayer connection hole in the interlayer insulating film as in the related art. Since the interlayer connection hole is not opened in this manner, misalignment occurs as in the related art, and when the interlayer connection hole is deeply etched, the wiring and the underlying semiconductor substrate or the underlying wiring are formed by the interlayer connection metal. There is no problem such as the occurrence of short circuit due to connection.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, a second wiring is formed on the first wiring via an interlayer insulating film, and the second wiring is formed by a metal plug for interlayer connection penetrating the interlayer insulating film. A method of manufacturing a semiconductor device in which a first wiring and a second wiring are connected, comprising: depositing a first metal layer for a first wiring on an insulating film; Depositing a first hard mask layer, applying a first resist on the surface of the first hard mask layer, and patterning the first hard mask layer into a first wiring shape;
Etching a hard mask layer, embedding an embedding material in portions other than the first resist,
After the resist is removed, a step of applying a second resist and patterning it so as to open a region where a metal plug for interlayer connection is formed, and a step of applying the first resist using the second resist as a mask
Etching the hard mask layer to expose the first metal layer, and removing the second resist, and then plating the exposed surface of the first metal layer by an electrolytic plating method to remove the first metal layer from the plating formation portion. Forming a metal plug for interlayer connection, depositing a second hard mask layer only on the metal plug for interlayer connection, removing a filling material, and forming a first hard mask layer and a second hard mask layer. Forming a first wiring by etching the first metal layer using the hard mask layer as a mask; and forming an interlayer insulating film over the entire surface after removing the first and second hard mask layers. Exposing the upper surface of the metal plug for interlayer connection, and exposing the upper surface of the metal plug for interlayer connection, forming a second metal layer on the entire surface, and etching the second metal layer into a desired shape. First Characterized in that it comprises a step of forming a wiring.

According to this manufacturing method, the first hard mask layer formed on the first metal layer for the first wiring is processed into the shape of the first wiring, and the second resist is used as a mask. Etching the first hard mask layer to expose the first metal layer in a region where the metal plug for interlayer connection is formed, and plating the exposed portion to form a metal plug for interlayer connection;
The first wiring is formed by etching the first metal layer using the first hard mask layer and the second hard mask layer formed only on the metal plug for interlayer connection as a mask, thereby forming the metal for interlayer connection. The plug is securely formed on the first wiring without being shifted from the first wiring, and a poor connection between the metal plug for interlayer connection and the first wiring can be prevented. Further, since the interlayer insulating film is formed after the metal plug for interlayer connection is formed as in claim 1, there is no need to open an interlayer connection hole in the interlayer insulating film as in the related art, and the conventional alignment shift occurs. In addition, when the interlayer connection hole is deeply etched, there is no problem that a short circuit occurs with the lower semiconductor substrate or the lower wiring.

According to a third aspect of the present invention, in the method for manufacturing a semiconductor device according to the first or second aspect, the interlayer insulating film is formed between the first wirings and the metal for interlayer connection. It is characterized in that a hole is formed at a position lower than the upper surface of the plug.

As described above, since the holes are formed between the wirings, the capacitance between the wirings can be reduced. Also, since the interlayer connection hole is not opened in the interlayer insulating film as in the conventional case, the interlayer connection hole and the hole are integrated due to misalignment as in the conventional case, and the metal for the interlayer connection enters the region, thereby causing a short circuit between the wirings. There is no problem that a defect occurs.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In both the following first and second embodiments, a second wiring is formed on a first wiring via an interlayer insulating film, and penetrates through the interlayer insulating film. A method for manufacturing a semiconductor device in which a first wiring and a second wiring are connected by a metal plug for interlayer connection to be described.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. Each drawing is a drawing for each process flow, (a) is a sectional view,
(B) is a top view.

First, referring to FIG. 1, an insulating film 102 (for example, a film thickness of 0.8 μm) is formed on a semiconductor substrate 101, and a first metal layer 103 having a laminated structure of, for example, aluminum and a titanium alloy is formed thereon. (Thickness 0.5 μm), the second metal layer 1 also having a laminated structure of aluminum and a titanium alloy
04 (film thickness: 1.0 μm) are sequentially formed. Here, the first
The metal layer 103 may be made of a material such as copper. Further, the first metal layer 103 and the second metal layer 104 may be formed using different materials or different compositions. Further, the first metal layer 103
When the boundary between the second metal layer 104 and the second metal layer 104 is made of a material such as titanium, the second metal layer 104 can be used as a film for controlling a stop when the second metal layer 104 is etched later.

Next, a first resist 105 is applied on the second metal layer 104, and is patterned into a shape of a first wiring. Next, in FIG. 2, the second metal layer 104 and the first metal layer 103 are patterned by etching using the first resist 105 as a mask. Here, the first metal layer 103 is patterned to form a first wiring.

Next, referring to FIG. 3, after the first resist 105 is peeled off, a second resist 106 is applied, and a pattern is formed so as to cover the second metal layer 103 in the region where the metal plug for interlayer connection is formed. The second resist 106
Is used as a mask to etch second metal layer 104. Here, as described above, a layer of titanium or the like is formed between the first metal layer 103 and the second metal layer 104 and is used as an etching stopper layer, so that only the second metal layer 104 is formed. The control of etching becomes easy. In the step of FIG. 3, when patterning the second resist 106 so as to cover the formation region of the metal plug for interlayer connection, the pattern of the first metal layer 104 and the second metal layer 103 as shown in FIG. Pattern so that it intersects with the pattern. That is, by patterning to a width larger than the wiring width so as not to reach the adjacent wiring, even if there is some misalignment in the width direction of the wiring,
A metal plug for interlayer connection described later can be reliably formed on the first wiring. Needless to say, the interlayer connection metal plug can be reliably formed on the first wiring when the alignment shift occurs in the longitudinal direction of the wiring. Therefore, when the wiring is formed on the XY plane, a defective connection between the interlayer connection metal plug and the first wiring can be prevented even if the alignment shift occurs in any of the X direction and the Y direction. .

After that, the second resist 106 is removed. As a result, as shown in FIG.
Are formed as plugs (metal plugs for interlayer connection) for connecting the first wiring made of the first metal layer 103 and the second wiring in the upper layer. Here, since the first metal layer 103 and the second metal layer 104 are patterned by the same first resist 105 as described above, the second metal layer 104 serving as a plug is formed by the first wiring. Can be formed without being shifted from the first metal layer 103.

Thereafter, a normal interlayer insulating film such as SiO ₂ can be formed. In the present embodiment, however, holes 107 are formed between the first metal layers 103 as shown in FIG. As described above, the interlayer insulating film 108 is formed using, for example, a plasma CVD apparatus.

Thereafter, although not shown, the interlayer insulating film 1 is formed.
08 is planarized by CMP to expose the upper surface of the second metal layer 104 which is a plug, or the interlayer insulating film 1
08 is flattened by etch back to expose the upper surface of the second metal layer 104 which is a plug. After that, the first wiring (the first metal layer 103) and the plug (the second metal layer 1)
04), a third metal layer for forming a second wiring connected through the interlayer insulating film 108 is formed on the entire surface of the interlayer insulating film 108, and the third metal layer is formed using a normal lithography and etching technique. Process into 2 wiring. In the case where the third wiring is provided above the second wiring, the second wiring and the plug thereon are formed in the same manner as the first wiring and the plug, and then the interlayer insulating film and the third wiring are formed. By forming three wirings, a three-layer wiring structure can be formed. In the case of a wiring structure of four or more layers, it can be similarly formed.

The holes 107 shown in FIG.
When the top surface of the second metal layer 104, which is a metal plug for interlayer connection, is exposed by flattening the surface of the substrate 08, it is necessary to form the second metal layer 104 so as not to be exposed. Therefore, when forming the interlayer insulating film 108, the holes 107 are formed at a position lower than the upper surface of the second metal layer 104. This allows
When a third metal layer serving as a second wiring is formed on the entire surface,
It is possible to prevent the third metal layer from invading into the holes 107 to cause a short circuit, and to form the holes 107 reliably.

As described above, according to the present embodiment, the first
A first metal layer 103 for wiring and a second metal layer 104 for forming a metal plug for interlayer connection are deposited, and these are etched using the same first resist 105 as a mask to form a first metal layer 103.
Then, only the second metal layer 104 is etched using the second resist 106 as a mask to form a metal plug for interlayer connection, whereby the metal plug for interlayer connection is formed on the first wiring. It is reliably formed on the first wiring without deviation from the first wiring, and a poor connection between the metal plug for interlayer connection and the first wiring can be prevented.

Further, according to the present embodiment, after forming the metal plug for interlayer connection, the holes 107 are formed between the first wirings.
To form the interlayer insulating film 108 so that
There is no need to open interlayer connection holes in the interlayer insulating film as in the conventional case. Since the interlayer connection hole is not opened in this manner, the interlayer connection hole and the hole are integrated due to misalignment as in the related art, and the metal for interlayer connection enters the region, thereby causing a short-circuit failure between the wirings and the interlayer. When the connection hole is deeply etched, the problem that the wiring and the underlying semiconductor substrate or the underlying wiring are connected by the metal for interlayer connection and short-circuit failure occurs does not occur. In addition, since the holes are integrated with the interlayer connection holes as in the conventional case and the metal for interlayer connection does not enter the holes, the holes 107 between the first wirings can also be reliably formed, and the capacitance between the wirings can be reduced. It is possible to realize a semiconductor device capable of suppressing the operation and operating at high speed.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. Each drawing is a drawing for each process flow, (a) is a sectional view,
(B) is a top view. This embodiment is based on a process using a plating method.

First, in FIG. 6, an insulating film 102 (for example, a film thickness of 0.8 μm) is formed on a semiconductor substrate 101, and a laminated structure of, for example, aluminum and a titanium alloy or a first metal of a copper material is formed thereon. Layer 103 (for example, 0.5 μm in thickness)
To form Next, a first hard mask layer 111 made of, for example, a nitride film is formed. Next, the hard mask layer 11
A first resist 112 is applied on the substrate 1 and patterned into a shape of a first wiring.

Next, referring to FIG. 7, the first hard mask layer 111 is etched using the first resist 112 as a mask.
Next, a temporary filling material 113 is buried in a portion where the first resist 112 pattern does not remain (a portion where the hard mask layer 111 is removed by etching). The filling material 113 is made of an insulator, and may be an oxide film such as SiO ₂ .

Next, in FIG. 8, the first resist 112 is removed. Next, a second resist 114 is applied, and patterning is performed so as to open an area where a metal plug for interlayer connection is to be formed. In the process of FIG. 8, when patterning the second resist 114 so as to open the formation region of the metal plug for interlayer connection, as shown in FIG.
The patterning is performed so that the opening of No. 4 intersects the patterning of the first hard mask layer 111. That is, by patterning the opening so that the width of the opening does not reach the adjacent wiring and is larger than the width of the wiring, even if some misalignment occurs in the width direction of the wiring, the later-described metal plug 115 for interlayer connection will be described. Can be reliably formed on the first wiring. It goes without saying that the interlayer connection metal plug 115 can be surely formed on the first wiring when the alignment shift occurs in the longitudinal direction of the wiring. Therefore,
Assuming that wiring is formed on the XY plane,
Even if the misalignment occurs in any of the Y directions,
Poor connection between the metal plug 115 for interlayer connection and the first wiring can be prevented.

Next, referring to FIG. 9, the first hard mask layer 111 is etched using the second resist 114 as a mask to expose the first metal layer 103. After that, the second resist 114 is removed.

Next, in FIG. 10, electrolytic plating is performed using the first metal layer 103 as an electrode. If the first metal layer 103 is copper, a similar copper material is formed by plating. The plated portion is an interlayer connection metal plug 115 for connecting the first wiring and the second upper wiring. Thereafter, a second hard mask layer 116 made of, for example, a nitride film is formed only on the upper surface of the metal plug 115 for interlayer connection by a known method such as CVD.

Next, in FIG. 11, the embedding material 113 temporarily embedded is removed. After that, the first wiring is formed by etching the first metal layer 103 using the first hard mask layer 111 and the second hard mask layer 116 as a mask.

Next, referring to FIG. 12, the first hard mask 11
The first and second hard masks 116 are removed. Subsequent steps are the same as in the first embodiment, and a normal interlayer insulating film such as SiO ₂ can be formed.
As shown in FIG. 12, holes 107 are formed between the first metal layers 103.
Is formed using, for example, a plasma CVD apparatus.

Thereafter, although not shown, the interlayer insulating film 1 is formed.
08 is flattened by CMP to expose the upper surface of the metal plug 115 for interlayer connection, or the interlayer insulating film 108
Is flattened by etch-back to expose the upper surface of the metal plug 115 for interlayer connection. After that, a second metal layer for forming a second wiring connected to the first wiring (the first metal layer 103) via the metal plug 115 for interlayer connection is formed on the entire surface of the interlayer insulating film 108. Then, the second metal layer is processed into a second wiring by using a usual lithography and etching technique. If the third wiring is provided above the second wiring, the second wiring and the metal plug for interlayer connection thereon are formed in the same manner as the first wiring and the metal plug for interlayer connection described above. After that, by forming an interlayer insulating film and a third wiring, a three-layer wiring structure can be formed. In the case of a wiring structure of four or more layers, it can be similarly formed.

The holes 107 in FIG. 12 are not exposed when the surface of the interlayer insulating film 108 is flattened to expose the upper surface of the metal plug 115 for interlayer connection, as in the first embodiment. Need to be formed. Therefore, when forming the interlayer insulating film 108, the holes 107 are formed at a position lower than the upper surface of the metal plug 115 for interlayer connection. Thus, when the second metal layer serving as the second wiring is formed on the entire surface, it is possible to prevent the second metal layer from entering the holes 107 to cause a short circuit, and to reliably form the holes 107. Can be formed.

As described above, according to the present embodiment, the first
The first hard mask layer 111 formed on the first metal layer 103 for wiring is processed into the shape of the first wiring, and the first hard mask layer 111 is formed using the second resist as a mask.
Is etched to expose the first metal layer 103 in the region where the metal plug 115 for interlayer connection is formed, and the exposed portion is plated to form the metal plug 115 for interlayer connection. Metal plug for interlayer connection 11
The first wiring is formed by etching the first metal layer 103 using the second hard mask layer 116 formed only on the substrate 5 as a mask, thereby forming the metal plug 11 for interlayer connection.
5 is reliably formed on the first wiring without shifting from the first wiring, and can prevent poor connection between the interlayer connection metal plug 115 and the first wiring.

Further, according to the present embodiment, the metal plug 115 for interlayer connection is provided in the first metal layer 10 serving as the first wiring.
Since the exposed portion 3 is formed by plating, it is possible to avoid an increase in connection resistance at a connection portion between the metal plug 115 for interlayer connection and the first wiring.

As in the first embodiment, after the metal plug 115 for interlayer connection is formed, the interlayer insulating film 108 is formed so that the holes 107 are formed between the first wirings. It is not necessary to open the interlayer connection hole in the interlayer insulating film as in the prior art, and the interlayer connection hole and the air hole are integrated due to misalignment as in the conventional case, and the metal for the interlayer connection enters the region, thereby causing a short circuit between the wirings. When the interlayer connection hole is deeply etched, the occurrence of a short circuit between the wiring and the underlying semiconductor substrate or the underlying wiring does not occur. Since the holes are not integrated with the interlayer connection holes unlike the conventional case, the holes 107 between the first wirings can be reliably formed, and the capacitance between the wirings can be reduced.
A semiconductor device capable of high-speed operation can be realized.

In the semiconductor devices manufactured in the first and second embodiments, the planar shape of the metal plug for interlayer connection (104 in FIG. 5 and 115 in FIG. 12) is substantially square. The width of the first wiring (FIGS. 5 and 12)
103) has the same dimensions as the wiring width.

[0052]

According to the method of manufacturing a semiconductor device of the first aspect of the present invention, a first metal layer for a first wiring and a second metal layer for forming a metal plug for interlayer connection are deposited. And etching them using the same first resist as a mask to form a first wiring, and then etching only the second metal layer using the second resist as a mask to form a metal plug for interlayer connection. Thus, the metal plug for interlayer connection is securely formed on the first wiring without being shifted from the first wiring, and a poor connection between the metal plug for interlayer connection and the first wiring can be prevented.

According to the method of manufacturing a semiconductor device of the second aspect of the present invention, the first hard mask layer formed on the first metal layer for the first wiring is processed into the shape of the first wiring. And etching the first hard mask layer using the second resist as a mask to expose the first metal layer in a region where the metal plug for interlayer connection is formed, and plating the exposed portion to form the metal plug for interlayer connection. Is formed, and the first metal layer is etched using the first hard mask layer and the second hard mask layer formed only on the metal plug for interlayer connection as a mask to form a first wiring. The metal plug for interlayer connection is securely formed on the first wiring without being shifted from the first wiring, and a poor connection between the metal plug for interlayer connection and the first wiring can be prevented. In addition, since the metal plug for interlayer connection is formed by plating the exposed portion of the first metal layer serving as the first wiring, the connection resistance at the connection between the metal plug for interlayer connection and the first wiring is reduced. Ascent can be avoided.

Also, in any of the manufacturing methods of claims 1 and 2, since the interlayer insulating film is formed after the formation of the metal plug for interlayer connection, an interlayer connection hole is opened in the interlayer insulating film as in the prior art. No need. Since the interlayer connection hole is not opened in this manner, misalignment occurs as in the related art, and when the interlayer connection hole is deeply etched, the wiring and the underlying semiconductor substrate or the underlying wiring are formed by the interlayer connection metal. There is no problem such as the occurrence of short circuit due to connection.

Further, according to the method of manufacturing a semiconductor device of the third aspect of the present invention, holes are formed between the first wirings and at a position lower than the upper surface of the metal plug for interlayer connection. By forming an interlayer insulating film and thus forming holes between the wirings, the capacitance between the wirings can be reduced. Also, since the interlayer connection hole is not opened in the interlayer insulating film as in the conventional case, the interlayer connection hole and the hole are integrated due to misalignment as in the conventional case, and the metal for the interlayer connection enters the region, thereby causing a short circuit between the wirings. There is no problem that a defect occurs. As described above, since the holes are integrated with the interlayer connection holes and the metal for interlayer connection does not enter the holes as in the related art, the holes between the first wirings can also be reliably formed, and the capacity between the wirings can be reduced. A semiconductor device which can be kept small and can operate at high speed can be realized.

[Brief description of the drawings]

FIG. 1A is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a plan view showing the same from above.

FIG. 2A is a sectional view showing a step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 2B is a plan view of the same as viewed from above.

FIG. 3A is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 3B is a plan view illustrating the same from above.

FIG. 4A is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 4B is a plan view of the same, viewed from above.

FIG. 5A is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 5B is a plan (perspective) view thereof as viewed from above.

FIG. 6A is a process sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention, and FIG. 6B is a plan view showing the same from above.

FIG. 7A is a process sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 7B is a plan view of the same, viewed from above.

FIG. 8A is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 8B is a plan view showing the same from above.

FIG. 9A is a cross-sectional view showing a step in a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 9B is a plan view of the same as viewed from above.

FIG. 10A is a sectional view showing a step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 10B is a plan view of the same as viewed from above.

FIG. 11A is a process sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 11B is a plan view of the same, viewed from above.

FIG. 12A is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention, and FIG. 12B is a plan (perspective) view of the same viewed from above.

FIG. 13 is a sectional view showing the structure of a conventional semiconductor device.

FIG. 14 is a process sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 15 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 insulating film 103 first metal layer 104 second metal layer 105, 106, 112, 114 resist 107 hole 108 interlayer insulating film 111, 116 hard mask layer 113 filling material 115 metal plug for interlayer connection

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 JJ08 JJ18 KK08 KK11 KK18 MM05 NN03 NN19 PP27 QQ08 QQ24 QQ28 QQ31 QQ48 RR29 SS15 XX15 XX24

Claims (3)

[Claims] A first wiring provided on the first wiring via an interlayer insulating film;
Wherein the first wiring and the second wiring are connected by a metal plug for interlayer connection penetrating the interlayer insulating film, wherein the second wiring is formed on the insulating film. Depositing a first metal layer for one wiring; depositing a second metal layer on the first metal layer; applying a first resist to a surface of the second metal layer Patterning the shape of the first wiring, etching the second metal layer using the first resist as a mask, and etching the first metal layer to form the first wiring And after removing the first resist, apply a second resist to form a portion of the second metal layer, which is processed into the shape of the first wiring, in the region where the metal plug for interlayer connection is formed. Patterning so as to cover; Forming the metal plug for interlayer connection consisting of the remaining second metal layer by etching only the second metal layer using the resist as a mask, after removing the second resist, Forming an interlayer insulating film on the entire surface; exposing an upper surface of the metal plug for interlayer connection; exposing an upper surface of the metal plug for interlayer connection; forming a third metal layer on the entire surface; Forming the second wiring by etching the third metal layer into a desired shape. 2. A method according to claim 1, wherein the second wiring is formed on the first wiring via an interlayer insulating film.
Wherein the first wiring and the second wiring are connected by a metal plug for interlayer connection penetrating the interlayer insulating film, wherein the second wiring is formed on the insulating film. Depositing a first metal layer for one wiring, depositing a first hard mask layer on the first metal layer, and depositing a first resist on a surface of the first hard mask layer. Applying a pattern to the shape of the first wiring, etching the first hard mask layer using the first resist as a mask, and filling an embedding material in portions other than the first resist. A step of embedding, a step of applying a second resist after removing the first resist, and patterning so as to open an area where the metal plug for interlayer connection is formed, and a step of using the second resist as a mask Said Etching a first hard mask layer to expose the first metal layer; and removing the second resist, plating the exposed surface of the first metal layer by an electrolytic plating method. Forming the metal plug for interlayer connection composed of the plating formation portion, depositing a second hard mask layer only on the metal plug for interlayer connection, removing the burying material, Forming the first wiring by etching the first metal layer using the first hard mask layer and the second hard mask layer as masks; and removing the first and second hard mask layers. Forming the interlayer insulating film on the entire surface; exposing the upper surface of the metal plug for interlayer connection; exposing the upper surface of the metal plug for interlayer connection; Forming the second metal layer, and etching the second metal layer into a desired shape to form the second wiring. 3. The interlayer insulating film according to claim 1, wherein holes are formed between the first wirings and at a position lower than the upper surface of the metal plug for interlayer connection. 3. The method for manufacturing a semiconductor device according to item 2.