JP2004022694A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device which can effectively form an upper layer wirings in different film thickness and a via plug for electrically connecting the upper layer wirings and lower layer wirings without depending on the thickness of the wiring film of the upper wirings. <P>SOLUTION: An interlayer insulation film including lower layer wirings of the predetermined shapes is formed on a semiconductor substrate, and a first groove aperture and a first hole aperture are simultaneously formed by a half-etching method in the first photolithography process. Thereafter, a second hole aperture overlapping the first groove aperture, and a second groove aperture overlapping the second hole aperture, are simultaneously formed in the second photolithography process. Finally, the upper layer wirings and a via plug for electrically connecting the upper layer wirings and lower layer wirings are formed by filling the first and the second hole apertures with a conductor. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a semiconductor device having an upper wiring, a lower wiring, and a via plug for electrically connecting the upper wiring and the lower wiring, with different wiring thicknesses. And a method for producing the same.
[0002]
[Prior art]
The operation speed of the semiconductor device depends on the wiring resistance and the wiring capacitance. The lower the values of the wiring resistance and the wiring capacitance, the faster the operation speed of the semiconductor device. That is, in order to reduce the wiring resistance, it is necessary to increase the wiring film thickness and the wiring width. On the other hand, in order to reduce the wiring capacitance, it is necessary to reduce the wiring film thickness and increase the distance between adjacent wirings. is there.
[0003]
However, in a semiconductor device having a multilayer wiring structure, with the recent miniaturization of the semiconductor device, the wiring resistance and the wiring capacitance are increasing steadily. Need to meet the conflicting demands for faster speeds.
[0004]
Therefore, as a first related art, a semiconductor device having a cross-sectional structure shown in FIG. 9 has been proposed in order to achieve both miniaturization of the semiconductor device and high operating speed.
[0005]
In the multilayer wiring semiconductor device of FIG. 9, a fine local wiring 101 and a global wiring 102 having a wide pitch are provided in separate layers, respectively.
[0006]
In the local wiring 101 used for the short-distance wiring, the wiring thickness is reduced so that the wiring capacitance is reduced because the wiring capacitance strongly depends on the operation speed of the semiconductor device.
[0007]
On the other hand, in the global wiring 102 used for long-distance wiring, since the operation speed of the semiconductor device strongly depends on the wiring resistance, the wiring film thickness is increased so that the wiring resistance is reduced. The wiring width is large.
[0008]
Also, in each wiring belonging to the local wiring 101 (or the global wiring 102), in order to further improve the performance of the semiconductor device, the wiring width, the wiring interval, and the like are adjusted to optimize the wiring resistance and the wiring capacitance. That is being done. For example, even for wirings belonging to the same global wiring 102, a wiring having a larger wiring width is formed for a wiring whose wiring resistance is desired to be lower than that of other wirings.
[0009]
On the other hand, in the second prior art disclosed in Japanese Patent Application Laid-Open No. 9-321046, upper wirings having different wiring film thicknesses are formed in the same wiring layer.
[0010]
In the second conventional technique shown in FIG. 10, after forming a first silicon oxide film 112 on a silicon substrate 111, a lower layer wiring 113 is formed to cover the first silicon oxide film 112 and the lower layer wiring 113. Thus, second silicon oxide film 114, which is an interlayer insulating film, is formed.
[0011]
Next, a first groove-shaped opening to be the first upper wiring 115 is formed in the second silicon oxide film 114 by a first photolithography step. Thereafter, by a second photolithography step, a second groove-shaped opening to be a second upper wiring 116 having a different wiring thickness from the first upper wiring 115 is formed in the second silicon oxide film 114, A hole-shaped opening serving as a via plug 117 for electrically connecting the upper layer wiring 115 and the lower layer wiring 113 is formed at the same time.
[0012]
Note that, at the time of the second photolithography step, by forming a second groove-shaped opening subsequent to the first groove-shaped opening formed in the first photolithography step, the third upper layer wiring is formed. A groove-like opening 118 is also formed.
[0013]
Finally, a metal such as aluminum is formed on the surface of the second silicon oxide film 114 so as to fill the groove-shaped openings and the hole-shaped openings, and the surface position of the second silicon oxide film 114 is By polishing the metal up to this point, a semiconductor device having a sectional structure shown in FIG. 10 is obtained.
[0014]
In the second prior art, since two or more wirings having different wiring thicknesses are formed in the same wiring layer, the semiconductor device is designed more freely in consideration of the wiring resistance and the wiring capacitance than in the first conventional technology. A high degree of design becomes possible. Therefore, the circuit design was simplified, and the circuit operation speed and the degree of integration of the semiconductor device could be improved.
[0015]
[Problems to be solved by the invention]
However, in the manufacturing method of the second prior art, the upper wiring having a different wiring thickness and the via plug connecting the upper wiring and the lower wiring of one of the upper wirings having the different wiring thickness are formed. Only the method is described, but it is not possible to efficiently form a via plug for electrically connecting the upper layer wiring and the lower layer wiring having different wiring film thicknesses.
[0016]
That is, in the manufacturing method including only the two etching steps described above, it is possible to form the via plug 117 that electrically connects the upper wiring 115 and the lower wiring 113 having one of two different wiring thicknesses. However, it is impossible to form a via plug for electrically connecting the other upper layer wiring 116 and a lower layer wiring (not shown).
[0017]
Further, by increasing the number of photolithography steps, a via plug for electrically connecting the other upper wiring 116 and a lower wiring (not shown) can be formed, but this is not efficient.
[0018]
In an actual semiconductor device, not only are upper wirings having different wiring thicknesses formed, but also upper wirings and lower wirings having different wiring thicknesses are connected by via plugs regardless of the wiring thickness of the upper wirings. It is important to connect and the utility is much higher.
[0019]
Therefore, the present invention provides a semiconductor device which has a higher degree of freedom in design of a semiconductor device in consideration of a wiring resistance and a wiring capacitance depending on the operation speed of the semiconductor device, and has practicality. Therefore, regardless of the thickness of the wiring of the upper wiring, the upper wiring, the lower wiring, and the via plug that electrically connects the upper wiring and the lower wiring are formed more efficiently regardless of the thickness of the wiring of the upper wiring. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can perform the above-described steps.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 according to the present invention, comprises electrically connecting an upper layer wiring having two or more different wiring thicknesses and the upper layer wiring and the lower layer wiring. A first region in which the thinner upper wiring is densely formed, and a thicker upper wiring in the first region. In a semiconductor device having a second region formed more sparsely than an upper wiring, (a) a step of preparing a semiconductor substrate; and (b) a first step having the lower wiring having a predetermined shape. Forming an interlayer insulating film on the semiconductor substrate; (c) forming a second interlayer insulating film so as to cover the first interlayer insulating film; and (d) forming the second interlayer insulating film. Penetrating the upper surface of the insulating film, and extending to the middle depth of the second interlayer insulating film; Simultaneously forming a first groove-shaped opening existing in the region and a first hole-shaped opening existing in the first region; and (e) after the step (d), Simultaneously forming a second hole-like opening overlapping the groove-like opening and a second groove-like opening overlapping the first hole-like opening; and (f) forming the first and second holes. By filling the groove-shaped opening and the first and second hole-shaped openings with a conductor, the upper layer wiring and the via plug for electrically connecting the upper layer wiring and the lower layer wiring are formed. And a process.
[0021]
In the method of manufacturing a semiconductor device according to claim 2, in the step (d), (d-1) a first mask in which a groove-shaped opening and a hole-shaped opening having a predetermined shape are patterned. Forming on the surface of the second interlayer insulating film, and (d-2) half-etching the second interlayer insulating film to a predetermined depth using the first mask as a mask. The step (e) comprises: (e-1) a hole opening having a predetermined shape formed by covering a part of the first groove opening; and the first hole opening. A second mask, which is formed to have a portion overlapping the portion and is patterned with a groove-shaped opening having a width smaller than that of the first groove-shaped opening, is provided on the surface of the second interlayer insulating film. (E-2) forming the first and second holes using the second mask as a mask; Until the mouth portion reaches the lower wiring, the second interlayer insulating film may include the step of etching.
[0022]
In the method of manufacturing a semiconductor device according to claim 3, in the step (e-1), the second mask further forms a groove-shaped opening that does not overlap with the first hole-shaped opening. May be used.
[0023]
In the method of manufacturing a semiconductor device according to claim 4, a plurality of the first groove-shaped openings are formed, and in the step (e-1), the second mask includes the plurality of first grooves. It may completely cover a part of the groove-shaped opening of the above.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments. FIG. 1 is a cross-sectional view showing a part of a semiconductor device according to an example of the present invention.
[0025]
In FIG. 1, a first interlayer insulating film (silicon oxide film or the like) 2 having a thickness of, for example, about 1 μm is formed on a semiconductor substrate 1, and from the outermost surface to the inside of the first interlayer insulating film 2. Lower layer wirings 3 each having a thickness of about 400 nm and made of a conductor such as copper are arranged in a predetermined shape and number.
[0026]
When the lower wiring 3 is made of copper, for example, the silicon nitride film 10 is coated so as to cover the entire surface of the first interlayer insulating film 2 and the lower wiring 3 for the purpose of preventing oxidation of copper and an etching stopper. It must be formed with a thickness of about 50 nm. On the other hand, when the lower wiring 3 is made of, for example, aluminum, the silicon nitride film 10 can be omitted.
[0027]
On the silicon nitride film 10, a second interlayer insulating film (silicon oxide film or the like) 4 is formed. From the outermost surface to the inside of the second interlayer insulating film 4, a first upper layer wiring is formed. (Wiring formed of copper or the like) 5 and a plurality of second upper wirings 6 (wirings formed of copper or the like) having a different thickness from the first upper wiring and a plurality of wirings are formed in a predetermined shape. ing.
[0028]
Here, the thickness of the second interlayer insulating film 4 is about 1 μm, the thickness of the first upper wiring 5 is about 700 nm, and the thickness of the second upper wiring 6 is about 400 nm. Further, as shown in FIG. 1, the first upper layer wiring 5 and the second upper layer wiring 6 may be formed so that not only the wiring film thickness but also the wiring width is different.
[0029]
Further, in the second interlayer insulating film 4, a first via plug 7 for electrically connecting the second upper wiring 6 and the lower wiring 3 and an electric connection between the first upper wiring 5 and the lower wiring 3 are formed. And a second via plug 8 which is electrically connected. Here, the first via plug 7 and the second via plug 8 are formed by filling the hole-shaped opening with a conductor such as copper.
[0030]
In the semiconductor device described above, since the upper wirings 5 and 6 having different wiring film thicknesses and wiring widths are formed, it is possible to design the circuit with high flexibility in consideration of wiring resistance and wiring capacitance. Become.
[0031]
In addition, the above-described semiconductor device is a more practical semiconductor device because the via plugs 7 and 8 for electrically connecting the upper wirings 5 and 6 having different wiring film thicknesses and the lower wiring 3 are formed. I have.
[0032]
For example, in FIG. 1, the second upper layer wiring 6 and the first via plug 7 are designed in a portion where the wiring pitch is to be reduced in design to increase the integration degree, while the portion in which the wiring resistance is desired to be reduced is designed. First, the first upper wiring 5 and the second via plug 8 are designed.
[0033]
Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.
[0034]
First, as shown in FIG. 2, a first interlayer insulating film (silicon oxide film or the like) 2 having a thickness of about 1 μm is formed on a semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method or the like. Then, in the interlayer insulating film 2, lower wirings 3 having a wiring thickness (for example, about 400 nm) from the surface of the interlayer insulating film 2 to a predetermined depth are formed in a predetermined shape and number.
[0035]
Here, the lower wiring 3 forms a groove opening of a predetermined shape in the first interlayer insulating film 2 by, for example, a series of photolithography steps, and embeds copper or the like as a conductor in the groove opening. The conductor is polished by a flattening technique such as CMP (Chemical and Mechanical Polishing) or the like so that the conductor surface is flush with the surface of the first interlayer insulating film 2.
[0036]
Subsequently, as shown in FIG. 3, for example, when the lower wiring 3 is made of copper, the upper surface of the first interlayer insulating film 2 and the lower wiring 3 are covered so as to prevent oxidation of copper. For example, after forming a silicon nitride film 10 or the like with a thickness of about 50 nm, a second interlayer insulating film (silicon oxide film or the like) 4 of about 1 μm is formed on the silicon nitride film 10 by a CVD method or the like. It is formed with a thickness.
[0037]
Here, when the lower wiring 3 is made of aluminum, the silicon nitride film 10 need not be formed.
[0038]
Next, as shown in FIG. 4, a resist (first mask) 11 having a predetermined pattern is formed on the upper surface of the second interlayer insulating film 4.
[0039]
Here, the resist 11 has two types of patterning: a groove-like opening 5a for forming the first upper wiring 5 of FIG. 1 and a hole-like opening 7a for forming the first via plug 7. Have been.
[0040]
After the resist 11 is formed, a first etching process is performed using the resist 11 as a mask. After the etching process, the resist 11 is removed. FIG. 5 shows the state after the step. Here, the process shown in FIGS. 4 and 5 is referred to as a first photolithography process.
[0041]
The etching process in the first photolithography process is a half-etching process, and the etching is stopped inside the second interlayer insulating film 4 so that the first upper wiring 5 has a desired wiring thickness. The etching is stopped by calculating the etching time to a desired depth (in this case, about 700 nm in the thickness of the first upper wiring 5) from the etching rate, and stopping the etching after the elapse of the time. Done.
[0042]
By the first photolithography process, the first groove-like opening 5b of about 700 nm and the first hole-like opening of about the same depth are formed in the second interlayer insulating film 4 having a thickness of about 1 μm. The portion 7b is formed.
[0043]
Next, as shown in FIG. 6, a resist (second mask) 12 having a predetermined pattern is formed on the upper surface of the second interlayer insulating film 4.
[0044]
The resist 12 has two types of patterning, a groove-like opening 6 a for forming the second upper wiring 6 and a hole-like opening 8 a for forming the second via plug 8.
[0045]
At this time, one of the first groove-shaped openings 5b is completely filled with the resist 12, and the other of the first groove-shaped openings 5b is partially filled with the resist 12.
[0046]
Further, a part of the groove-shaped opening 6a is patterned on the resist 12 so as to overlap with the first hole-shaped opening 7b, and the other groove-shaped opening 6a is formed with the first hole-shaped opening 7b. Are patterned on the resist 12 so as not to overlap.
[0047]
After the formation of the resist 12, a second etching process is performed using the resist 12 as a mask, and then the resist 12 is removed. FIG. 7 shows the state after this step. Here, the steps shown in FIGS. 6 and 7 are referred to as a second photolithography step.
[0048]
In the etching process of the second photolithography step, the second upper wiring 6 needs to have a desired wiring film thickness, and the first via plug 7 and the second via plug 8 are connected to the lower wiring 3 respectively. As a result, the under-etched portion of the first groove-shaped opening 5b and the under-etched portion of the first hole-shaped opening 7b formed in the first photolithography step are etched to reach the lower wiring 3. There is a need.
[0049]
For example, if the wiring thickness of the second upper layer wiring 6 is designed to be 400 nm, the time for etching to 400 nm is calculated from the etching rate, and after the etching for the time, the second etching is stopped. Then, the underetched portion 300 nm in the first etching step is etched, and the first hole-shaped opening 7b and the second hole-shaped opening 8b reach the lower wiring 3 (FIG. 7).
[0050]
Next, a conductor 13 such as copper is buried so as to fill each opening formed in the second interlayer insulating film 4.
[0051]
As a method of embedding the conductor 13, a metal barrier layer and a seed layer (not shown) are formed by, for example, a sputtering method, and then the conductor 13 such as copper is filled in each of the openings by a plating method. At this time, at the same time as the conductor 13 is buried in each opening, the conductor 13 is also formed on the surface of the second interlayer insulating film 4. FIG. 8 shows the state after the step.
[0052]
Finally, the conductor 13 is polished by, for example, a CMP method until the upper surface of the second interlayer insulating film 4 and the upper surface of the conductor 13 are flush with each other, and each opening formed in the second interlayer insulating film 4 is formed. The conductor 13 is left only in the portion (FIG. 1).
[0053]
The first groove-shaped opening 5b and the first hole-shaped opening 7b are simultaneously formed by the above series of steps, that is, the first photolithography step (half-etching processing step using the resist 11). A second groove-shaped opening 6b formed so as to overlap the first hole-shaped opening 7b by a second photolithography step (an etching process using the resist 12); and a first groove-shaped opening. By simultaneously forming the second hole-shaped openings 8b formed in the upper and lower wirings 5 and 6 with different wiring thicknesses as shown in FIG. It is possible to efficiently manufacture a semiconductor device having via plugs 7 and 8 for electrically connecting the upper wirings 5 and 6 and the lower wiring 3 irrespective of the thickness of the wiring.
[0054]
For example, in a portion where the wiring pitch is to be reduced to increase the degree of integration (a portion in which the wiring film thickness is thin and the cover margin for the via plug needs to be designed to be small), a second groove is formed after the first hole-shaped opening 7b is formed. The second upper wiring 6 and the first via plug 7 can be formed by forming the opening 6b in an overlapping manner, and a portion where the wiring resistance is desired to be reduced (the wiring thickness or the wiring width is large, In the portion where the cover margin for the via plug needs to be designed to be large), the second hole-like opening 8b is overlapped and formed after the formation of the first groove-like opening 5b, so that the first upper-layer wiring 5 and the second upper-layer wiring 5 are formed. Two via plugs 8 can be formed.
[0055]
Further, in manufacturing the semiconductor device having the structure shown in FIG. 1, when the method described in the second prior art is applied, that is, in a portion where the wiring pitch is narrowed, a groove-shaped opening is formed and then a hole-shaped opening is formed. When the method of forming the portion is applied, the resist for forming the hole-shaped opening is patterned in the step of the groove-shaped opening formed earlier, so that the resist film thickness becomes deep, that is, the aspect ratio is increased. Therefore, there is a problem that it is difficult to form a fine pattern of a resist on a portion with a high degree of integration because the depth of focus is small.
[0056]
However, by adopting the above-described manufacturing method (procedure) of the present invention, that is, a procedure of forming a hole-shaped opening and then forming a groove-shaped opening in a portion where the wiring pitch is narrowed, the above problem is solved. Will be resolved.
[0057]
In addition, wirings having different wiring widths may be adopted as the upper wirings, whereby, for example, it is possible to increase the wiring width of the upper wirings whose wiring resistance is desired to be reduced. Therefore, the wiring film thickness and the wiring width can be freely designed, and the degree of freedom in design is further increased. However, when the CMP method is used for forming the wiring, there is a limitation in increasing the wiring width (lowering the wiring resistance) due to the wiring dishing phenomenon. However, in the method of the present invention, the wiring thickness is increased. By doing so, the resistance of the wiring can be reduced, so that the degree of freedom of design is increased as compared with the related art.
[0058]
In addition, if the manufacturing method (procedure) of the present invention is applied, the dimensions and materials of each member described above need not be limited to these.
[0059]
In the description of the present invention, two wiring layers have been described. However, the present invention is not limited to this, and it is needless to say that the present invention can be applied to a multilayer wiring structure.
[0060]
【The invention's effect】
A method for manufacturing a semiconductor device according to claim 1 of the present invention includes an upper wiring having two or more different wiring thicknesses and two or more via plugs for electrically connecting the upper wiring and the lower wiring. A first region in which the thinner upper wiring is densely formed, and a thicker upper wiring in which the upper wiring is formed more sparsely than the upper wiring in the first region. In the semiconductor device having the second region, (a) preparing a semiconductor substrate; and (b) forming a first interlayer insulating film having the lower wiring having a predetermined shape on the semiconductor substrate. Forming; (c) forming a second interlayer insulating film so as to cover the first interlayer insulating film; and (d) penetrating an upper surface of the second interlayer insulating film, A first groove-shaped opening existing in the second region up to a halfway depth of the second interlayer insulating film; And simultaneously forming a first hole-shaped opening existing in the first region; and (e) after the step (d), a second hole-shaped hole overlapping the first groove-shaped opening. Simultaneously forming an opening and a second groove-like opening overlapping the first hole-like opening; and (f) the first and second groove-like openings, and the first and second groove-like openings. Forming a via plug that electrically connects the upper wiring and the upper wiring with the lower wiring by filling the second hole-shaped opening with a conductor. At the time of design, it is possible to design with a higher degree of freedom in consideration of the wiring resistance and the wiring capacitance depending on the operation speed of the semiconductor device, regardless of the thickness of the wiring film of the upper layer wiring. A via plug that electrically connects to the lower wiring It can be rate formed.
[0061]
In the method for manufacturing a semiconductor device according to claim 2 of the present invention, in the step (d), (d-1) a first pattern in which a groove-shaped opening and a hole-shaped opening having a predetermined shape are patterned. Forming a mask on the surface of the second interlayer insulating film; and (d-2) half-etching the second interlayer insulating film to a predetermined depth using the first mask as a mask. Wherein the step (e) comprises: (e-1) a hole-shaped opening having a predetermined shape formed by covering a part of the first groove-shaped opening; A second mask, which is formed to have a portion overlapping with the opening and is patterned with a groove-shaped opening having a width smaller than that of the first groove-shaped opening, is formed on the second interlayer insulating film. (E-2) forming the first and second holes using the second mask as a mask; A step of etching the second interlayer insulating film until the opening reaches the lower wiring, so that the two photolithography steps allow an upper wiring having a different thickness, a lower wiring, Via plugs for electrically connecting the upper layer wiring and the lower layer wiring can be formed easily and accurately.
[0062]
In the method of manufacturing a semiconductor device according to claim 3 of the present invention, in the step (e-1), the second mask further includes a groove-shaped opening that does not overlap with the first hole-shaped opening. Since the patterning is performed, the second groove-shaped opening serving as an upper wiring that is not electrically connected to the lower wiring can also be formed in the second photolithography step, and a semiconductor device with higher flexibility can be formed. .
[0063]
In a method of manufacturing a semiconductor device according to a fourth aspect of the present invention, a plurality of the first groove-shaped openings are formed, and in the step (e-1), the second mask includes the plurality of the first grooves. Since it completely covers a part of the one grooved opening, the first grooved opening formed in the first photolithography step is electrically connected to the lower wiring. A first groove-shaped opening serving as an upper wiring that is not connected can also be formed, and a semiconductor device having a higher degree of freedom can be formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device of the present invention.
FIG. 2 is a first diagram showing a manufacturing process of the semiconductor device of the present invention.
FIG. 3 is a second diagram showing the manufacturing process of the semiconductor device of the present invention.
FIG. 4 is a third diagram showing the manufacturing process of the semiconductor device of the present invention.
FIG. 5 is a fourth diagram showing the manufacturing process of the semiconductor device of the present invention.
FIG. 6 is a fifth diagram showing the manufacturing process of the semiconductor device of the present invention.
FIG. 7 is a sixth diagram showing the manufacturing process of the semiconductor device of the present invention.
FIG. 8 is a seventh diagram illustrating the manufacturing process of the semiconductor device according to the present invention;
FIG. 9 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first related art.
FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second conventional technique.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor substrate, 2 first interlayer insulating film, 3 lower layer wiring, 4 second interlayer insulating film, 5 first upper layer wiring, 5 b first groove-shaped opening, 6 second upper layer wiring, 6 b second Groove opening, 7 first via plug, 7b first hole opening, 8 second via plug, 8b second hole opening, 10 silicon nitride film, 11, 12
Resist, 13 conductor (copper, etc.).

Claims (4)

An upper wiring having two or more different wiring thicknesses and two or more via plugs for electrically connecting the upper wiring and the lower wiring are provided, and the upper wiring having a smaller thickness is densely formed. A first region and a second region in which the thicker upper wiring is formed more sparsely than the upper wiring in the first region.
(A) preparing a semiconductor substrate;
(B) forming, on the semiconductor substrate, a first interlayer insulating film having the lower wiring having a predetermined shape;
(C) forming a second interlayer insulating film so as to cover the first interlayer insulating film;
(D) a first groove-shaped opening existing in the second region and penetrating an upper surface of the second interlayer insulating film and extending to a certain depth in the second interlayer insulating film; A step of simultaneously forming a first hole-shaped opening present in the region,
(E) After the step (d), simultaneously forming a second hole-like opening overlapping the first groove-like opening and a second groove-like opening overlapping the first hole-like opening. The process of
(F) By filling the first and second groove-shaped openings and the first and second hole-shaped openings with a conductor, the upper wiring and the upper wiring and the lower wiring are separated from each other. Forming the via plug to be electrically connected,
A method for manufacturing a semiconductor device, comprising: The step (d) includes:
(D-1) forming a first mask on which a groove-shaped opening and a hole-shaped opening having a predetermined shape are patterned on the surface of the second interlayer insulating film;
(D-2) half-etching the second interlayer insulating film to a predetermined depth using the first mask as a mask,
The step (e) includes:
(E-1) A hole having a predetermined shape formed by covering a part of the first groove-shaped opening, and a portion overlapping with the first hole-shaped opening. Forming a second mask on the surface of the second interlayer insulating film, a second mask patterned with a groove-like opening narrower than the first groove-like opening,
(E-2) etching the second interlayer insulating film using the second mask as a mask until the first and second hole-shaped openings reach the lower wiring. ,
2. The method for manufacturing a semiconductor device according to claim 1, wherein: 3. The step (e-1), wherein the second mask is further patterned with a groove-shaped opening that does not overlap with the first hole-shaped opening. Manufacturing method of a semiconductor device. A plurality of the first groove-shaped openings are formed,
In the step (e-1), the second mask completely covers a part of the plurality of first groove-shaped openings.
4. The method for manufacturing a semiconductor device according to claim 2, wherein:

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