JPH04307939A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To keep the performance and reliability of a multilayer interconnection high by preventing the width and thickness of the interconnection from falling short of the designed size when patterning the interconnection and by making the interconnection formation surface nearly completely flat, concerning the method for manufacturing a semiconductor device, specifically, the method for making the interconnection formation surface of the semiconductor device having the multilayer interconnection structure flat. CONSTITUTION:In a layer insulation film (3) formed on a first conductive pattern (2), a recess (5) which has such a specified pattern shape as to include a contact hole installation region (4) that has the depth not to reach the bottom of the layer insulation film is made. In the recess (5), a contact hole (6) is formed to expose the surface of the first conductive pattern (2). Then, a second conductor layer is so deposited as to fill the contact hole (6) and the inside of the recess (5) completely. After that, the whole surface is etched to form an upper second conductive pattern (7) which is buried flat in the recess (5) including the contact hole (6) of the layer insulation film (3).

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
In particular, the present invention relates to a method for flattening a wiring formation surface in a semiconductor device having a multilayer wiring structure.

As semiconductor ICs have become highly integrated in recent years, the wiring constituting the circuit has become multilayered, and the width of the wiring has become extremely fine. In such a situation, in order to ensure high quality wiring using fine wiring rules and maintain high reliability of semiconductor ICs, when forming multilayer wiring, it is necessary to reduce the thickness and width of the wiring from the designed dimensions and to prevent shape deterioration. A planarization technique that does not involve such problems is required.

0003

[Prior Art] Multilayer wiring is often used in semiconductor ICs where elements are miniaturized and circuits are highly integrated.
In order to ensure high reliability in such a semiconductor device, it is extremely important to form wiring in each layer constituting the multilayer wiring with high precision according to design rules. Therefore, in multilayer wiring, it is absolutely necessary to flatten the underlying surface on which the wiring is formed.

Conventionally, when forming multilayer wiring based on fine wiring rules, patterning of wiring layers is performed by reactive ion etching (RIE) processing.
The reaction gas includes an etching gas (CCl4 in the case of aluminum or its alloy) and a deposition gas (CCl4 for aluminum or its alloys).
In the case of aluminum or its alloy SiCl4, B
A method of suppressing deterioration of the pattern shape as much as possible has been carried out by using a mixture of Cl3, etc.). In addition, in order to flatten the wiring formation surface, spin-coated SOG (Sp
A method has been used in which the recesses between the wirings are filled with an in-on-glass (in-on-glass) film.

[0005]

[Problems to be Solved by the Invention] However, in the above-mentioned conventional wiring layer patterning method, the formation of wiring layers due to fluctuations in the ratio of the above-mentioned etching gas and deposition gas in the reaction gas, a decrease in etching selectivity with respect to the resist, etc. The problem is that the thickness and width of the wiring pattern are reduced from the design dimensions, and especially in LSIs where wiring rules are miniaturized, the performance and reliability of the wiring are significantly reduced due to the reduction in thickness and width. was there.

[0006] Furthermore, in the conventional planarization method using SOG spin coating, the thickness of the SOG accumulated in areas where the wiring spacing is narrow differs from that where the wiring spacing is wide, so that planarization is partially insufficient. Particularly in LSIs, etc., where wiring rules are miniaturized, there is a problem that the upper layer wiring is likely to have insufficient film thickness or breakage due to insufficient step coverage on the stepped portion, and the performance and reliability of the wiring will be significantly reduced. was occurring.

Accordingly, the present invention aims to avoid reduction in width and thickness from design dimensions when patterning wiring, and to flatten the wiring formation surface almost completely, thereby maintaining a high level of performance and reliability of multilayer wiring. purpose.

[0008]

[Means for Solving the Problems] FIG. 1 is a schematic cross-sectional view for explaining the principle of the present invention. In the figure, 1 is a lower insulating film, 2 is a lower layer first conductive pattern (for contact of first layer wiring). 3 is an interlayer insulating film, 4 is a contact hole arrangement region, 5 is a trench, 6 is a contact hole, and 7 is an upper second conductive layer (second conductor layer) buried in the trench including the contact hole. layer embedded wiring). As shown in the same figure, the above-mentioned problem involves a process of forming an interlayer insulating film (3) on a substrate having a first conductive pattern (2), and a step of forming an interlayer insulating film (3) on a substrate having a first conductive pattern (2). A groove (5) having a predetermined pattern shape that includes the conductive pattern (2) and the contact hole arrangement region (4) on the conductive pattern (2) and having a depth that does not reach the bottom of the interlayer insulating film (3) is formed. and forming a contact hole (6) exposing the surface of the first conductive pattern (2) in the contact hole arrangement region (4) in the groove (5) of the interlayer insulating film (3). a step of forming;
The contact hole (6) is formed on the interlayer insulating film (3).
and depositing a second conductive layer that completely fills the inside of the groove (5), and etching the second conductive layer by anisotropic dry etching means to remove the upper surface of the interlayer insulating film (3). The second conductive pattern (7) of the upper layer is flatly buried in the groove (5) including the contact hole (6) of the interlayer insulating film (3) by etching the entire surface until it is completely exposed. ), or patterning the second conductive layer along the groove of the interlayer insulating film to fill the groove including the contact hole of the interlayer insulating film, and filling the groove of the interlayer insulating film with a surface of the interlayer insulating film. This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes one or both of the steps of forming a second conductive pattern in the upper layer that projects upward.

[0009]

[Operation] That is, in the present invention, the upper conductive pattern (for example, the upper conductive layer (wiring) (7)) is connected to the interlayer insulating film (
3) Grooves (5) that meet the design rules formed on the surface of
When patterning the upper layer wiring (7), the upper layer wiring (7) can be buried flat or higher than flat.
Avoid reducing reliability due to loss of width or thickness by preventing parts necessary for maintaining quality from coming into contact with etching gas. Also, at least upper layer wiring other than the top layer (7)
In this case, the upper surface of the wiring (7) embedded in the groove (5) and the upper surface of the interlayer insulating film (3) are formed so as to be located on almost the same plane, so that the surface on which the wiring in the upper layer is formed is The surface is almost completely flat without any stepped portions, and there is no further deterioration in the quality of the upper layer wiring due to insufficient coverage.

[0010] Through the above steps, a multilayer wiring having high yield and high reliability is formed.

[0011]

[Embodiment] The present invention will be specifically described below with reference to an embodiment of the present invention with reference to schematic process cross-sectional views shown in FIGS. 2 and 3.

Refer to FIG. 2(a) When forming a multilayer wiring such as an LSI by the method of the present invention, a semiconductor substrate 10 on which elements (not shown) are formed is used.
A lower layer insulating film 11 is formed on the lower layer insulating film 11, and a first layer Al wiring (contact pad portion shown) 12 made of, for example, pure Al or an Al alloy is led out through a contact hole (not shown) on the lower layer insulating film 11. First, a first interlayer insulating film 13 made of PSG or the like and having a thickness of about 1.5 μm is formed on the processed substrate by the CVD method. The thickness (t1) of this first interlayer insulating film 13 is greater than or equal to the sum of the thickness that satisfies the interlayer dielectric strength and the thickness required for the second layer wiring embedded in this first interlayer insulating film. stipulated in

Referring to FIG. 2(b), control etching is then performed by ordinary photolithography using reactive ion etching (RIE) using [CF4+CHF3] gas as the etching means, and the first interlayer insulating film 13 is etched with a first
Contact hole formation region 14 for layered Al wiring 12
A first groove 15 having a pattern shape corresponding to the pattern shape of the second layer wiring including, for example, a width of 1 μm and a depth of about 0.8 μm is formed. Here, the width and depth (d) of the first groove 15 are the width and thickness (d) required for the second layer wiring.
t2). Further, the contact pad portion is formed to have a width approximately two to three times the wiring width as usual.

Note that R1 in the figure indicates the first resist mask formed during the photolithography described above. Refer to FIG. 2(c) Next, the first groove 15 of the first interlayer insulating film 13 is etched by photolithography using the same etching means as described above.
The first layer Al wiring 1 is formed in the contact hole formation region 14 within the
A first contact hole 16 exposing the upper surface of 2 (contact pad portion) is formed. In the figure, R2 indicates the second resist mask formed during the photolithography.

Referring to FIG. 2(d), a film having a thickness of about 1 μm is then deposited on the first interlayer insulating film 13 by a normal bias sputtering method to completely fill the first contact hole 16 and the first groove 15. Second A
A layer 117 (containing an Al alloy) is deposited.

Referring to FIG. 2(e), a chlorine-based gas such as CCl4 is used as the etching gas.
Etching back is performed by RIE using a method until the upper surface of the first interlayer insulating film 13 is completely exposed, and the inside of the first groove 15 including the first contact hole 16 of the first interlayer insulating film 13 is etched back. , a second layer buried Al wiring 17 whose upper surface is substantially flat with the upper surface of the first interlayer insulating film 13 is formed.

Referring to FIG. 3A, next, on the first interlayer insulating film 13 having the second layer buried Al wiring 17, a film corresponding to the sum of the interlayer dielectric strength and the thickness required for the third layer wiring as described above is applied. For example, a second interlayer insulating film 18 having a thickness of about 1.5 μm is formed.

Referring to FIG. 3(b), the second layer wiring and the third layer wiring of the second interlayer insulating film 18 are
A region corresponding to the pattern of the third layer wiring, including the contact hole forming region 19 with the layer wiring, is formed with a width of 1 μm and a depth corresponding to the width and thickness necessary for the third layer wiring, for example, by the same photolithography method as described above. The second layer of about 0.8μm
A groove 20 is formed. In the figure, R3 indicates the third resist mask.

Referring to FIG. 3(c), a contact hole formation region for the second layer Al buried wiring 17 is formed in the second trench 20 formed in the second interlayer insulating film 18 by the same photolithography method as described above. A second contact hole 21 is formed in 19 to expose a contact pad portion of the second layer buried Al wiring 17. Then, as shown in FIG. In the figure, R4 indicates the fourth resist mask.

Referring to FIG. 3(d), the fourth resist mask R4 is removed, and the inside of the second groove 20 including the second contact hole 21 is completely etched on the second interlayer insulating film 18. For example, a third Al (including Al alloy) layer 122 with a thickness of about 1 μm is buried.
Then, the third Al layer 122 is patterned by ordinary photolithography using RIE using a chlorine-based gas such as CCl4 as an etching means, so that the lower part is inside the second interlayer insulating film 18. , and the second layer A is buried in the second contact hole 21.
A third layer Al wiring 22 connected to the buried wiring 17 is formed, and a multilayer wiring structure having three layers of Al wiring is completed.

Note that the reason why the third layer Al wiring 22 was patterned by photolithography rather than by an etch-back method is that this third layer Al wiring 22 is the top layer wiring, and it is intentionally not completely buried. This is because there was no need to include it.

Further, in the above embodiment, the grooves 15, 20
Although the formation of the contact holes 16, 21, etc. was carried out first, and the formation of the contact holes 16, 21, etc. was carried out later, these orders may be reversed. As is clear from the description of the above embodiments, according to the present invention, when forming a multilayer wiring structure, the upper layer wiring, for example (1
7) (22) etc. are buried in the grooves (15) (20) formed in the interlayer insulating film (13) (18) etc. to form flat or higher than flat upper layer wiring (17) (22).
When patterning, etc., portions necessary for maintaining quality such as the upper layer wiring (17), (22), etc. are not brought into contact with the etching gas. Therefore, there is no loss in width or thickness of the upper layer wiring (17), (22), etc. that would impair its performance, and its reliability is ensured.

[0023] Also, at least upper layer wiring other than the top layer (
17), the wiring (1) embedded in the groove (15)
7) Since the upper surface of the interlayer insulating film (13) is embedded in the interlayer insulating film (13) so that the upper surface of the interlayer insulating film (13) is located almost on the same plane, the surface on which the upper layer wiring (22) will be formed will have a stepped portion. This results in an almost completely flat surface with no traces, and there is no further deterioration in the quality of the upper layer wiring (22) due to insufficient coverage.

[0024]

[Effects of the Invention] As explained above, according to the present invention, the cross-sectional shape necessary for ensuring the quality of wiring in multilayer wiring is secured as designed, and deterioration of wiring quality due to insufficient coverage of wiring layers is prevented. do not have. Therefore, the present invention greatly contributes to improving the yield and reliability of semiconductor devices having a multilayer wiring structure.

[Brief explanation of drawings]

[Figure 1] Schematic sectional view for explaining the principle of the present invention

[Figure 2]
Schematic process cross-sectional diagram of one embodiment of the method of the present invention (Part 1)

[Figure 3] Schematic process cross-sectional diagram of one embodiment of the method of the present invention (Part 2)

[Explanation of symbols]

1 Lower insulating film 2 Lower layer first conductive pattern (first layer wiring) 3
Interlayer insulating film 4 Contact hole formation region 5 Groove 6 Contact hole

Claims (1)

[Claims] 1. A step of forming an interlayer insulating film (3) on a substrate having a first conductive pattern (2), and forming the first conductive pattern (2) on the interlayer insulating film (3). A step of forming a groove (5) having a predetermined pattern shape that includes the upper contact hole arrangement region (4) and having a depth that does not reach the bottom of the interlayer insulating film (3);
) in the groove (5) of the contact hole arrangement area (
4) forming a contact hole (6) exposing the surface of the first conductive pattern (2), and forming the contact hole (6) and the groove (5) on the interlayer insulating film (3); The upper surface of the interlayer insulating film (3) is completely exposed by depositing a second conductive layer that completely fills the inside of the interlayer insulating film (3) and dry etching the second conductive layer with anisotropy. The interlayer insulating film (3
) The groove (5) including the contact hole (6)
The upper layer second conductive pattern (
7) forming a step, or patterning the second conductive layer along the groove of the interlayer insulating film to fill the groove including the contact hole of the interlayer insulating film; 1. A method of manufacturing a semiconductor device, comprising the step of forming a second conductive pattern in an upper layer protruding from a surface.