JPH05226475A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05226475A
JPH05226475A JP2514292A JP2514292A JPH05226475A JP H05226475 A JPH05226475 A JP H05226475A JP 2514292 A JP2514292 A JP 2514292A JP 2514292 A JP2514292 A JP 2514292A JP H05226475 A JPH05226475 A JP H05226475A
Authority
JP
Japan
Prior art keywords
wiring layer
insulating film
contact hole
contact
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2514292A
Other languages
Japanese (ja)
Inventor
Masanori Obata
正則 小畑
Akimasa Fujiki
謙昌 藤木
Toshimi Endou
豪美 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2514292A priority Critical patent/JPH05226475A/en
Publication of JPH05226475A publication Critical patent/JPH05226475A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a method of forming a contact hole stable and excellent in quality in a semiconductor device provided with laminated wiring layers. CONSTITUTION:When a first wiring layer 3 and a third wiring layer 7 separated from each other by a first interlayer insulating film 4 and a second interlayer insulating film 6 communicating with each other are directly connected together, a dummy contact hole 9 used only for connecting the wiring layers 3 and 7 together is provided to the first interlayer insulating film 4, and a second wiring layer and a dummy wiring layer 8 are formed at the same time. By this setup, overetching at the formation of contact holes caused by an aspect ratio difference between contact holes and the disconnection of a conductive layer inside a contact hole can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、三層以上の配線層を
有する半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having three or more wiring layers.

【0002】[0002]

【従来の技術】近年、LSIの高集積化、高機能化の傾
向はとどまる所を知らず、これを実現するためにパター
ンの微細化が進められるとともに、LSIを構成する配
線層数も増加の一途をたどってきている。このような多
層構造をもつデバイスでは当然ながら表面の段差が大き
く、種々の不良の原因となっており、このような段差を
低減するために種々の改良がなされてきている。
2. Description of the Related Art In recent years, there has been no end to the trend toward higher integration and higher functionality of LSIs. To achieve this, finer patterns have been advanced, and the number of wiring layers that make up LSIs has also increased. Is following. A device having such a multilayer structure naturally has a large step difference on the surface, which causes various defects, and various improvements have been made in order to reduce such a step difference.

【0003】図4は従来の半導体装置におけるコンタク
ト孔部の構造を示す断面図である。図において、1は半
導体素子が形成されている半導体基板、2は半導体基板
1上に形成されたシリコン酸化膜よりなる下地絶縁膜、
3は下地絶縁膜2上に形成された導電層であるアルミ膜
よりなる第1の配線層、4は第1の配線層3上に形成さ
れたシリコン酸化膜よりなる第1の層間絶縁膜、5は第
1の層間絶縁膜4上に形成されたアルミ膜よりなる第2
の配線層、6は第2の配線層5上に形成されたシリコン
酸化膜よりなる第2の層間絶縁膜、7はアルミ膜よりな
る第3の配線層、10は第2の配線層5上の第2の層間
絶縁膜6に設けられた第3の配線層7のためのコンタク
ト孔、11は第1の配線層3上の第1および第2の層間
絶縁膜4,6に渡って設けられた第3の配線層7のため
のコンタクト孔である。
FIG. 4 is a sectional view showing the structure of a contact hole portion in a conventional semiconductor device. In the figure, 1 is a semiconductor substrate on which semiconductor elements are formed, 2 is a base insulating film made of a silicon oxide film formed on the semiconductor substrate 1,
3 is a first wiring layer made of an aluminum film which is a conductive layer formed on the base insulating film 2, 4 is a first interlayer insulating film made of a silicon oxide film formed on the first wiring layer 3, Reference numeral 5 denotes a second aluminum film formed on the first interlayer insulating film 4.
Wiring layer, 6 is a second interlayer insulating film made of a silicon oxide film formed on the second wiring layer 5, 7 is a third wiring layer made of an aluminum film, and 10 is on the second wiring layer 5. A contact hole for the third wiring layer 7 provided in the second interlayer insulating film 6, and 11 provided over the first and second interlayer insulating films 4 and 6 on the first wiring layer 3. This is a contact hole for the formed third wiring layer 7.

【0004】次に、以上のようにして構成される半導体
装置のコンタクト孔部の製造方法を図5(a)〜(d)
に従って順次説明する。まず、所定処理を施して半導体
基板1に半導体素子を形成する(図示なし)。その後、
半導体基板1上にCVD法等によりシリコン酸化膜を形
成し、下地絶縁膜2とする。この下地絶縁膜2上にスパ
ッタ法等によりアルミ膜を形成し、写真製版およびエッ
チング法等によって第1の配線層3を形成する。この第
1の配線層3と半導体素子とは下地絶縁膜2に設けられ
たコンタクト孔(図示なし)を介して接続されている
(図5(a))。次に、全面にCVD法等によりシリコ
ン酸化膜を形成し、第1の層間絶縁膜4とする(図5
(b))。次に、スパッタ法等によりアルミ膜を形成
し、写真製版およびエッチング法等によって第2の配線
層5を形成する。この第2の配線層5と第1の配線層3
とは第1の層間絶縁膜4に設けられたコンタクト孔(図
示なし)を介して接続されている。(図5(c))。次
に、全面にCVD法等によりシリコン酸化膜を形成し、
第2の層間絶縁膜6とする(図5(d))。次に、第2
の配線層5上の第2の層間絶縁膜6にコンタクト孔10
を、また第1の配線層3上の第1の層間絶縁膜4と第2
の層間絶縁膜6に渡ってコンタクト孔11を、写真製版
およびエッチング法等によって、同時に形成する(図5
(e))。その後、図4に示すようにスパッタ法等によ
り全面にアルミ膜を形成し、写真製版およびエッチング
法等によって第3の配線層7を形成する。
Next, a method of manufacturing a contact hole portion of a semiconductor device configured as described above will be described with reference to FIGS.
Will be sequentially described. First, a predetermined process is performed to form a semiconductor element on the semiconductor substrate 1 (not shown). afterwards,
A silicon oxide film is formed on the semiconductor substrate 1 by the CVD method or the like to form the base insulating film 2. An aluminum film is formed on the underlying insulating film 2 by the sputtering method or the like, and the first wiring layer 3 is formed by the photolithography and the etching method or the like. The first wiring layer 3 and the semiconductor element are connected to each other via a contact hole (not shown) provided in the base insulating film 2 (FIG. 5A). Next, a silicon oxide film is formed on the entire surface by a CVD method or the like to form the first interlayer insulating film 4 (FIG. 5).
(B)). Next, an aluminum film is formed by the sputtering method or the like, and the second wiring layer 5 is formed by the photolithography and the etching method or the like. The second wiring layer 5 and the first wiring layer 3
Are connected to each other via a contact hole (not shown) provided in the first interlayer insulating film 4. (FIG.5 (c)). Next, a silicon oxide film is formed on the entire surface by a CVD method or the like,
The second interlayer insulating film 6 is used (FIG. 5D). Then the second
Of the contact hole 10 in the second interlayer insulating film 6 on the wiring layer 5 of
And the first interlayer insulating film 4 on the first wiring layer 3 and the second
A contact hole 11 is formed at the same time across the interlayer insulating film 6 by the photolithography and the etching method (FIG. 5).
(E)). After that, as shown in FIG. 4, an aluminum film is formed on the entire surface by the sputtering method or the like, and the third wiring layer 7 is formed by the photolithography and the etching method or the like.

【0005】[0005]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、図4に示すように第3
の配線層7と第1の配線層3および第2の配線層5とを
電気的に接続するために層間絶縁膜4,6にコンタクト
孔10,11を設ける際、第1の配線層3上の層間絶縁
膜は第1の層間絶縁膜4と第2の層間絶縁膜6との2層
よりなり、第2の配線層5上の層間絶縁膜は第2の層間
絶縁膜6よりなるため、第1の配線層3上の層間絶縁膜
厚は第2の配線層5上の層間絶縁膜厚より厚くなる。そ
のため、第1の配線層3上のコンタクト孔11と第2の
配線層5上のコンタクト孔10におけるアスペクト比
(コンタクト孔における開口幅に対する深さの比)を比
べると、第1の配線層3上のコンタクト孔11の方が大
きくなる。これらのことから、第3の配線層7の形成時
にはコンタクト孔11内で断線がおこりやすい。また、
2つのコンタクト孔10,11は同工程を経て形成され
るため、第2の配線層5上のコンタクト孔10はコンタ
クト孔11の形成時にオーバーエッチングされることに
なり、特性の良い半導体装置が得られないといった問題
点があった。
Since the conventional semiconductor device is constructed as described above, the third semiconductor device shown in FIG.
When the contact holes 10 and 11 are provided in the interlayer insulating films 4 and 6 to electrically connect the wiring layer 7 of the first wiring layer 7 to the first wiring layer 3 and the second wiring layer 5, Since the interlayer insulating film of 2 is composed of two layers of the first interlayer insulating film 4 and the second interlayer insulating film 6, and the interlayer insulating film on the second wiring layer 5 is composed of the second interlayer insulating film 6, The interlayer insulating film thickness on the first wiring layer 3 is thicker than the interlayer insulating film thickness on the second wiring layer 5. Therefore, comparing the aspect ratio (ratio of the depth to the opening width of the contact hole) of the contact hole 11 on the first wiring layer 3 and the contact hole 10 on the second wiring layer 5, the first wiring layer 3 The upper contact hole 11 becomes larger. For these reasons, disconnection is likely to occur in the contact hole 11 when the third wiring layer 7 is formed. Also,
Since the two contact holes 10 and 11 are formed through the same process, the contact hole 10 on the second wiring layer 5 is over-etched when the contact hole 11 is formed, and a semiconductor device having excellent characteristics can be obtained. There was a problem that it could not be done.

【0006】この発明は上記のような問題点を解消する
ためになされたもので良好でかつ安定した電気的接続を
得ることのできる3層以上の積層配線層を有する半導体
装置の製造方法を提供することを目的とする。
The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device having three or more laminated wiring layers capable of obtaining good and stable electrical connection. The purpose is to do.

【0007】[0007]

【課題を解決するための手段】この発明に係る半導体装
置の製造方法は、連接する複数の絶縁膜が介在して互い
に離隔する導電層間をコンタクトにより直接接続する場
合、当該複数絶縁膜の各絶縁膜1層毎にコンタクト孔を
形成して当該各絶縁膜の上部に接する各導電層と同時に
上記直接接続のためのみのダミーコンタクトを形成し、
これら各ダミーコンタクトを順次接続して上記離隔導電
層間を電気的に接続するようにしたものである。
In the method of manufacturing a semiconductor device according to the present invention, when a plurality of insulating films that are connected to each other are used to directly connect conductive layers that are separated from each other by a contact, each insulating film of the plurality of insulating films is connected. A contact hole is formed for each layer of the film, and a dummy contact for only the direct connection is formed at the same time as each conductive layer in contact with the upper part of each insulating film.
These dummy contacts are sequentially connected to electrically connect the separated conductive layers.

【0008】[0008]

【作用】この発明の半導体装置の製造方法においては、
連接する複数の絶縁膜が介在して互いに離隔する導電層
間をコンタクトにより直接接続する場合、当該複数絶縁
膜の各絶縁膜1層毎にコンタクト孔を形成して当該各絶
縁膜の上部に接する各導電層と同時に上記直接接続のた
めのみのダミーコンタクトを形成し、これら各ダミーコ
ンタクトを順次接続して上記離隔導電層間を電気的に接
続するようにしたので同時に形成するコンタクト孔は常
にアスペクト比の等しいもとなる。したがって、アスペ
クト比の異なるコンタクト孔を同時に形成することによ
って生ずるオーバーエッチングや、さらにコンタクト孔
内のコンタクトの断線を防止することが出来る。
According to the method of manufacturing the semiconductor device of the present invention,
When the conductive layers that are separated from each other by interposing a plurality of insulating films that are connected to each other are directly connected by a contact, a contact hole is formed in each insulating film of each of the plurality of insulating films to contact each upper part of the insulating films. At the same time as forming the dummy contacts for the direct connection at the same time as the conductive layer and connecting the dummy contacts in order to electrically connect the isolated conductive layers, the contact holes formed at the same time always have the aspect ratio of Equal to the source. Therefore, it is possible to prevent over-etching caused by simultaneously forming contact holes having different aspect ratios, and disconnection of contacts in the contact holes.

【0009】[0009]

【実施例】実施例1 以下、この発明の一実施例を図を用いて説明する。な
お、従来の技術の説明と重複する部分については適宜そ
の説明を省略する。
Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the description of the part overlapping the description of the conventional technique will be appropriately omitted.

【0010】図1はこの発明の一実施例の半導体装置の
コンタクト孔部の構造を示す断面図であり、図において
1〜7は従来例におけるものと同等のものである。8は
第1の配線層3上に形成され、第2の配線層と同時に形
成されるアルミ膜よりなるダミー配線層であり、第1の
配線層3と第3の配線層7とを接続するためにのみ用い
られる中継配線層である。
FIG. 1 is a sectional view showing the structure of a contact hole portion of a semiconductor device according to an embodiment of the present invention. In the figure, 1 to 7 are equivalent to those in the conventional example. Reference numeral 8 is a dummy wiring layer formed on the first wiring layer 3 and formed at the same time as the second wiring layer, which is made of an aluminum film, and connects the first wiring layer 3 and the third wiring layer 7. It is a relay wiring layer used only for.

【0011】図2は図1の半導体装置の製造工程を示す
断面図である。この図2(a),(b)に示す工程は従
来例の図5(a),(b)に示す工程と同じであり、そ
の詳細な説明は省略する。
FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device of FIG. The steps shown in FIGS. 2A and 2B are the same as the steps shown in FIGS. 5A and 5B of the conventional example, and detailed description thereof will be omitted.

【0012】次に、第1の層間絶縁膜4の第1の配線層
3上にあたる領域部に少なくとも2個のコンタクト孔9
を充分な近さに並べて形成する。このコンタクト孔9
は、第1の配線層3と第3の配線層7とを接続するため
にのみ用いられるダミー配線層8用である(図1
(c))。次に、スパッタ法等によりアルミ膜を形成
し、写真製版およびエッチング法等によって第2の配線
層5およびダミー配線層8を形成する。この第2の配線
層5と第1の配線層3とは第1の層間絶縁膜4に設けら
れたコンタクト孔(図示なし)を介して接続されている
(図2(d))。次に、全面にCVD法等によりシリコ
ン酸化膜を形成し、第2の層間絶縁膜6とする(図2
(e))。次に、第2の配線層5上とダミー配線層8上
の第2の層間絶縁膜6にコンタクト孔10,12を形成
する(図2(f))。その後、図1に示すようにスパッ
タ法等によりアルミ膜を形成し、写真製版およびエッチ
ング法等によって第3の配線層7を形成する。
Next, at least two contact holes 9 are formed in the region of the first interlayer insulating film 4 which is on the first wiring layer 3.
Are formed close to each other. This contact hole 9
Is for the dummy wiring layer 8 used only for connecting the first wiring layer 3 and the third wiring layer 7 (FIG. 1).
(C)). Next, an aluminum film is formed by the sputtering method or the like, and the second wiring layer 5 and the dummy wiring layer 8 are formed by the photolithography and the etching method. The second wiring layer 5 and the first wiring layer 3 are connected to each other via a contact hole (not shown) provided in the first interlayer insulating film 4 (FIG. 2 (d)). Next, a silicon oxide film is formed on the entire surface by the CVD method or the like to form the second interlayer insulating film 6 (FIG. 2).
(E)). Next, contact holes 10 and 12 are formed in the second interlayer insulating film 6 on the second wiring layer 5 and the dummy wiring layer 8 (FIG. 2 (f)). Thereafter, as shown in FIG. 1, an aluminum film is formed by the sputtering method or the like, and the third wiring layer 7 is formed by the photolithography and the etching method or the like.

【0013】このとき、この発明によるコンタクト孔1
2のアスペクト比は図4に示した従来のコンタクト孔1
1よりも小さくなり、かつ同時に形成するコンタクト孔
10のアスペクト比と等しくなるので、コンタクト孔内
での断線を防止でき、同時に形成するコンタクト孔10
のオーバーエッチングも防止できるので良好なコンタク
ト孔の形成が出来、特性の良い半導体装置の製造方法が
得られる。
At this time, the contact hole 1 according to the present invention
The aspect ratio of 2 is the conventional contact hole 1 shown in FIG.
Since it is smaller than 1 and is equal to the aspect ratio of the contact hole 10 formed at the same time, disconnection in the contact hole can be prevented and the contact hole 10 formed at the same time.
Since over-etching can be prevented, a good contact hole can be formed, and a semiconductor device manufacturing method with excellent characteristics can be obtained.

【0014】実施例2 上記実施例1ではダミー配線層8用のコンタクト孔9を
少なくとも2個形成した場合を示したが図3に示すよう
にコンタクト孔9が1個の場合でもダミー配線層8を形
成でき、上記実施例1と同様の効果を奏する。
Embodiment 2 In Embodiment 1 described above, the case where at least two contact holes 9 for the dummy wiring layer 8 are formed is shown. However, as shown in FIG. 3, even if there is one contact hole 9, the dummy wiring layer 8 is formed. Can be formed, and the same effect as that of the first embodiment can be obtained.

【0015】実施例3 また、上記実施例1ではダミー配線層8用のコンタクト
孔9を少なくとも2個形成した場合を示したが、このコ
ンタクト孔9の形状をドーナツ状としても、上記実施例
1と同様の効果を奏する。
Third Embodiment In the first embodiment, the case where at least two contact holes 9 for the dummy wiring layer 8 are formed is shown. However, even if the contact holes 9 have a donut shape, Has the same effect as.

【0016】実施例4 上記実施例1,2,3では配線層としてアルミ膜を用い
た場合を示したがアルミ合金でもよい。また、層間絶縁
膜としてシリコン酸化膜を用いた場合を示したがシリコ
ン窒化膜等他の絶縁膜であっても良い。上記いずれの場
合であっても上記実施例と同様の効果を奏する。
Embodiment 4 In the above Embodiments 1, 2, and 3, the case where an aluminum film is used as the wiring layer is shown, but an aluminum alloy may be used. Although the case where the silicon oxide film is used as the interlayer insulating film is shown, other insulating films such as a silicon nitride film may be used. In any of the above cases, the same effect as that of the above embodiment can be obtained.

【0017】実施例5 上記実施例1では2層の層間絶縁膜にわたってコンタク
トを設ける場合を示したが、これが3層以上の場合も同
様にしてダミー配線層を順次積み重ねて接続することに
よって上記実施例1と同様の効果を奏する。
Fifth Embodiment In the first embodiment described above, the case where the contact is provided over the two layers of the interlayer insulating film has been described. However, when the number of contacts is three or more, the dummy wiring layers are sequentially stacked and connected in the same manner as described above. The same effect as in Example 1 is obtained.

【0018】更に、半導体基板1上に形成された半導体
素子およびその上に形成された下地絶縁膜を請求の範囲
でいうそれぞれ導電層および絶縁膜の対象に含めてこの
発明を適用することもできる。
Further, the present invention can be applied by including the semiconductor element formed on the semiconductor substrate 1 and the base insulating film formed thereon as the target of the conductive layer and the insulating film respectively in the claims. ..

【0019】[0019]

【発明の効果】以上のようにこの発明では、連接する複
数の絶縁膜が介在して互いに離隔する導電層間をコンタ
クトにより直接接続する場合、当該複数絶縁膜の各絶縁
膜1層毎にコンタクト孔を形成して当該各絶縁膜の上部
に接する各導電層と同時に上記直接接続のためのみのダ
ミーコンタクトを形成し、これら各ダミーコンタクトを
順次接続して上記離隔導電層間を電気的に接続するよう
にしたのでコンタクト孔間のアスペクト比の差異に起因
するコンタクト孔形成時におけるオーバーエッチングお
よびコンタクト孔内での導電層の断線を防止でき、良好
でかつ安定した電気特性を有する半導体装置の製造方法
が得られるという効果がある。
As described above, according to the present invention, when a plurality of insulating films connected to each other are used to directly connect conductive layers separated from each other by a contact, a contact hole is provided for each insulating film of the plurality of insulating films. And forming dummy contacts only for the direct connection at the same time as forming the conductive layers in contact with the upper portions of the insulating films, and sequentially connecting the dummy contacts to electrically connect the isolated conductive layers. Therefore, it is possible to prevent overetching at the time of contact hole formation and disconnection of the conductive layer in the contact hole due to the difference in aspect ratio between the contact holes, and to provide a method for manufacturing a semiconductor device having good and stable electrical characteristics. It has the effect of being obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例の半導体装置のコンタクト
孔部の構造を示す断面図である。
FIG. 1 is a sectional view showing a structure of a contact hole portion of a semiconductor device according to an embodiment of the present invention.

【図2】図1に示すこの発明の半導体装置の製造工程を
示す断面図である。
FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device of the invention shown in FIG.

【図3】この発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.

【図4】従来の半導体装置のコンタクト孔部の構造を示
す断面図である。
FIG. 4 is a sectional view showing a structure of a contact hole portion of a conventional semiconductor device.

【図5】図4に示す従来の半導体装置の製造工程を示す
断面図である。
FIG. 5 is a cross-sectional view showing a manufacturing process of the conventional semiconductor device shown in FIG.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 下地絶縁膜 3 第1の配線層 4 第1の層間絶縁膜 5 第2の配線層 6 第2の層間絶縁膜 7 第3の配線層 8 ダミー配線層 9 ダミー配線層用コンタクト孔 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Base insulating film 3 First wiring layer 4 First interlayer insulating film 5 Second wiring layer 6 Second interlayer insulating film 7 Third wiring layer 8 Dummy wiring layer 9 Dummy wiring layer contact hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に絶縁膜と導電層とをそれ
ぞれ所定のパターンで複数層交互に形成し、上記絶縁膜
にコンタクト孔を形成して当該絶縁膜の上部に接する導
電層と同時に上記当該絶縁膜の下部に接する導電層との
電気的接続のためのコンタクトを上記コンタクト孔に形
成するようにした半導体装置の製造方法において、 連接する複数の絶縁膜が介在して互いに離隔する導電層
間を上記コンタクトにより直接接続する場合、当該複数
絶縁膜の各絶縁膜1層毎にコンタクト孔を形成して当該
各絶縁膜の上部に接する各導電層と同時に上記直接接続
のためのみのダミーコンタクトを形成し、これら各ダミ
ーコンタクトを順次接続して上記離隔導電層間を電気的
に接続するようにしたことを特徴とする半導体装置の製
造方法。
1. A plurality of insulating films and conductive layers are alternately formed on a semiconductor substrate in a predetermined pattern, and contact holes are formed in the insulating film to simultaneously form the conductive layer in contact with the upper portion of the insulating film. In a method of manufacturing a semiconductor device, wherein a contact for electrically connecting to a conductive layer in contact with a lower portion of the insulating film is formed in the contact hole, a conductive layer separated from each other with a plurality of insulating films connected to each other is interposed. When the above-mentioned contacts are directly connected to each other, a contact hole is formed for each insulating film of the plurality of insulating films, and a dummy contact only for the direct connection is formed at the same time as each conductive layer contacting the upper part of each insulating film. A method of manufacturing a semiconductor device, wherein the dummy contacts are formed and are sequentially connected to electrically connect the separated conductive layers.
JP2514292A 1992-02-12 1992-02-12 Manufacture of semiconductor device Pending JPH05226475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2514292A JPH05226475A (en) 1992-02-12 1992-02-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2514292A JPH05226475A (en) 1992-02-12 1992-02-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05226475A true JPH05226475A (en) 1993-09-03

Family

ID=12157738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2514292A Pending JPH05226475A (en) 1992-02-12 1992-02-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05226475A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7075704B2 (en) 2003-03-19 2006-07-11 Seiko Epson Corporation Test-element-provided substrate, method of manufacturing the same, substrate for electro-optical device, electro-optical device, and electronic apparatus
US7095550B2 (en) 2003-03-13 2006-08-22 Seiko Epson Corporation Substrate having a planarization layer and method of manufacture therefor, substrate for electro-optical device, electro-optical device, and electronic apparatus
US7211826B2 (en) 2003-08-28 2007-05-01 Samsung Sdi Co., Ltd. Organic electroluminescent display
US7538342B2 (en) 2005-07-14 2009-05-26 Samsung Electronics, Co., Ltd. Flat panel display and method for fabricating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095550B2 (en) 2003-03-13 2006-08-22 Seiko Epson Corporation Substrate having a planarization layer and method of manufacture therefor, substrate for electro-optical device, electro-optical device, and electronic apparatus
US7075704B2 (en) 2003-03-19 2006-07-11 Seiko Epson Corporation Test-element-provided substrate, method of manufacturing the same, substrate for electro-optical device, electro-optical device, and electronic apparatus
US7211826B2 (en) 2003-08-28 2007-05-01 Samsung Sdi Co., Ltd. Organic electroluminescent display
CN100449773C (en) * 2003-08-28 2009-01-07 三星Sdi株式会社 Organic electroluminescent display
US7538342B2 (en) 2005-07-14 2009-05-26 Samsung Electronics, Co., Ltd. Flat panel display and method for fabricating the same

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