JPS5921043A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of each of an upper metallic layer and a lower metallic layer through side etching while fining a wiring by each metallic layer easily by forming the inter-layer insulating films of an upper layer metal and a lower layer metal by the insulating films of two layers of different etching rates and forming the structure of an opening section for communicating each layer metal in a two stepped shape. CONSTITUTION:An electrode and a wiring by a first metallic layer 3 are formed onto a semiconductor substrate 1 containing a comparatively thick oxide film 2, and a first insulating film 7 and a second insulating film 8 are formed for insulation from a second metallic layer 4. A first opening section 9 is formed to the second insulating film 8 on a region in which the opening section for communicating the first metallic layer 3 and the second metallic layer 4 must be formed. A second opening section 10 is formed to the first insulating film 7 in the opening section 9. A resist 12 is removed, the metallic layer 4 is formed to the metallic layer 3 in the opening section 10 and the whole surface containing the opening section 10 and the opening section 9, a connection with the metallic layer 3 or the wiring by the metallic layer 4 is formed through a photoetching method, and the device is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device with a semiconductor multilayer circuit, and particularly relates to a method for manufacturing a semiconductor device with a semiconductor multilayer circuit, and in particular, in multilayer metal wiring (hereinafter referred to as multilayer wiring), lower metal wiring and "two-layer metal wiring" are used. The present invention relates to a method of forming an opening for communication between an interlayer insulating film and a lower metal film and a -1 layer metal film with a wiring line.

Multilayer wiring technology (/i) is essential when manufacturing semiconductor devices such as semiconductor multiplication circuits, and recently there has been an increasing demand for wire breakage prevention and fine patterning.

A conventional method for manufacturing multilayer wiring will be explained with reference to FIG. 1. In the figure, (1) is a semiconductor substrate, and (2) is an insulating film made of a thick oxide film formed on the semiconductor substrate (1). ,
(3) is the first metal layer, and (4) is the second metal layer.

(5) is an interlayer insulating film formed between the first and second metal layers (3) and (4), and (6) is an interlayer insulating film formed between the first and second metal layers M (3) and (4). This is a communication opening. When manufacturing such multilayer wiring, first, stain electrodes and wiring are formed on the first metal layer (3) by photolithography on the semiconductor substrate (1) by a known method, and then the first metal layer (3) is formed on the semiconductor substrate (1) by photolithography. 3) and the second metal layer (4) using a known technique.
) to form. At this time, an oxide film, a nitride film, etc. is used as the interlayer isolation R film (5), and the film thickness is determined by Jl, 0.0. About m is required. Then, a first metal layer (3) and a second metal layer (4) are formed by photolithography.
) All communication openings (6) are formed. Next, a semiconductor substrate (1) including the opening (6) and the first metal layer (3) is formed.
), and then the wiring of the second metal layer (4) and the first metal layer (
3) is used.

By the way, the interlayer insulating film (5)
And when the communication opening (6) between the first metal layer (3) and the second metal layer (4) is completely formed, the interlayer insulation between the first metal layer (3) and the second metal layer (4) The film thickness of the film (5) is relatively thick;
Furthermore, the slope of the connecting hole (6) needs to be relatively gentle in order to prevent disconnection during formation of the second metal layer (4). For this reason, the finished opening (6) is extremely stiff compared to the design value, and the opening wall extends up to the opening wall (a) and Φ) as shown by the dotted line in Figure 2. fall back.

Therefore, if the film quality of the first metal layer (3) and the second metal layer (4) is the same, then when wiring is formed using the second metal layer (4), as shown in the region I in FIG. 3.

Disconnection occurs in the wiring of the first metal layer (3). Furthermore, if the interlayer insulating film (5) and the insulating film (2) under the first metal layer (3) are of the same film quality, the interlayer insulating film (5) may be etched to form the opening (6). At times, as shown in the region marked with the symbol ■ in FIG. 3, the insulating film (2) under the first metal layer (3) is also etched at the same time, and the step becomes large when the second metal layer (4) is formed. This causes disconnection of the second metal layer (4).

In order to prevent these, it is necessary to place the second metal layer (4) on the wiring area formed by the first metal layer (3) in advance at the design stage.
) so that the connecting hole (6) can be formed, and the wiring formed by the second metal layer (4) can be formed in the connecting hole (6) sufficiently. 6) and the first metal layer (3
) with the wiring area (C) (see Figure 2), and the communication opening (6) with the second metal layer (4) (d).
(See Figure 2). Therefore, as shown in FIGS. 2 and 3, the wiring spacing (e) due to the first metal layer (3) and the wiring spacing (f) due to the second metal layer (4).
) is limited, and in order to provide a margin as described above, it is necessary to add the areas marked ``■'' and ``■'' in FIG. This has the disadvantage that the cell size shown in FIGS. 2 and 3 requires an enlargement of the cell size and the chip size unless the distance B of the cell size shown in FIG. 4 is reached.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional method, and the insulating film between the eyebrows of the upper layer metal and the lower layer metal is formed by two layers of insulating film with different etching ratios, and the insulating film for connecting each metal layer is formed. By making the structure of the opening part into a two-stage shape, it is possible to prevent disconnection of each metal layer due to side etching of the glabella insulating film when forming the opening part, and also to miniaturize the wiring by each metal layer. It is an object of the present invention to provide a method for manufacturing multilayer wiring that can be easily performed.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a cross-sectional view of a communication opening between an upper metal layer and a lower metal layer of a multilayer wiring manufactured by the method of the present invention. In the figure, (1) is a semiconductor substrate; (1) a thick oxide film as an insulating film formed on the top; (3) the first
((A) is the second metal layer.

Also, σ) is the first insulating film between the first and second metal layers (3) and (4), (8) is the second insulating film, and (9) is the first insulating film between the first metal layer (3) and (4). The first communicating hole (10) with the second metal layer (4) is a second communicating hole formed in the first communicating hole (9).

Next, a method for manufacturing a multilayer wiring according to the present invention will be explained with reference to FIGS. 6 to 11. In FIG. 6, electrodes and wiring are formed by a first metal layer (3) on a semiconductor substrate (1) including a relatively thick oxide film (2), and then a second metal layer (3), which will be described later, is formed.
A first insulating film σ) and a second insulating film (8) (see FIG. 7) are formed for insulation from the metal layer (4) (see FIG. 5). In this case, first, a first insulating film (7) made of silicon oxide is formed on the entire surface including the first metal layer (3) by a method such as a CVD method or a sputtering method, as shown in FIG. As shown in FIG. 7, a second insulating film (8) gold CVI) is formed on the film 17'), which is made of silicon nitride having a different etching ratio from the silicon oxide of the first insulating film q). J or sputtering method.

At this time, the film thickness of the second insulating film (8) is equal to that of the first insulating film (7).
For example, the thickness of the first insulating film (7) is approximately 1000-200X, and the thickness of the second insulating film (8) is approximately 500-900X. Next, by photolithography, the second insulating film (8) in the area 2 where all the openings for connecting the first metal layer (3) and the second metal layer (4) are to be formed is first etched with the eighth metal layer (8). A first opening (9) is formed as shown in the figure.

In this case, when etching the second insulating film (8), the slope of the opening wall may be made gentle to prevent disconnection at the opening wall of the second gold striped layer (4). Since the second insulating film (8) is relatively thick as described above,
The product of the opening 11i has a considerable side etch ridge compared to the design value. In FIG. 8, (11) is l/cyst applied during etching of the second insulating film (8).

Next, the first opening (9) formed in the second insulating film (8) is opened.
As shown in FIG. 9, a second opening (10) is entirely formed in the first insulating film σ) in ) by the same photolithography method. in this case,
Since the first insulating film σ) is sufficiently thinner than the second insulating film (8), there is no need for the entire tilting body to hang on the wall of the opening of the second opening (10). The side etching Ml is almost the same as the design value during etching, and the opening area can be formed with high precision by making it even smaller than the cutting value (see No. 101!'1). JIF-1p+y 9 c+: 1i'ij(1
2) is a resist applied during etching of the first insulating film (7). Next, remove as shown in FIG. 10 (12)'. After k, 21st: il hole ('
The first metal layer (3) and the second opening part (1) in the fit (10)
As shown in FIG. 11, a py2 layer (4) is formed on the entire surface including the first hole (9) and the first opening (9) by any known method,
A connection with the first metal layer (3) or a wiring using the second metal layer (4) is formed by photolithography to complete the process.

As described above, according to the above embodiment, the first metal layer (3) and the second metal layer (4) have different total etching ratios of the interlayer insulation films (7) and (8). Formation 1~
, and by forming the communication openings between the first metal layer (3) and the second metal layer (4) into a two-stage structure with the first and second openings (9) and (10), The area of the opening on the first metal layer (3) can be formed with extremely high precision relative to the design value. In other words, the wiring allowance (C) due to the connecting hole (10) and the first metal layer (3) (see Figure 2), and the wiring margin (C) due to the connecting hole (1o) and the second metal layer (4). The margin (d) (see FIG. 2) with respect to the wiring can be extremely reduced, making it possible to miniaturize the pattern. 1. Disconnection of the first and second metal layers due to side etching of the interlayer insulating film (5) when forming the connecting hole (6) as in the conventional method can be completely prevented.

In the above embodiment, silicon oxide was used as the first insulating film (7) and silicon nitride was used as the second insulating film (8); film(
8) and I- Even if silicon oxide is used, the same effect as in the above embodiment can be obtained. Furthermore, although the above embodiments have been described with respect to two-layer metal wiring, the present invention can also be applied to communication openings between lower and upper metal layers in multilayer wiring of three or more layers.

As described in -1- below, according to the present invention, the interlayer insulating film of the multilayer wiring is formed by two layers of insulating films with different etching ratios,
Furthermore, if the cross section of the communication hole between the lower layer metal and the -L layer metal is also made into a two-stage structure, the area of the hole on the lower layer metal can be formed with extremely high precision relative to the design value, and therefore,
It has excellent effects such as preventing disconnection of the second layer metal and lower layer metal in multilayer wiring, as well as enabling fine patterning.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a communication hole between the second layer metal and the lower layer metal in a conventional multilayer wiring, Figure 2 is a cross-sectional view of one cell in a conventional multilayer wiring, and Figure 3 is a cross-sectional view of one cell in a conventional multilayer wiring. FIG. 4 is a cross-sectional view of one cell to explain multilayer wiring using the conventional method. FIG. 4 is a cross-sectional view of one cell enlarged to prevent the drawbacks of multilayer wiring using the conventional method. FIG. 6 to 11 are cross-sectional views of connecting holes between the upper layer metal and the lower layer metal in the multilayer wiring for explaining one embodiment. be. (1)... Semiconductor substrate, (2)... Oxide film, (
3)...first metal layer, (4)...second metal layer,
(!i)...Interlayer insulating film, (6)...Openings for connecting each metal layer, σ)...First insulating film (first interlayer insulating film), (8)... ... second insulating film (second interlayer insulating film),
(9)...First opening, (10)...Second opening, (11), (12)---Resist, (a),
(b) -... Wall of the opening, (C)... Margin between the wiring made of the first metal layer and the opening, (d)... Wiring made of the second metal layer and the opening margin, (e)...1st
Minimum interval between wirings in the metal layer, (f) Minimum interval between wirings in the second metal layer, (g) Final opening,
(I)...Disconnection in the first metal layer, (U)...Disconnection in the second metal layer, (III)...Additional area for wiring by the second metal layer, (■) ...Additional area for wiring due to the first metal layer, A...Minimum cell size, B...
The minimum cell size specified to prevent disconnection of the first and second metal layers. Agent Shin Kuzuno - (11
) Figure 5 Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8 - To-22 is Figure 9 Figure 10 Figure 11

Claims (1)

[Scope of Claims] α) In the step of forming a multilayer metal wiring on a semiconductor substrate, there are a step of forming a lower metal film, a step of selectively removing the entire lower metal film, and a step of removing the entire surface including the lower metal film. a step of covering with a first insulating film; a step of covering the entire surface of the first insulating film with a second insulating film having a different etching ratio from the first insulating film; a step of forming all the first apertures in the film; a step of forming all the second apertures in the first insulating film in the first apertures; 2. A method for manufacturing a semiconductor device, comprising the steps of forming an upper layer metal film on the entire surface of a semiconductor substrate including a lower layer metal layer in an opening. C) The method for manufacturing a semiconductor device according to claim 1, characterized in that silicon oxide or a substance containing silicon oxide as a main component is used as the first insulating film, and silicon nitride is used as the second insulating film. 0) Manufacture of a semiconductor device according to claim 1, characterized in that silicon nitride is used as the first insulating film, and silicon oxide film or a material containing silicon oxide as a main component is used as the second insulating film. Method.