JPS63107043A - Forming method of conductive line for semiconductor device - Google Patents

Abstract

PURPOSE:To form connection between each of conductive lines having a fine shape without disconnections and to a flat shape by shaping a conductive metallic region connecting the conductive lines before forming an interlayer insulating layer. CONSTITUTION:First metallic layers 6, 7 are applied directly or through an insulating layer 2 onto a semiconductor substrate 1, an insulating layer 8 for plating is shaped onto the layers 6, 7, and the surface of the first metallic layer 7 is exposed partially through selective removal. A conductive metallic region 9 in predetermined thickness is formed through a plating method, using the first metallic layers 6, 7 as conductive paths for plating, the insulating layer 8 for plating is removed, the first metallic layers 6, 7 are removed with the exception of the lower section of the conductive metallic region 9 and a section near the region 9, and a lower-layer conductive line 10 is shaped. A first insulating layer 11 thicker than the sum of the thickness of the lower-layer conductive line 10 and the conductive metallic region 9 is applied, the surface of the conductive metallic region 9 is exposed through an etchback method to form an interlayer insulating layer 3, and an upper-layer conductive line 5 connected to the conductive metallic region 9 is shaped.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for forming conductive lines in a semiconductor device, and in particular to a method for forming a multilayer wiring that electrically connects a plurality of conductive lines provided through an interlayer insulating layer. Regarding the forming method.

[Conventional technology]

In recent years, as elements incorporated in semiconductor integrated circuits have become more highly integrated, multilayer wiring via insulating layers has been used as a wiring method for conductive lines connecting elements.

Conventionally, when performing this type of multi-layer wiring, the method of obtaining continuity between conductive lines in each layer was to provide contact openings in the interlayer insulating layer 3 above the lower conductive lines 4, as shown in FIG. The upper layer conductive line 5 was formed by depositing it by vapor deposition or sputtering and then patterning it into a predetermined shape.

[Problem that the invention seeks to solve]

As the miniaturization of semiconductor devices progresses, the conventional method for forming conductive lines in semiconductor devices described above has changed as shown in FIG.
The size of the contact I/opening becomes smaller with respect to the thickness of the insulating layer, and the thickness of the metal layer attached to the inner wall of the contact opening becomes thinner. For this reason, there is a drawback that disconnection occurs between the lower layer conductive line 4 and the upper layer conductive line 5, resulting in poor continuity.

In addition, in order to prevent this disconnection, a method is used in which the contact opening in the interlayer insulating layer 3 is formed into an inclined shape and a metal layer is attached to it, as shown in FIG. However, there is a drawback that the shape of the contact opening becomes large and miniaturization cannot be performed.

Further, the contact opening in the interlayer insulating layer 3 remains as a depression, which makes processing difficult when forming a conductive line in an upper layer.

[Means for solving problems]

A method for forming a conductive line in a semiconductor device according to the present invention includes a lower conductive line provided directly or via an insulating layer on one main surface of a semiconductor substrate, and an interlayer insulating layer having a contact opening on the lower conductive line. A step of depositing a first metal layer directly or via the insulating layer on one main surface of the semiconductor substrate, and a step of depositing an insulating layer for plating on the first metal layer in providing an upper conductive line through the semiconductor substrate. forming and then selectively removing to locally expose the surface of the first metal layer; and plating a conductive metal region of a predetermined thickness using the first metal layer as a conductive path for plating. a step of forming the lower layer conductive line by a method, and a step of forming the lower layer conductive line by removing the first metal layer except under and in the vicinity of the conductive metal region after removing the plating insulating layer; forming the interlayer insulating layer by exposing the surface of the conducting metal region by an etch-back method after depositing a first insulating layer thicker than the sum of the thicknesses of the conductive line and the conducting metal region; The method includes a step of forming an upper layer conductive line connected to the conductive metal region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1H are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a Ti layer 6 with a thickness of 50 nm and an Au layer 7 with a thickness of 500 nm are formed on one main surface of a semiconductor substrate 1 via an insulating layer 2 made of silicon oxide. A first metal layer of Au
Layer 7 is shaped into a predetermined shape.

Next, as shown in FIG. 1(b), the Ti layer 6 and the Au
After applying a 1 μm thick photosensitive resin layer on the surface of layer 7,
A plating insulating layer 8 is formed by removing a part of the photosensitive resin layer by exposing a part of the Au layer 7.

Next, as shown in FIG. 1(c), using the Ti layer 6 as a conductive path for plating, the exposed portion of the Au layer 8 is plated with Au to form a conductive metal region 9 having a thickness of 1 μm.

Next, as shown in FIG. 1(d), after removing the photosensitive resin layer with an organic solvent, the Ti layer 6 is removed by plasma etching using the Au layer 7 as a mask, and the lower layer with the conductive metal region 9 is removed. A conductive line 10 is formed.

Next, as shown in FIG. 1(e), a first insulating layer 11 made of a silicon oxide layer with a thickness of 1.2 μrn is formed.

Next, as shown in FIG. 1(f), a low temperature softening resin such as photoresist is applied and softened by heating at, for example, 200° C. to form a low temperature softening resin film 12 having a flat surface.

Next, as shown in FIG. 1(g), the low temperature softening resin film 12 and the silicon oxide layer on the conductive metal region 9 are removed at a constant speed using a plasma etching method (etchback method). The surface of conductive metal region 9 is exposed.

Finally, as shown in FIG. 1(h), a Ti-Au film is deposited and shaped into a predetermined shape, thereby forming an upper conductive line 5 in contact with the conductive metal region 9.

FIGS. 2(a) to 2(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), a Ti layer 6 is placed on an insulating layer 2 made of silicon oxide formed on a semiconductor substrate 1.
(film thickness: 50 nm), followed by Au layer 7 (film thickness: 5 nm).
00 nm) to form a first metal film.

Next, as shown in FIG. 2(b), a photosensitive resin layer (thickness: 1 μm) is applied to the surface of the Au layer 7, and then the photosensitive resin layer is selected so that a part of the Au layer 7 is exposed. The insulating layer 8 for plating is formed by photoremoval.

Next, as shown in FIG. 2(c), the Ti layer 6 and the Au
Using the layer 7 as a conductive path for plating, the exposed portion of the Au layer 7 is plated with Au to form a conductive metal region 9 made of Au and having a thickness of 1 μm.

Next, as shown in FIG. 2(d), after removing the photosensitive resin with an organic solvent, the Au layer 7 and the Ti layer 6 are selectively removed using an ion milling method to form the lower conductive line 10. Form. The subsequent steps are similar to those in the first embodiment.

1st. The second embodiment differs only in whether the first metal layer has a striped region or is flat, but the second embodiment requires fewer steps. Also,
The lower conductive line may be something like a gate electrode provided directly on one main surface of the GaAs substrate. Further, the present invention is effective not only for two-layer wiring but also for multi-layer wiring by repeatedly using the method shown in the embodiments.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by providing a conductive metal region for connecting conductive lines before forming an interlayer insulating layer, contact between finely shaped conductive lines can be formed without disconnection and in a flat shape. There is.

[Brief explanation of the drawing]

1(a) to 1(h) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the first embodiment of the present invention;
Figures (a) to (d) are cross-sectional views of a semiconductor chip arranged in the order of steps for explaining a second embodiment of the present invention, and Fig. 3 is a cross-sectional view of a semiconductor chip for explaining a first conventional example. figure,
FIG. 4 is a cross-sectional view of a semiconductor chip for explaining the drawbacks of the first conventional example, and FIG. 5 is a cross-sectional view of the semiconductor chip for explaining the second conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating layer, 3... Interlayer insulating layer, 4... Lower layer conductive line, 5... Upper layer conductive line,
6... Ti layer, 7... Au layer, 8... Insulating layer for plating, 9... Conductive metal region, 10... Lower conductive line, 11... First insulating layer, 12 ...Low temperature softening resin film. Agent Patent Attorney Uchihara Oto l'gu(,. Do゛・ Figure 1 Figure 1 Figure $2

Claims (1)

[Claims] In providing a lower layer conductive line directly or via an insulating layer on one main surface of the semiconductor substrate and an upper layer conductive line via an interlayer insulating layer having a contact opening on the lower layer conductive line, a step of depositing a first metal layer on one main surface directly or via the insulating layer; forming an insulating layer for plating on the first metal layer and then selectively removing the first metal layer; a step of locally exposing the surface of the metal layer, a step of forming a conductive metal region of a predetermined thickness by a plating method using the first metal layer as a conductive path for plating, and after removing the insulating layer for plating. , forming the lower layer conductive line by removing the first metal layer except under and in the vicinity of the conductive metal region; forming the interlayer insulating layer by exposing the surface of the conductive metal region by an etch-back method after depositing the insulating layer; and forming an upper conductive line connected to the conductive metal region. A method of forming a conductive line in a semiconductor device, the method comprising: