JPS63207153A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce contact resistance, and to increase the density of an interconnection by forming a first interconnection, an interlayer insulating film and a second interconnection, shaping an opening section to the crossing section of these first and second interconnections and burying a conductive film into the opening section. CONSTITUTION:An Al interconnection 7 as an upper layer is formed onto a PSG film 6, and an SiN film 8 is applied onto the whole surface through a plasma technique. An SiN film 8, the Al interconnection 7 and the PSG film 6 are removed partially, using a patterned resist film as a mask, thus shaping an opening section 9 to the crossing section of an Al interconnection 5 and the Al interconnection 7. An Al film 10 is applied through a vertical evaporation method, and the Al film 10 on the SiN film 8 is gotten rid of through polishing, employing the SiN film 8 as a stopper. Consequently, a semiconductor device having structure in which an Al member 11 is buried into the opening section 9 is completed. Accordingly, contact resistance is reduced, and the density of the interconnections can be increased.

Description

[Detailed Description of the Invention] [Summary] The method for forming a contact portion of a multilayer wiring according to the present invention includes the first
After forming the first wiring, living room insulating film, and second wiring. The method is characterized in that openings are provided in the portions where the second wirings alternate, and a conductive film is further embedded in the openings.

This simplifies the manufacturing process because the only alignment necessary for contact formation is alignment during the formation of the opening. Further, the size of the opening can be made approximately the same as the width of the first wiring and the second wiring. This eliminates the need for highly accurate positioning, and allows for reduced contact resistance and higher wiring density.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of forming contact portions between multilayer interconnections.

[Conventional technology]

FIG. 2(a) is a sectional view showing the structure of a contact portion according to a conventional example. In FIG.
is PSG [.

3 is the upper layer A hybridization line.

Next, a conventional method of forming a contact portion will be described with reference to FIGS. 2(a) and 2(b).

(1) First, form the lower layer A cross line 1.

(2) Next, PSG [2 is applied to the entire surface.

(3) Next, in order to connect the upper and lower layer An wiring, PSG
The film 2 is patterned to form openings 4. At this time, make sure that the opening 4 does not protrude from the lower layer A cross line l.
The pattern width of the opening 4 must be narrower than the width of the underlying Ann wiring with a certain margin.

(4) Next, after depositing an A2 film on the entire surface, the A2 film is patterned to form the upper layer An wiring 3.

At this time, in order to prevent the upper layer Ai wiring 3 from protruding from the opening 4, the width of the All wiring 3 at the contact portion must be made wider than the other wiring portions.

[Problem that the invention seeks to solve]

However, the conventional example has the following problems.

(1) It is necessary to align the opening 4 with respect to the lower layer human wiring 1 and the upper layer An wiring 3 with respect to the opening 4 during pattern formation. For this reason, it becomes necessary to set the alignment margin to be correspondingly wide, making it difficult to miniaturize.

(2) When the width of the Ai wiring is reduced, the width of the opening 4 is also reduced. Therefore, the contact resistance between the A cross line 1 and the An interconnect 3 increases.

(3) Furthermore, as the width of the opening 4 becomes smaller, the aspect ratio (depth of the opening/radius of the opening) increases. Therefore, disconnection of the Ai wiring 3 at the stepped portion of the opening 4 is likely to occur.

The present invention was created in view of such conventional problems, and aims to provide a method for forming a contact portion that has good wiring coverage, enables high-density wiring, and has low contact resistance. purpose.

[Means for solving problems]

A method for forming a contact portion of a multilayer wiring according to the present invention includes the steps of forming a first wiring, forming an insulating film covering the first wiring, and forming a second wiring film on the insulating film. forming an opening at the intersection of the first wiring film and the second wiring film to expose the first wiring film; and forming a conductive film in the opening. The method is characterized by comprising a step of coating the entire surface with a conductive film so that the conductive film is filled with the conductive film, and a step of removing the conductive film by polishing to leave the conductive film only in the opening.

[Effect]

According to the method for forming a contact portion of the present invention, the first
A conductive member embedded in an opening formed at the intersection of the wiring and the second wiring in the upper layer electrically connects the first wiring in the lower layer and the second wiring in the upper layer. Since this conductive member is buried at approximately the same height as the second wiring, the entire surface is flat.

Furthermore, according to the method for forming a contact portion of the present invention, alignment is only required once when forming an opening at the intersection of the first wiring and the second wiring, thereby simplifying the formation process. Furthermore, since the size of the opening can be made comparable to the width of the wiring, highly accurate positioning is not required and contact resistance can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a method of forming a contact portion of a multilayer wiring according to an embodiment of the present invention.

(1) First, after forming the lower layer human interconnection 5 with a film thickness of 1 lumen, PS as an interlayer insulating film with a film thickness of 1.0 to 1.5 lumen is formed.
A G film 6 is deposited on the entire surface (FIG. 2(a)).

(2) Next, an upper layer of AI with a thickness of 1 pm is placed on the PSG film 6.
LIji! , forming a line 7 (FIG. 2(b)).

(3) Next, using plasma technology, 5i with a film thickness of 0.2 gm was
Nffi8 is applied to the entire surface (FIG. 2(b)).

(SiN film 8. Anti!, line 7° PSG film 6
By partially removing , an opening 9 is formed at the intersection of the AM wiring 5 and the Ai wiring 7 (FIG. 1(d)).
, At this time, alignment for patterning the opening 9 only needs to be done once, and the width of the opening 9 is determined by the width of the All wiring 5 and the
The width of the n-line 7 does not need to be particularly narrow, and may be approximately the same as the width of these lines. Therefore, the alignment thereof does not need to be particularly accurate.

(5) Next, by vertical evaporation method, A1 with a film thickness of 2 to 3 pm was deposited.
1110 (Ce in the same figure)).

(8) Then, using the SiN film 8 as a stopper, the SiN
The Ai film 10 on the film 8 is removed by polishing. As a result, a semiconductor device according to the embodiment of the present invention having a structure in which the A-shaped member 11 is embedded in the opening 9 is completed (FIG. 2(f)).
Note that the SiN film 8 may be removed afterwards if necessary.

As described above, according to the embodiment of the present invention, the width of the opening 9 and therefore the width of the A1 member 11 can be made equal to the convergence of the lower layer AM wiring 5, so that alignment during patterning can be performed. Not only is this easy, but it is also possible to reduce contact resistance.

Further, since the contact A11 member 11 is buried, the surface of the semiconductor device is flat. Therefore, by further forming interconnects in a stacked manner, it is possible to obtain a semiconductor device having a multilayer interconnect structure with fewer disconnections.

In the example, All was used as the conductive material for the wiring and contacts, but other metals or conductive materials may be used, and a SiN film was used as the polishing stopper.
Other films may be used, and if the upper layer wiring is a metal film or the like that is hard to polish, it is not necessary to provide a polishing stopper film.

〔Effect of the invention〕

As described above, according to the method of manufacturing a semiconductor device of the present invention, the surface of the contact portion can be formed flat, so that highly reliable multilayer wiring with extremely few disconnections is possible.

Furthermore, since the size of the opening of the contact portion can be made sufficiently large, contact resistance can be reduced.

Further, according to the method of manufacturing a semiconductor device of the present invention, alignment for forming a contact portion is simple and easy. Further, since no special alignment margin is required for forming the contact portion, it is possible to increase the wiring density.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a method of forming a contact portion of a multilayer wiring according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a method of forming a contact portion of a multilayer wiring according to a conventional example. (Explanation of symbols) 1.3, 5.7... An wiring, 21, 6... PSGfi, 4.9... Opening. 8...SiN film.

Claims (1)

[Claims] (1) a step of forming a first wiring, a step of forming an insulating film covering the first wiring, a step of forming a second wiring film on the insulating film, and a step of forming the first wiring. forming an opening at the intersection of the wiring film and the second wiring film to expose the first wiring film; and forming a conductive film over the entire surface so that the opening is filled with the conductive film. A method for manufacturing a semiconductor device, comprising: a step of covering the conductive film; and a step of removing the conductive film by polishing to leave the conductive film only in the opening.