JPS6057648A - Formation of metallic wiring pattern - Google Patents

Abstract

PURPOSE:To remove a disconnection in an opening section by forming a lower- layer metallic wiring pattern on a semiconductor substrate first, coating the pattern with an inter-layer insulating film, forming the opening section in a predetermined region, burying a conductive material into the opening section and shaping an upper-layer metallic wiring pattern while being brought into contact with the conductive material and being extended on the insulating film when froming a multilayer wiring pattern. CONSTITUTION:A lower-layer metallic wiring pattern 2 is formed on a semiconductor substrate 1 in a predetermined manner, an inter-layer insulating film 3 is applied on the whole surface containing the pattern 2, and a contact opening section 4 is bored in response to the pattern 2 to expose the prescribed section of the pattern 2. A polycrystalline Si layer 7 as a conductive material 7 is grown on the whole surface in the vapor phase to completely bury the inside of the opening section 4, and the material 7 except the inside of the opening section 4 is removed through anisotropic etching. An upper-layer metallic wiring pattern 5 is applied on the flattened material 7 and the film 3 of the surroundings of the material 7. Accordingly, the upper layer and lower layer patterns are connected positively while a flattened surface is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a metal wiring pattern at a contact opening in a semiconductor device manufacturing process.

[Prior art]

A schematic structure of this type of metal wiring pattern obtained by a conventional forming method is shown in FIG.

That is, in this conventional method, first a semiconductor substrate (
1) Pattern (2) of the lower layer on top using known means.

After the lower layer pattern (2), which generally inevitably has a step part on the side, is completely formed, a silicon oxide film as an interlayer insulating film (3) is deposited by, for example, chemical vapor deposition. Form. Next, a desired contact opening (4) is completely formed in this interlayer insulating film (3) by a normal etching technique, and then the entire surface is subjected to, for example, sputtering or CVD.
A metal material for wiring is vapor-deposited by a method or the like to form an upper layer metal wire (5), and the metal film (5) for wiring and the lower layer pattern (2) are passed through the contact opening (4). The metal wiring patterns are connected using photolithographic technology and patterned to form the desired metal wiring pattern.

However, in this conventional method for forming a metal wiring pattern, as is clear from FIG. Film thickness part (6)
was formed, and the risk of wire breakage at this portion was extremely undesirable.

[Summary of the invention]

In view of these conventional drawbacks, the present invention has been developed by first filling the contact opening in a conductive material and then forming a metal wiring pattern in a β-reflective manner. This is designed to eliminate the risk of wire breakage.

[Embodiments of the invention]

Hereinafter, a method according to an embodiment of the present invention will be described in detail with reference to FIGS. 2(a) to d)fc.

In the example method shown in FIG. 2 (a) to d), the same reference numerals as in the conventional method shown in FIG. 1 indicate the same or corresponding parts. First, as shown in Figure 2(a), a semiconductor substrate (
1) After fully forming the lower layer pattern (2) having stepped portions on the sides, an interlayer insulating film (3) is formed uniformly and flatly on top of these using a flattening technique, In addition, contact openings (4) are completely formed in this glabella insulating film (3) by conventional photolithography and etching techniques as shown in FIG. 2(b). Next, as shown in FIG. 2(c), the contact openings (4) are filled with a conductive material (7), such as polysilicon, by chemical vapor deposition or the like. As shown in FIG. 2(a), the entire surface of the contact opening (4 ) is completely removed except for the buried portion, and then metal material 1 for wiring, such as aluminum, is vapor-deposited on the entire surface of the conductive material (7) in the same manner as in the past to form the upper layer metal film for wiring (5).
This wiring metal film (5) and the lower layer pattern (2) are connected by the conductive material (7) of the contact opening (4), and then patterned using photolithography technology to It is difficult to obtain the metal wiring pattern of the period.

In the above embodiment method, the case where polysilicon is used as the conductive material to fill the contact opening has been described, but as long as the conductive material is used, for example, AL
, P t , All, or a mixture thereof may be used as β, and of course it can be used not only for inter-element coupling as described above, but also for other applications such as multilayer wiring.

〔Effect of the invention〕

As detailed above, when using the method of the present invention, only the contact opening is filled with a conductive material, and then the entire upper layer metal wiring pattern is formed, and the upper layer metal wiring pattern is used to fill the conductive material in the opening. Since the connection is made through the material to the underlying pattern, there is no disconnection within the opening, which is the case with conventional methods, and a reliable connection can be made between both patterns.In addition, the metal wiring surface is flat. Since it is supported, it must be able to exhibit features such as facilitating the formation of a coating or pattern on the upper layer.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an outline of a metal wiring pattern obtained by a conventional method, and FIGS. Illustrated. (1)... Semiconductor substrate, (2)... Lower layer pattern, (3)... Interlayer insulating film, (4)... Contact opening, (5)... Metal film for wiring, (7)・
...Conductive material. Agent: Masuo Oiwa Procedural amendment @ (voluntary) 1. Description of the case Japanese Patent Application No. 165986/1986 2 Title of the invention Metal wiring pattern forming method 3 To the representative Hitoshi Katayama of the person making the amendment: r (CVD method) after "method" in the column of the detailed explanation of the invention in the specification ” to join. (2) Delete "-1: As shown in Figure 2 (a)" on page 3, line 18 of the same book. (3) In the same book, page 5, line 13, change “Yoshishidakara,” to “
"Because I did so," he corrected. that's all

Claims (1)

[Claims] In a method of forming a metal wiring pattern on a semiconductor substrate for manufacturing semiconductor devices, etc., a lower layer pattern is first formed on the substrate, an interlayer insulating film is formed on these, and an interlayer insulating film is formed on the lower layer pattern. Contact openings are formed in the insulating film, then a conductive material is provided on the entire surface of the contact openings, the bottom of the opening is filled with the conductive material, and then the conductive material is filled in the area other than the openings. 1. A method for forming a metal wiring pattern, which comprises removing the wiring metal film, completely forming a wiring metal film thereon, and then patterning the wiring metal film by photolithography to form a thin film pattern.