JPH02183536A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02183536A JPH02183536A JP344989A JP344989A JPH02183536A JP H02183536 A JPH02183536 A JP H02183536A JP 344989 A JP344989 A JP 344989A JP 344989 A JP344989 A JP 344989A JP H02183536 A JPH02183536 A JP H02183536A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- connection hole
- interlayer connection
- aluminum
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 abstract description 12
- 239000010937 tungsten Substances 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 230000010354 integration Effects 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000605 extraction Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線構造の半導体装置に利用され、特に、
微細多層配線を可能にする半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a semiconductor device having a multilayer wiring structure, and in particular,
The present invention relates to a semiconductor device that enables fine multilayer wiring.
本発明は多層配線を有する半導体装置において、下層配
線と上層配線との接続用導電体膜が、前記下層配線の上
面と、その上面に連なる一部側面部分とを露出して形成
された層間接続孔を埋めて形成された配線間接続部を設
けることにより、配線間接続部における下層配線の幅を
大きくする必要をなくし、高集積化を図ったものである
。The present invention provides an interlayer connection in a semiconductor device having multilayer wiring, in which a conductive film for connection between a lower layer wiring and an upper layer wiring is formed by exposing an upper surface of the lower layer wiring and a part of a side surface portion continuous to the upper surface. By providing the inter-wiring connection portion formed by filling the hole, there is no need to increase the width of the lower layer wiring in the inter-wiring connection portion, and high integration is achieved.
従来、この種の半導体装置は、第４図（ａ）および（ｂ
）に示すような配線構造を有していた。同図において、
１はシリコン基板、２はシリコン酸化膜、３は第一アル
ミ配線、４はバイアスＥＣＲ（Ｂｌｅ−ｃｔｒｏｎ Ｃ
ｙ’ｃｌｏｔｒｏｎ Ｒｅ５ｏｎａｎｃｅ）ブラズ７Ｃ
ＶＤ法等により形成されたシリコン酸化膜、７は第ニア
ルミ配線、および８は層間接続孔である。Conventionally, this type of semiconductor device is shown in FIGS. 4(a) and 4(b).
) It had a wiring structure as shown in ( ). In the same figure,
1 is a silicon substrate, 2 is a silicon oxide film, 3 is a first aluminum wiring, 4 is a bias ECR (Ble-ctron C
y'clotron Re5onance) Blaz 7C
A silicon oxide film is formed by a VD method or the like, 7 is a second aluminum wiring, and 8 is an interlayer connection hole.
本従来例においては、第一アルミ配線２と第ニアルミ配
線４との配線間接続部において、第一アルミ配線２の幅
が大きくなっている。このため、例えば、第一アルミ配
線幅を１．０μｍ、配線間隔を１．０μｍ１層間接続孔
８を１． Ｏｉｔｍ％層間接続孔８と第一アルミ配線３
との余裕を０．５μｍとすると、第一アルミ配線ピッチ
は２．５μｍとなる。In this conventional example, the width of the first aluminum wiring 2 is increased at the connection portion between the first aluminum wiring 2 and the second aluminum wiring 4. For this reason, for example, the first aluminum wiring width is 1.0 μm, the wiring interval is 1.0 μm, and the interlayer connection hole 8 is 1.0 μm. Oitm% interlayer connection hole 8 and first aluminum wiring 3
If the margin is 0.5 μm, the first aluminum wiring pitch will be 2.5 μm.
前述した従来の半導体装置は、層間接続孔が下層配線に
対してずれて外抜きにならないように、層間接続孔の開
孔される下層配線部分において、回合せ余裕を考慮し配
線幅を大きくしていた。このことは、層間接続孔の設置
された部分では、設置されない部分に比べて配線ピッチ
が大きくなることを意味し、特に、半導体集積回路の高
集積化に対する主な阻害要因となる欠点があった。In the conventional semiconductor device described above, in order to prevent the interlayer connection hole from shifting relative to the lower layer wiring and cutting out, the wiring width is increased in consideration of the wiring margin in the lower layer wiring portion where the interlayer connection hole is opened. was. This means that the wiring pitch is larger in areas where interlayer connection holes are installed than in areas where they are not installed, which is a drawback that is a major impediment to higher integration of semiconductor integrated circuits. .
本発明の目的は、前記の欠点を除去することにより、下
層配線の配線ピッチを大きくすることなく層間接続がで
き、高集積化を図ることができる半導体装置を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can achieve high integration by eliminating the above-mentioned drawbacks and which allows interlayer connections to be made without increasing the wiring pitch of the lower layer wiring.
本発明は、半導体基板上の一主面上にそれぞれ絶縁膜を
挟んで形成された複数層の配線を有する半導体装置にお
いて、下層配線の上面およびそれに連なる一部側面部分
を露出し前記絶縁膜の一部に形成された層間接続孔に、
前記下層配線の露出箇所を覆って形成され上層配線と接
続された接続用導電体膜が埋め込まれた配線間接続部を
有することを特徴とする。The present invention provides a semiconductor device having multiple layers of wiring formed on one principal surface of a semiconductor substrate with an insulating film sandwiched therebetween, in which the upper surface of the lower wiring and a part of the side surface connected thereto are exposed, and the insulating film is exposed. In the interlayer connection hole formed in a part,
It is characterized by having an inter-wiring connection portion in which a connecting conductive film formed to cover the exposed portion of the lower-layer wiring and connected to the upper-layer wiring is embedded.
接続用導電体膜、例えばタングステン膜は、下層配線の
上面とそれに連なる一部側面部分を露出して形成された
層間接続孔を埋めて形成され、前記側面部分と前記下層
配線の上面との間には層間絶縁膜が介在する構成となる
。A conductive film for connection, such as a tungsten film, is formed by filling an interlayer connection hole formed by exposing the upper surface of the lower layer wiring and a part of the side surface connected thereto, and between the side surface portion and the upper surface of the lower layer wiring. The structure has an interlayer insulating film interposed therebetween.
従って、層間接続孔は前記下層配線の幅よりも大すなわ
ち外抜きとなり、回合せのずれを考慮した十分な大きさ
に設定できる。しかも、前記下層配線の幅はそのままで
よいことになり、結果として配線ピッチを小さくし高集
積化を図ることが可能となる。Therefore, the interlayer connection hole is larger than the width of the lower layer wiring, that is, it is cut out, and can be set to a size sufficient to take into account misalignment. Moreover, the width of the lower layer wiring can be left as is, and as a result, it is possible to reduce the wiring pitch and achieve high integration.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）は本発明の一実施例を示す平面図および第
１図ら）はそのＡ−Ａ’断面図である。FIG. 1(a) is a plan view showing one embodiment of the present invention, and FIG. 1(a) is a sectional view taken along line AA'.
本実施例は、シリコン基板１上の一主面上にそれぞれ絶
縁膜としてのシリコン酸化膜２および４を挟んで形成さ
れた二層の配線としての第一アルミ配線３と、第ニアル
ミ配線７とを有する半導体装置において、
第一アルミ配線３の上面およびそれに連なる一部側面部
分を露出してシリコン酸化膜４に形成された層間接続孔
８に第一アルミ配線３の露出箇所を覆って形成され第ニ
アルミ配線７と接続された接続用導電体膜としてのタン
グステン膜５が埋め込まれた配線間接続部を有している
。In this embodiment, a first aluminum wiring 3 and a second aluminum wiring 7 are formed as two-layer wiring, which are formed on one principal surface of a silicon substrate 1 with silicon oxide films 2 and 4 as insulating films sandwiched therebetween. In the semiconductor device having the above, the upper surface of the first aluminum interconnect 3 and a part of the side surface connected thereto are exposed, and an interlayer connection hole 8 is formed in the silicon oxide film 4 to cover the exposed portion of the first aluminum interconnect 3. It has an inter-wiring connection portion in which a tungsten film 5 as a connection conductive film connected to the second aluminum wiring 7 is embedded.
第１図（ａ）および（ｂ）において、６はタングステン
膜５と層間接続孔８との間隙を充填して形成されたシリ
カ塗布酸化膜で、層間接続孔形成時の回合せずれにより
生じる間隙により生じる凹部を埋め、第ニアルミ配線７
が形成される面の平坦化を図るためのものであり、材料
はシリカに限らず、間隙を埋めて絶縁物を形成できるも
のであればよい。In FIGS. 1(a) and (b), 6 is a silica-coated oxide film formed by filling the gap between the tungsten film 5 and the interlayer connection hole 8, which is a gap caused by misalignment when forming the interlayer connection hole. Fill in the recesses caused by the second aluminum wiring 7.
The material is not limited to silica, but may be any material that can fill the gap and form an insulator.
本発明の特徴は、第１図（ａ）および（ｂ）において、
配線接続孔８の大きさを下層配線３の幅よりも大きく設
定し、それを埋め込んで、接続用導電体膜としてのタン
グステン膜５を設けたことにある。The feature of the present invention is that in FIGS. 1(a) and (b),
The size of the wiring connection hole 8 is set larger than the width of the lower layer wiring 3, and the tungsten film 5 is provided as a connection conductor film by filling it.
次に、本実施例の製造方法について、第２図（ａ）およ
び（ｂ）ならびに第３図（ａ）および（ｂ）に示す主要
工程における平面図およびそのＡ−Ａ’断面図を参照し
て説明する。Next, regarding the manufacturing method of this example, please refer to the plan view and the AA' cross-sectional view of the main steps shown in FIGS. 2(a) and (b) and 3(a) and (b). I will explain.
最初、第２図（ａ）およびら）に示すように、シリコン
基板１上のシリコン酸化膜２上に膜厚０．５μｍ程度の
アルミニニウムを被着パクン化し、第一アルミ配線３を
形成する。First, as shown in FIGS. 2(a) and 2(a), aluminum with a thickness of about 0.5 μm is deposited on the silicon oxide film 2 on the silicon substrate 1 to form a first aluminum wiring 3. .
次に、第３図（ａ）および（ｂ）に示すように、第一ア
ルミ配線３上にバイアスＥＣＲプラズマＣＶＤ法による
シリコン酸化膜４を膜厚０．９μｍ程度形成後、第一ア
ルミ配線３の上面および一部側面を選択的に露出させ、
タングステン選択ＣＶＤ法により膜厚０．４μｍ程度の
タングステン膜５を形成する。そしてタングステン膜５
とシリコン酸化膜４との間隙をエッチバック法によりシ
リカを塗布し熱処理によりシリカ塗布酸化膜６で充填す
る。Next, as shown in FIGS. 3(a) and 3(b), after forming a silicon oxide film 4 with a thickness of about 0.9 μm on the first aluminum wiring 3 by bias ECR plasma CVD method, the first aluminum wiring 3 Selectively expose the top surface and some sides of the
A tungsten film 5 having a thickness of about 0.4 μm is formed by a tungsten selective CVD method. and tungsten film 5
The gap between the silicon oxide film 4 and the silicon oxide film 4 is coated with silica by an etch-back method, and then filled with a silica-coated oxide film 6 by heat treatment.
最後に、第１図（ａ）およびら）に示すように、膜厚１
．０μｍ程度のアルミニニウムを被着パタン化しタング
ステン膜５と電気的に接続される第ニアルミ配線７を形
成する。Finally, as shown in Fig. 1(a) and et al., the film thickness is 1
．． Aluminum with a thickness of about 0 μm is deposited and patterned to form a second aluminum wiring 7 electrically connected to the tungsten film 5.
本実施例において、第一アルミ配線幅を１．０μｍ１配
線間隔を１．０即、層間接続孔８を１．０μｍＸ２．０
−とすると、第一アルミ配線ピッチは２．０μｍとなる
。In this example, the first aluminum wiring width is 1.0 μm, the wiring spacing is 1.0 μm, and the interlayer connection hole 8 is 1.0 μm×2.0 μm.
-, the first aluminum wiring pitch is 2.0 μm.
なお本実施例では第一配線および第二配線の配線材とし
てアルミニニウムを用いたが、アルミニュウムの代わり
にタングステン等の高融点金属を用いる゛こともできる
。この場合は配線の耐マイグレーション性が非常に向上
する利点がある。また、配線材料として高導電性の多結
晶シリコン等の他の導電体材料を用いる場合も同様であ
る。In this embodiment, aluminum is used as the wiring material for the first wiring and the second wiring, but a high melting point metal such as tungsten can also be used instead of aluminum. In this case, there is an advantage that the migration resistance of the wiring is greatly improved. Further, the same applies when using other conductive materials such as highly conductive polycrystalline silicon as the wiring material.
以上説明したように、本発明は、層間接続孔の大きさを
下層配線の幅よりも大きくすなわち外抜きできるように
することにより、微細多層配線を実現でき、高集積化を
図ることができる効果がある。As explained above, the present invention has the effect that fine multilayer wiring can be realized and high integration can be achieved by making the size of the interlayer connection hole larger than the width of the lower layer wiring, that is, by making it possible to cut out the outer layer. There is.
第１図（ａ）および（ｂ）は本発明の一実施例を示す平
面図およびそのＡ−Ａ’断面図。
第２図（ａ）および（ｂ）はその主要製造工程における
平面図およびそのＡ−Ａ’断面図。
第３図（ａ）およびら）はその主要製造工程における平
面図およびそのＡ−Ａ’断面図。
第４図（ａ）および（ｂ）は従来例を示す平面図および
そのＢ−Ｂ’断面図。
１・・・シリコン基板、２．４・・・シリコン酸化膜、
３・・・第一アルミ配線、５・・・タングステン膜、６
・・・シリカ塗布酸化膜、７・・・第ニアルミ配線、訃
・・層間接続孔。FIGS. 1(a) and 1(b) are a plan view and an AA' cross-sectional view showing an embodiment of the present invention. FIGS. 2(a) and 2(b) are a plan view and an AA' sectional view of the main manufacturing process. FIGS. 3(a) and 3(a) are a plan view and a sectional view taken along the line AA' of the main manufacturing process. FIGS. 4(a) and 4(b) are a plan view and a BB' sectional view showing a conventional example. 1... Silicon substrate, 2.4... Silicon oxide film,
3... First aluminum wiring, 5... Tungsten film, 6
...Silica-coated oxide film, 7.Near aluminum wiring, and...Interlayer connection hole.
Claims (1)
形成された複数層の配線を有する半導体装置において、 下層配線の上面およびそれに連なる一部側面部分を露出
し前記絶縁膜の一部に形成された層間接続孔に、前記下
層配線の露出箇所を覆って形成され上層配線と接続され
た接続用導電体膜が埋め込まれた配線間接続部 を有することを特徴とする半導体装置。[Claims] 1. In a semiconductor device having multiple layers of wiring formed on one main surface of a semiconductor substrate with an insulating film in between, the upper surface of the lower wiring and a part of the side surface connected thereto are exposed. The interlayer connection hole formed in a part of the insulating film has an inter-wiring connection part in which a connecting conductive film formed to cover the exposed portion of the lower-layer wiring and connected to the upper-layer wiring is embedded. semiconductor device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1003449A JP2508831B2 (en) | 1989-01-09 | 1989-01-09 | Semiconductor device |
| US07/725,942 US5233223A (en) | 1989-01-09 | 1991-06-27 | Semiconductor device having a plurality of conductive layers interconnected via a tungsten plug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1003449A JP2508831B2 (en) | 1989-01-09 | 1989-01-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02183536A true JPH02183536A (en) | 1990-07-18 |
| JP2508831B2 JP2508831B2 (en) | 1996-06-19 |
Family
ID=11557644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1003449A Expired - Lifetime JP2508831B2 (en) | 1989-01-09 | 1989-01-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2508831B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0426151A2 (en) * | 1989-10-31 | 1991-05-08 | Kabushiki Kaisha Toshiba | Method of manufacturing a multi-layered wiring structure of semiconductor integrated circuit device |
| US6316836B1 (en) | 1998-05-27 | 2001-11-13 | Nec Corporation | Semiconductor device interconnection structure |
| US7166923B2 (en) | 2003-03-26 | 2007-01-23 | Seiko Epson Corporation | Semiconductor device, electro-optical unit, and electronic apparatus |
| JP2013084969A (en) * | 2005-02-03 | 2013-05-09 | Semiconductor Energy Lab Co Ltd | Semiconductor device, module, and electronic apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137456A (en) * | 1986-11-29 | 1988-06-09 | Nec Corp | Manufacture of semiconductor integrated circuit |
| JPS63269546A (en) * | 1987-04-27 | 1988-11-07 | Nec Corp | Manufacture of semiconductor device |
-
1989
- 1989-01-09 JP JP1003449A patent/JP2508831B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137456A (en) * | 1986-11-29 | 1988-06-09 | Nec Corp | Manufacture of semiconductor integrated circuit |
| JPS63269546A (en) * | 1987-04-27 | 1988-11-07 | Nec Corp | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0426151A2 (en) * | 1989-10-31 | 1991-05-08 | Kabushiki Kaisha Toshiba | Method of manufacturing a multi-layered wiring structure of semiconductor integrated circuit device |
| US6316836B1 (en) | 1998-05-27 | 2001-11-13 | Nec Corporation | Semiconductor device interconnection structure |
| US7166923B2 (en) | 2003-03-26 | 2007-01-23 | Seiko Epson Corporation | Semiconductor device, electro-optical unit, and electronic apparatus |
| JP2013084969A (en) * | 2005-02-03 | 2013-05-09 | Semiconductor Energy Lab Co Ltd | Semiconductor device, module, and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2508831B2 (en) | 1996-06-19 |
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