JPS6340347A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6340347A
JPS6340347A JP18442286A JP18442286A JPS6340347A JP S6340347 A JPS6340347 A JP S6340347A JP 18442286 A JP18442286 A JP 18442286A JP 18442286 A JP18442286 A JP 18442286A JP S6340347 A JPS6340347 A JP S6340347A
Authority
JP
Japan
Prior art keywords
wiring
insulating film
polycrystalline silicon
film
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18442286A
Other languages
Japanese (ja)
Inventor
Kiichi Morooka
諸岡 毅一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18442286A priority Critical patent/JPS6340347A/en
Publication of JPS6340347A publication Critical patent/JPS6340347A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the increase in the coupling capacitance between a polycrystalline Si wiring and a metal wiring by a method wherein another polycrystalline Si film and an interlayer insulating film are formed on both sides of the polycrystalline Si wiring. CONSTITUTION:A polycrystalline Si film 8 is formed on the surface of a field insulating film 2 leaving an interval between them, and interlayer insulating films 9 are formed on the surface of said film 8. A polycrystalline Si wiring 3 is formed on the exposed surface of the insulating film 2 located between said insulating films 9. Then, an interlayer insulating film 40 is formed on the surface of the insulating film 9, the insulating film 2 and the wiring 3, and a wiring 50 is formed on the surface of the insulating film 40 in such a manner that the wiring 50 crosses the wiring 3. As a result, the difference between the upper surface of the wiring 3 and the upper surface of the insulating film 9 can be made small, and the increase in coupling capacitance between the wiring 3 and the wiring 50 can be prevented.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は半導体集積回路装置の配線構造に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring structure of a semiconductor integrated circuit device.

[従来の技術] 第3図は、従来の半導体集積回路装置を示す平面図であ
り、第4図は、第3図のA−A−線断面図である。
[Prior Art] FIG. 3 is a plan view showing a conventional semiconductor integrated circuit device, and FIG. 4 is a sectional view taken along the line AA in FIG. 3.

図において、半導体基板1表面にフィールド用絶縁l!
12が形成されており、このフィールド用絶縁1112
表面に多結晶シリコン配置3が形成されている。フィー
ルド用絶縁膜2表面および多結晶シリコン配線3表面に
層間絶縁14が形成されており、この層間絶縁膜4表面
に、多結晶シリコン配置13と交差するようにアルミニ
ウム配線5が形成されている。また、層間絶縁膜4表面
にアルミニウム配l116が形成されており、このアル
ミニウム配線6は、多結晶シリコン配線3とアルミニウ
ム配置i15との交差部付近でコンタクトホール7によ
り多結晶シリコン配線3に接続されている。
In the figure, field insulation l! is provided on the surface of a semiconductor substrate 1!
12 is formed, and this field insulation 1112
A polycrystalline silicon arrangement 3 is formed on the surface. Interlayer insulation 14 is formed on the surface of field insulating film 2 and polycrystalline silicon wiring 3, and aluminum wiring 5 is formed on the surface of interlayer insulation film 4 so as to intersect with polycrystalline silicon arrangement 13. Further, an aluminum interconnect 116 is formed on the surface of the interlayer insulating film 4, and this aluminum interconnect 6 is connected to the polycrystalline silicon interconnect 3 through a contact hole 7 near the intersection of the polycrystalline silicon interconnect 3 and the aluminum interconnect 115. ing.

[発明が解決しようとする問題点コ 従来の半導体集積回路装置における配線の交差部は以上
のように構成されているので、多結晶シリコン配線3と
アルミニウム配線5との交差部において多結晶シリコン
配線3と層間絶縁vA4とアルミニウム配線5とからキ
ャパシタ構造が形成される。この場合、多結晶シリコン
配線3の上面部とフィールド用絶縁1112表面との高
低差が大きく段差部が形成されているため、層間絶縁1
4を形成するとき、この段差部近傍で層間絶縁[14の
膜厚が、マルA内に示したように減少して多結晶シリコ
ン配線3とアルミニウム配線5間の結合容量が増加し、
多結晶シリコン配線3とアルミニウム配線5間で信号の
クロストークが生じるという問題点があった。
[Problems to be Solved by the Invention] Since the wiring intersections in the conventional semiconductor integrated circuit device are configured as described above, the polycrystalline silicon wiring 3 and the aluminum wiring 5 intersect with each other. 3, interlayer insulation vA4, and aluminum wiring 5 form a capacitor structure. In this case, since the height difference between the upper surface of the polycrystalline silicon wiring 3 and the surface of the field insulation 1112 is large and a stepped portion is formed, the interlayer insulation 1112
4, the film thickness of the interlayer insulation [14] decreases as shown in the circle A near this stepped portion, and the coupling capacitance between the polycrystalline silicon wiring 3 and the aluminum wiring 5 increases.
There was a problem in that signal crosstalk occurred between the polycrystalline silicon wiring 3 and the aluminum wiring 5.

この発明は上記のような問題点を解消するためになされ
たもので、配線の交差部において配線間の信号のクロス
トークが生じにくい半導体集積回路装置を得ることを目
的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device in which signal crosstalk between wires is less likely to occur at intersections of wires.

[問題点を解決するための手段1 この発明にかかる半導体集積回路装置は、半導体基板表
面にフィールド用絶縁膜を形成し、このフィールド用絶
縁膜表面に互いに間隔を隔てて多結晶シリコン膜を形成
し、この多結晶シリコン膜表面に第1の層間絶縁膜を形
成し、この第1の層間絶縁m間のフィールド用絶縁膜の
露出した表面に多結晶シリコン配線を形成し、第″1の
層間絶縁膜表面、残りのフィールド用絶縁膜の露出した
表面および多結晶シリコン配線表面に第2の層間絶縁膜
を形成し、この第2の層間絶縁膜表面に多結晶シリコン
配線と交差するように金属配線を形成したものである。
[Means for Solving the Problems 1] A semiconductor integrated circuit device according to the present invention includes forming a field insulating film on the surface of a semiconductor substrate, and forming polycrystalline silicon films at intervals on the surface of the field insulating film. Then, a first interlayer insulating film is formed on the surface of this polycrystalline silicon film, a polycrystalline silicon wiring is formed on the exposed surface of the field insulating film between the first interlayer insulating m, and a first interlayer insulating film is formed. A second interlayer insulating film is formed on the surface of the insulating film, the exposed surface of the remaining field insulating film, and the surface of the polycrystalline silicon wiring, and a metal layer is formed on the surface of the second interlayer insulating film so as to cross the polycrystalline silicon wiring. This is formed by wiring.

[作用] この発明においては、多結晶シリコン配線の両側に多結
晶シリコン膜、第1の層間絶縁膜を形成することによっ
て、この多結晶シリコン配線の上面部と第1の層間絶縁
膜の上面部との高低差が小さくなり、第2の層間絶縁膜
を形成したとき、この第2の層間絶縁膜のm厚が多結晶
シリコン配線と金属配線との交差部において減少するの
が防止される。このため、多結晶シリコン配線と金属配
線間の結合容量の増大が防止され、配線間の信号のクロ
ストークが生じにくくなる。
[Function] In the present invention, by forming a polycrystalline silicon film and a first interlayer insulating film on both sides of a polycrystalline silicon wiring, the upper surface of the polycrystalline silicon wiring and the upper surface of the first interlayer insulating film are separated. When the second interlayer insulating film is formed, the thickness (m) of the second interlayer insulating film is prevented from decreasing at the intersection between the polycrystalline silicon wiring and the metal wiring. Therefore, an increase in the coupling capacitance between the polycrystalline silicon wiring and the metal wiring is prevented, and signal crosstalk between the wirings is less likely to occur.

[実施例] 以下、この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

なお、この実施例の説明において、従来の技術の説明と
重複する部分については、適宜その説明を省略する。
In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

第1図は、この発明の実施例である半導体集積回路装置
を示す平面図であり、第2図は、第゛1図のA−A”線
断面図である。
FIG. 1 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A--A in FIG.

この実施例の構成が、第3図および第4図の半導体集積
回路装置の構成と異なる点は以下の点である。すなわち
、フィールド用絶縁!12表面に互い!、:間隔を隔て
て多結晶シリコン膜8が形成されており、この多結晶シ
リコン1118表面に層間絶縁119が形成されている
。層間絶縁vA9間のフィールド用絶縁膜2の露出した
表面に多結晶シリコン配線3が形成されている。層間絶
縁119表面、残りのフィールド用絶縁膜2の露出した
表面および多結晶シリコン配線3表面に層間絶縁llI
40が形成されており、この層間絶縁膜40表面に多結
晶シリコン配線3と交差するようにアルミニウム配線5
0が形成されている。
The structure of this embodiment differs from the structure of the semiconductor integrated circuit device shown in FIGS. 3 and 4 in the following points. In other words, field insulation! 12 each other on the surface! ,: Polycrystalline silicon films 8 are formed at intervals, and interlayer insulation 119 is formed on the surface of this polycrystalline silicon 1118. A polycrystalline silicon wiring 3 is formed on the exposed surface of the field insulating film 2 between the interlayer insulation vA9. Interlayer insulation llI is applied to the surface of the interlayer insulation 119, the exposed surface of the remaining field insulation film 2, and the surface of the polycrystalline silicon wiring 3.
40 is formed, and an aluminum wiring 5 is formed on the surface of this interlayer insulating film 40 so as to intersect with the polycrystalline silicon wiring 3.
0 is formed.

このように、多結晶シリコン配線3の両側に多結晶シリ
コンI[I18.層間絶縁lll9を形成することによ
って、多結晶シリコン配線3の上面部と層間絶all1
9の上面部との高低差を小さくすることができるので、
層間絶縁1I40を形成したとき、多結晶シリコン配置
3とアルミニウム配置fi50との交差部において、層
間絶縁膜40の膜厚が、従来の第4図のマルA内に示し
たように減少するのを防ぐことができる。このため、多
結晶シリコン配置13と層間絶縁m間0とアルミニウム
配線5oとで形成されるキャパシタ構造において、多結
晶シリコン配線3とアルミニウム配線50間の結合容量
の増大を防ぎ、多結晶シリコン配wA3とアルミニウム
配置950間の信号のクロストークを生じにくくするこ
とができる。
In this way, polycrystalline silicon I[I18. By forming the interlayer insulation lll9, the upper surface part of the polycrystalline silicon wiring 3 and the interlayer insulation lll1
Since the difference in height from the top surface of 9 can be reduced,
When the interlayer insulating film 1I40 is formed, the film thickness of the interlayer insulating film 40 is reduced at the intersection of the polycrystalline silicon arrangement 3 and the aluminum arrangement fi50 as shown in the conventional circle A in FIG. It can be prevented. Therefore, in the capacitor structure formed by the polycrystalline silicon arrangement 13, the interlayer insulation m0, and the aluminum wiring 5o, an increase in the coupling capacitance between the polycrystalline silicon wiring 3 and the aluminum wiring 50 is prevented, and the polycrystalline silicon wiring wA3 Signal crosstalk between the aluminum arrangement 950 and the aluminum arrangement 950 can be made less likely to occur.

なお、上記実施例では、上層の配線がアルミニウム配線
である場合について示したが、上層の配線として他の金
属配線を用いるようにしてもよい。
In the above embodiment, the upper layer wiring is aluminum wiring, but other metal wiring may be used as the upper layer wiring.

[発明の効果] 以上のようにこの発明によれば、半辱体1s板表面にフ
ィールド用絶縁膜を形成し、このフィールド用絶縁膜表
面に互いに間隔を隔てて多結晶シリコン膜を形成し、こ
の多結晶シリコン膜表面に第1の層間絶縁膜を形成し、
この第1の層間結縁膜間のフィールド用絶縁膜の露出し
た表面に多結晶シリコン配線を形成し、第1の層間絶縁
膜表面、残りのフィールド用#!縁摸の露出した表rf
JI3よび多結晶シリコン配線表面に第2の層間絶縁膜
を形成し、この第2の層間絶縁膜表面に多結晶シリコン
配線と交差するように金属配線を形成するので、多結晶
シリコン配線の上面部と第1の磨間絶RIIの上面部と
の高低差が小さくなり、第2の層間絶amの膜厚が、多
結晶シリコン配線と金属配線との交差部において減少す
るのが防止される。このため、多結晶シリコン配線と金
属配線間の結合容量の増大が防止され、配線の交差部に
おいて配線間の信号のクロストークが生じにくい半導体
集積回路装置を得ることができる。
[Effects of the Invention] As described above, according to the present invention, a field insulating film is formed on the surface of the semicircular body 1s plate, and polycrystalline silicon films are formed on the surface of the field insulating film at intervals, forming a first interlayer insulating film on the surface of this polycrystalline silicon film;
A polycrystalline silicon wiring is formed on the exposed surface of the field insulation film between the first interlayer insulation films, and the remaining field #! is formed on the surface of the first interlayer insulation film. Exposed front surface rf
A second interlayer insulating film is formed on the surface of the JI3 and polycrystalline silicon wiring, and a metal wiring is formed on the surface of the second interlayer insulating film so as to intersect with the polycrystalline silicon wiring, so that the upper surface of the polycrystalline silicon wiring is The difference in height between the upper surface portion of the first wear barrier RII is reduced, and the film thickness of the second layer barrier RII is prevented from decreasing at the intersection of the polycrystalline silicon interconnect and the metal interconnect. Therefore, an increase in the coupling capacitance between the polycrystalline silicon wiring and the metal wiring is prevented, and it is possible to obtain a semiconductor integrated circuit device in which signal crosstalk between the wirings is less likely to occur at the intersection of the wirings.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明の大筋例である半導体集積回路装置
を示す平面図であり、第2図は、第1図のA−A′線断
面図である。 第3図は、従来の半導体集積回路装置を示す平面図であ
り、第4図は、第3因のA−A−線断面図である。 図において、1は半導体基板、2はフィールド用1If
J緑膜、3は多結晶シリコン配線、4.9.40はm間
絶縁膜、5.6.50はアルミニウム配線、7はコンタ
クトホール、8は多結晶シリコン膜である。 なお、各図中同一符号は同一または相当部分を示す。
FIG. 1 is a plan view showing a semiconductor integrated circuit device which is a general example of the present invention, and FIG. 2 is a sectional view taken along the line A-A' in FIG. FIG. 3 is a plan view showing a conventional semiconductor integrated circuit device, and FIG. 4 is a cross-sectional view taken along the line AA of the third factor. In the figure, 1 is a semiconductor substrate, 2 is a field 1If
J green film, 3 is a polycrystalline silicon wiring, 4, 9, 40 is an m insulating film, 5, 6, 50 is an aluminum wiring, 7 is a contact hole, and 8 is a polycrystalline silicon film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板と、 前記半導体基板表面に形成されるフィールド用絶縁膜と
、 前記フィールド用絶縁膜表面に互いに間隔を隔てて形成
される多結晶シリコン膜と、 前記多結晶シリコン膜表面に形成される第1の層間絶縁
膜と、 前記第1の層間絶縁膜間の前記フィールド用絶縁膜の露
出した表面に形成される多結晶シリコン配線と、 前記第1の層間絶縁膜表面、残りの前記フィールド用絶
縁膜の露出した表面および前記多結晶シリコン配線表面
に形成される第2の層間絶縁膜と、前記第2の層間絶縁
膜表面に前記多結晶シリコン配線と交差するように形成
される金属配線とを備えた半導体集積回路装置。
(1) A semiconductor substrate, a field insulating film formed on the surface of the semiconductor substrate, a polycrystalline silicon film formed on the surface of the field insulating film at a distance from each other, and a polycrystalline silicon film formed on the surface of the polycrystalline silicon film. a polycrystalline silicon wiring formed on the exposed surface of the field insulating film between the first interlayer insulating films; a second interlayer insulating film formed on the exposed surface of the field insulating film and the surface of the polycrystalline silicon wiring; and a metal formed on the surface of the second interlayer insulating film so as to intersect with the polycrystalline silicon wiring. A semiconductor integrated circuit device equipped with wiring.
(2)前記金属配線はアルミニウムからなる特許請求の
範囲第1項記載の半導体集積回路装置。
(2) The semiconductor integrated circuit device according to claim 1, wherein the metal wiring is made of aluminum.
JP18442286A 1986-08-05 1986-08-05 Semiconductor integrated circuit device Pending JPS6340347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18442286A JPS6340347A (en) 1986-08-05 1986-08-05 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18442286A JPS6340347A (en) 1986-08-05 1986-08-05 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6340347A true JPS6340347A (en) 1988-02-20

Family

ID=16152881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18442286A Pending JPS6340347A (en) 1986-08-05 1986-08-05 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6340347A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006080514A (en) * 2002-12-25 2006-03-23 Semiconductor Energy Lab Co Ltd Display device
US8058672B2 (en) 2002-12-25 2011-11-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
JP2013207240A (en) * 2012-03-29 2013-10-07 Asahi Kasei Electronics Co Ltd Infrared-ray sensor array
US9046410B2 (en) 2012-03-29 2015-06-02 Asahi Kasei Microdevices Corporation Light receiving device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006080514A (en) * 2002-12-25 2006-03-23 Semiconductor Energy Lab Co Ltd Display device
US8058672B2 (en) 2002-12-25 2011-11-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
US8227837B2 (en) 2002-12-25 2012-07-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
US8569802B2 (en) 2002-12-25 2013-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
JP2013207240A (en) * 2012-03-29 2013-10-07 Asahi Kasei Electronics Co Ltd Infrared-ray sensor array
US9046410B2 (en) 2012-03-29 2015-06-02 Asahi Kasei Microdevices Corporation Light receiving device

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