JPS61188946A - Multilayer interconnection semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To highly integrate a circuit by utilizing recesses of an irregular surface produced in case of forming an insulating layer as new wiring region. CONSTITUTION:Aluminum of the first layer metal wirings 2 is formed on a semiconductor substrate 1, and a CVD-SiO2 film of an insulating film 3 is coated thereon. In this case, the upper portion of the portion between two adjacent first layer metal wirings 2 is recessed as compared with the upper portion coated with the wirings 2. Aluminum of the first and fifth layer metal wirings 4 is coated in the recess, aluminum of the second layer metal wirings 5 is coated on the projection of the upper portion of the wirings 2, and a CVD-SiO2 film of an insulating film 6 is coated thereon. When the first, fifth layer wirings 4 and the first layer wirings 2 or the second layer wirings 5 are separated therebetween only at a distance of the degree that they are electrically interfered, the thickness of the insulating film is increased or the interval of the first and second adjacent wirings is increased.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to multilayer wiring integrated circuits.

[Technical background of the invention and its problems]

In a multilayer wiring semiconductor integrated circuit, if each layer is insulated with an insulating film, a plurality of wiring lines can be stacked at the same place, and the degree of integration is increased. At that time, adjacent wiring metals on the same layer are kept at a certain distance λ to prevent electrical interference f:
is followed by Yasutsugu. In conventional multilayer wiring semiconductor integrated circuits, the use of the above-mentioned intervals inside each layer is hardly considered.

FIG. 3(b) is a parallel wiring diagram of a two-layer wiring semiconductor integrated circuit, and FIG. 3(a) is a cross-sectional view thereof. In conventional multilayer wiring semiconductor integrated circuits, adjacent wiring metal parts 10 and 11 are separated by a distance λ to prevent electrical interference.
They are stacked up in each layer while maintaining the
No proposal has yet been made to improve the degree of integration of multilayer wiring semiconductor integrated circuits by effectively utilizing this portion.

[Purpose of the invention]

It is an object of the present invention to provide a multilayer wiring semiconductor integrated circuit that can improve the degree of integration by effectively utilizing the above-mentioned portions between adjacent wiring metal parts.

[Summary of the invention]

The present invention achieves the above object by newly utilizing the concave portion of the unevenness formed on the insulating film as a wiring region when the wiring metal portion is formed in each layer and then insulated with an insulating film.

〔Effect of the invention〕

As explained above, according to the present invention, wiring in a multilayer interconnection semiconductor integrated circuit, particularly the layer joint between multilayer parallel interconnections with intervals for preventing interference, can be achieved without complicating the semiconductor manufacturing process. By using the area as a new wiring area, it is possible to increase the degree of integration of the circuit.

[Embodiments of the invention]

FIG. 1(b) is a parallel wiring diagram showing a part of an embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 1(a) is a schematic cross-sectional view thereof. First, a first layer metal wiring 2 (At) is formed on a semiconductor substrate 1, and an insulating film 3 (C'%'D7
Cover with SiO2 film). At this time, the upper part of the portion between two adjacent first-layer metal wiring lines 2 is recessed compared to the upper part of the first-layer metal wiring line 2t. The first and fifth layer metal interconnects 4 (AL) are applied to the recessed portions, the second layer metal interconnects 5 (A-a)' are applied to the white portions above the first layer metal interconnects 2, and an insulating film is formed on top of the second layer metal interconnects 5 (A-a)'. 5 (CVD-8i02 film). The 1.5th layer metal wiring 4 may be formed simultaneously with the second layer metal wiring 5, or may be formed separately. In this process, the first and fifth
If the distance between the layer metal wiring 4 and the first layer metal wiring 2 or the second layer metal wiring 5 is too far apart to cause electrical interference, increase the thickness of the insulating film or make them adjacent to each other. Mutual interference can be prevented by increasing the distance between the first and second layer metal wiring.

FIG. 2 is a circuit diagram showing another embodiment of the semiconductor integrated circuit according to the present invention. In FIG. 2(a), the first layer wiring 7 (real #
) and second layer wiring 8 (broken lines).

λ is the spacing between adjacent wires. When the present invention is applied to this example, as shown in FIG. 2(b), a first
, five-layer wiring 9 (dotted chain line) can be applied, the wiring area is reduced by the distance λ, and the degree of circuit integration can be improved. Although this example relates to a two-layer wiring semiconductor integrated circuit, the same applies to a multi-layer wiring semiconductor integrated circuit.

[Brief explanation of the drawing]

Fig. 1 Ta) (b) is a sectional view and a plan view showing a part of an embodiment of the semiconductor integrated circuit according to the present invention, and Fig. 2 (a) and (b) are a plan view and a plan view of another embodiment, respectively. Figure 3 (a)
(b) is a sectional view and a plan view, respectively, of a conventional example. In the figure, 1... Semiconductor substrate, 2... Metal for first layer wiring, 3... First layer insulating film, 4... Metal for fourth and fifth layer wiring, 5... Second layer Layer wiring metal, 6...2nd
layer insulation film. 7... 1st layer wiring, 8... 2nd layer wiring %9... 1st and 5th layer wiring. 10... Metal for second layer wiring, 11... Metal for Si layer layer wire 12... Part between parallel wiring metals. Agent: Patent attorney Kensuke Norichika (and 1 other person) Figure 1
(α) Fig. 1 (b) Fig. 2 (α) Fig. 2 Cb) Fig. 3 (a> Input

Claims (1)

[Claims] A multilayer interconnection semiconductor integrated circuit in which each layer is insulated with an insulating film, the multilayer interconnection semiconductor integrated circuit is characterized in that a concave portion of unevenness that occurs when forming an insulating layer is used as a new wiring area.