JPS62108542A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62108542A JPS62108542A JP24954285A JP24954285A JPS62108542A JP S62108542 A JPS62108542 A JP S62108542A JP 24954285 A JP24954285 A JP 24954285A JP 24954285 A JP24954285 A JP 24954285A JP S62108542 A JPS62108542 A JP S62108542A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- wiring
- metallic wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、複数階配線を有する高集積度半導体装置の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a highly integrated semiconductor device having multiple levels of wiring.
第2図は従来の半導体装置の2層配線の構造を示す断面
図であり、図において、(1)は半導体基板、(2)は
絶縁膜、(3)は第1層金属配線、(4)は層間絶縁膜
、(5)は第2層金属配線である。FIG. 2 is a cross-sectional view showing the structure of two-layer wiring of a conventional semiconductor device. In the figure, (1) is a semiconductor substrate, (2) is an insulating film, (3) is a first-layer metal wiring, and (4) ) is an interlayer insulating film, and (5) is a second layer metal wiring.
すなわち、従来の半導体装置では、半導体基板(1)
上を、リンシリケートガラス膜(PSG)からなる絶縁
膜(2)で平坦化した後、Aj’からなる第1層金属配
線(3)を形成し、1間絶縁膜(4)としてプラズマ窒
化けい素膜を積み、その上にAlからなる第2層金属配
線(5)を形成して2層配線を構成していた。That is, in a conventional semiconductor device, a semiconductor substrate (1)
After flattening the upper surface with an insulating film (2) made of phosphosilicate glass film (PSG), a first layer metal wiring (3) made of Aj' is formed, and a plasma silicon nitride film is formed as an interlayer insulating film (4). A two-layer wiring was constructed by stacking elementary films and forming a second layer metal wiring (5) made of Al on top of the layers.
従来の半導体装置は以上のように構成されており、第1
層金属配線にもとづく極端な凹凸を残したまま、ひき続
きこの上に第2層金属配線層を形成しようとするので、
微細なパターニングは困難になり、配線の段切れや短絡
を起こしたり、または段差部の膜厚が薄くなって信頼性
が悪くなるなどの問題があった。The conventional semiconductor device is configured as described above, and the first
The second layer metal wiring layer is subsequently formed on top of this while leaving the extreme unevenness caused by the layer metal wiring.
Fine patterning becomes difficult, leading to problems such as breakage or short circuits in the wiring, or a reduction in film thickness at stepped portions, resulting in poor reliability.
この発明は上記のような問題点を解消するためになされ
たもので、複数層配線構造における配線の段切れや短絡
の発生をなくすことができるとともK、上層の配線の膜
厚を均一にすることができる半導体装置の製造方法を得
ることを目的としている。This invention was made in order to solve the above-mentioned problems, and it is possible to eliminate the occurrence of disconnections and short circuits in the wiring in a multi-layer wiring structure, and also to make the film thickness of the upper layer wiring uniform. The purpose of the present invention is to obtain a method for manufacturing a semiconductor device that can perform the following steps.
この発明に係る半導体装置の製造方法では下層配線形成
後、配線に絶縁膜を枠付けしてテーパをつけ、そして層
間絶縁膜を形成した上に上層配線を形成するものである
。In the method of manufacturing a semiconductor device according to the present invention, after forming the lower layer wiring, the wiring is framed with an insulating film and tapered, and then the upper layer wiring is formed after forming an interlayer insulating film.
この発明における複数層配線の形成方法では下層配線形
成後絶縁膜を枠付けして、これにテーパをつけることK
より、極端に急激な凹凸が解消され、平滑化され、上層
の配線を良好な形態に形成できる。In the method for forming multi-layer wiring in this invention, after forming the lower layer wiring, an insulating film is framed and tapered.
As a result, extremely sharp unevenness is eliminated and smoothed, and the upper layer wiring can be formed in a good shape.
第1図A〜Eはこの発明の一実施例方法の主要工程段階
での状態を示す断面図で、第2図の従来例と同一符号は
同等部分を示す。FIGS. 1A to 1E are cross-sectional views showing the main process steps of a method according to an embodiment of the present invention, and the same reference numerals as in the conventional example in FIG. 2 indicate equivalent parts.
まず、半導体基5に常圧OVD法によってリンガラスか
らなる絶縁膜(2)を形成して上面を平坦化した後、そ
の上に第1層金属配線(3)を形成する(第1図A)。First, an insulating film (2) made of phosphorous glass is formed on the semiconductor substrate 5 by the atmospheric pressure OVD method to flatten the upper surface, and then a first layer metal wiring (3) is formed on it (see FIG. 1A). ).
次いで、第1層金属配線(3)の上を含め絶縁膜(2)
の上にプラズマCvD法で段差部平滑化用絶縁膜として
シリコン窒化膜(6)を形成する(第1図B)z次に、
シリコン窒化膜(6)の全上面からりアクティブイオン
エツチング(R工E)を施して第1層金属配線(3)の
両側面部のみにテーパをもって枠付けしたようにシリコ
ン窒化膜(6)を残す(第1図C)。続いて全上面に外
囲プラズマCVD法で層間絶縁膜としてのシリコン窒化
膜(4)を形成することによって表面の平滑化を達成す
る(第1図D)っそして、その上に第2層金属配線(5
)を形成する(第1図E)ワ
上記実施例では段差部平滑化用絶縁膜及び層間絶縁膜に
シリコン窒化膜を用いたが層間絶縁機能を果すものであ
ればよい。更に、上記実施例では第1#配線とその上の
第2層配線とについて述べたが多層配線の任意の連続す
る2層の配線に適用できる。Next, an insulating film (2) is formed, including on the first layer metal wiring (3).
A silicon nitride film (6) is formed as an insulating film for smoothing the stepped portion by plasma CVD method (Fig. 1B).Next,
Active ion etching (R process E) is applied to the entire upper surface of the silicon nitride film (6), leaving the silicon nitride film (6) tapered and framed only on both side surfaces of the first layer metal wiring (3). (Figure 1C). Next, a silicon nitride film (4) as an interlayer insulating film is formed on the entire upper surface using an envelope plasma CVD method to achieve surface smoothness (Fig. 1D). Wiring (5
) (FIG. 1E) In the above embodiment, a silicon nitride film was used as the insulating film for smoothing the stepped portion and the interlayer insulating film, but any film may be used as long as it fulfills the interlayer insulating function. Further, in the above embodiment, the first # wiring and the second layer wiring thereon have been described, but the present invention can be applied to any two consecutive layers of multilayer wiring.
線を形成したのち、絶縁膜を枠付けして、この絶縁膜に
テーパをつけることによって、その上に形成する層間絶
縁膜の上面を平滑化した上に、上層金属配線を形成する
ようにしたので、配線の段切れや短絡が減少し分留りが
向上するとともに1均一な膜厚の上層金属配線が形成き
れ、泡頼性が向上する効果がある。After the lines are formed, an insulating film is framed, and this insulating film is tapered to smooth the upper surface of the interlayer insulating film formed on top of it, and then the upper layer metal wiring is formed. This has the effect of reducing wiring breaks and short circuits, improving fractionation, and forming upper layer metal wiring with a uniform film thickness, thereby improving foam reliability.
第1図はこの発明の一実施例方法の主要工程段階におけ
る状態を示す断面図、第2図は従来の半導体装置の2層
配線の構造を示す断面図である。
図において、(1)は半導体基板、(3)は下層(第1
層)金属配線、(4)は層間絶縁膜、(5)は上層(第
2#)金属配線、(6)は段差部平滑化用絶縁膜である
。
なお、図中同一符号は同一または相当部分を示す0FIG. 1 is a cross-sectional view showing the main process steps of a method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure of a two-layer wiring of a conventional semiconductor device. In the figure, (1) is the semiconductor substrate, (3) is the lower layer (first
(4) is an interlayer insulating film, (5) is an upper layer (#2) metal wiring, and (6) is an insulating film for smoothing the stepped portion. In addition, the same symbols in the figures indicate the same or corresponding parts.
Claims (1)
して、基体上に下層金属配線を形成し、この下層金属配
線を覆うように上記基体上に段差部平滑化用絶縁膜を形
成し、この段差部平滑化用絶縁膜に上方から反応性イオ
ンエッチング等を施して、上記下層金属配線の側壁部の
みに残した後に、上記下層金属配線及びその側壁部に残
つた段差部平滑化用絶縁膜を覆うように上記基体上に層
間絶縁膜を形成し、この層間絶縁膜の上に上層金属配線
を形成することを特徴とする半導体装置の製造方法。(1) When manufacturing a semiconductor device having multiple layers of wiring, a lower metal wiring is formed on a base, an insulating film for smoothing the stepped portion is formed on the base so as to cover the lower metal wiring, and this After reactive ion etching or the like is applied to the step smoothing insulating film from above and leaving it only on the side wall of the lower metal wiring, the step smoothing insulating film remains on the lower metal wiring and its side wall. 1. A method of manufacturing a semiconductor device, comprising forming an interlayer insulating film on the base so as to cover the substrate, and forming an upper layer metal wiring on the interlayer insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24954285A JPS62108542A (en) | 1985-11-06 | 1985-11-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24954285A JPS62108542A (en) | 1985-11-06 | 1985-11-06 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62108542A true JPS62108542A (en) | 1987-05-19 |
Family
ID=17194535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24954285A Pending JPS62108542A (en) | 1985-11-06 | 1985-11-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62108542A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0289318A (en) * | 1988-09-27 | 1990-03-29 | Nec Corp | Manufacture of multilayer interconnected semiconductor integrated circuit device |
WO2016203970A1 (en) * | 2015-06-16 | 2016-12-22 | 株式会社Ihi | Sealing structure and supercharger |
-
1985
- 1985-11-06 JP JP24954285A patent/JPS62108542A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0289318A (en) * | 1988-09-27 | 1990-03-29 | Nec Corp | Manufacture of multilayer interconnected semiconductor integrated circuit device |
WO2016203970A1 (en) * | 2015-06-16 | 2016-12-22 | 株式会社Ihi | Sealing structure and supercharger |
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