JPH07147281A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a flat interlayer insulating film, in which steps between wirings are reduced, by a method wherein such a second insulating film as to make slow the film-forming rate of a silicon oxide film is held formed on a lower wiring layer and the film-forming rate of the silicon oxide film on the wiring layer is made to differ from that of the silicon oxide film on a wiring space region. CONSTITUTION:A field insulating film 2 is formed on a semiconductor substrate 1, a semiconductor element is formed on an active region on the substrate 1 and thereafter, a first insulating film 3 is formed on the film 2. Then, after a conductive film for first wiring layer and a second insulating film 5 are formed in order on the film 3, this conductive film is etched to form a first wiring layer 4. At this time, the film-forming rate of a silicon oxide film 6, which is formed on the film 5 on the layer 4, is formed slower than that of the film 6 on a wiring space region on the film 3. Accordingly, a step between the upper part of the wiring space region and the upper part of the layer 4 is dissolved and the surface of the film 6 can be roughly flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an interlayer insulating film structure of multi-layer wiring.

[0002]

2. Description of the Related Art As the width and space of wirings become finer and wiring layers become multi-layered as semiconductor integrated circuit devices become highly integrated, an interlayer insulating film for insulating lower wirings from upper wirings. A technology capable of further flattening is required.

When the wiring space becomes fine, the burying property of the interlayer insulating film in the wiring space region deteriorates, and it becomes difficult to eliminate the wiring step especially in the dense wiring region.
As a result, the wiring length of the upper layer wiring routed over the wiring step becomes long, and the signal transmission speed decreases. In addition, stress concentration in the wiring is likely to occur, and it becomes weak against stress migration and electromigration.

If the wiring step cannot be eliminated sufficiently,
After forming the interlayer insulating film, there is a difference in elevation between a region where the wiring is dense and a region where the wiring is rough. In the multi-layer wiring structure, the difference in elevation is accumulated in the upper layer wiring, so that it becomes more difficult to process the wiring and the connection hole in the upper layer wiring, and the wiring is short-circuited due to the deformation of the processed shape.

Further, when the altitude difference occurs in the interlayer insulating film, the aspect ratio of the connection hole opened in the high altitude region becomes large, and the disconnection easily occurs inside the connection hole. On the contrary, in a region of low altitude, the distance between the lower layer wiring and the upper layer wiring becomes too short, so that there is a risk that the capacitance between the wirings increases and the signal transmission speed decreases.

As an interlayer insulating film for multilayer wiring, a spin-on-glass (Spin On Glass) film is provided between two silicon oxide films.
s) An interlayer insulating film having a three-layer structure sandwiching the film, a silicon oxide film by a normal pressure CVD method using tetraethyl ortho Silicate (hereinafter referred to as TEOS) and ozone are known.

[0007]

As the interlayer insulating film having the three-layer structure, a lower silicon oxide film is first formed by a plasma CVD method, an intermediate spin-on-glass film is spin-coated thereon, and this is heat treated. After being densified by, the surface is flattened by etch back, and an upper silicon oxide film is further formed on this spin-on-glass film by the plasma CVD method. This interlayer insulating film is characterized in that, since the spin-on-glass film of the intermediate layer has fluidity, the stepped shape of the lower layer wiring can be relaxed and the step coverage of the upper layer wiring can be improved.

However, when the wiring space of the silicon oxide film formed by the plasma CVD method is miniaturized to about 0.3 [μm], the filling property in the wiring space region deteriorates and voids are formed in the film. There is a problem that it tends to occur. Further, the spin-on-glass film has a low moisture resistance and the film quality is unstable, so that gas is generated and the reliability of the interlayer insulating film is deteriorated.

On the other hand, atmospheric pressure C using TEOS and ozone
The silicon oxide film formed by the VD method is superior to the silicon oxide film formed by the plasma CVD method in the burying property in a fine wiring space region, but the flatness in a wide wiring space region is poor, so that spin-on is currently performed. There is a problem that it must be used together with a glass membrane.

An object of the present invention is to provide a technique capable of forming a flat interlayer insulating film that does not depend on a step difference in the underlying layer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

According to the first aspect of the invention, an interlayer insulating film for insulating the lower wiring and the upper wiring of the semiconductor integrated circuit is formed by the following steps (a) to (f).

(A) First, a first insulating film is formed on the main surface of a semiconductor substrate, and a conductive film for lower layer wiring is formed on the first insulating film. The first insulating film is composed of, for example, a silicon oxide film formed by a plasma CVD method using monosilane and nitrous oxide.

(B) Next, a second silicon oxide film is formed on the conductive film by the atmospheric pressure CVD method using TEOS and ozone at a lower deposition rate than the first insulating film.
Insulating film (for example, plasma C using TEOS and oxygen
A silicon oxide film or the like formed by the VD method is formed.

(C) Next, the conductive film is etched together with the second insulating film to form a lower layer wiring.

(D) Next, a silicon oxide film is formed on the semiconductor substrate by the atmospheric pressure CVD method using TEOS and ozone.

(E) Next, the silicon oxide film is etched back until at least the second insulating film on the lower wiring is exposed.

(F) Next, a third insulating film is formed on the silicon oxide film to obtain an interlayer insulating film composed of a laminated film of the silicon oxide film and the third insulating film.

[0020]

Before the step (step (d)) of depositing the silicon oxide film by the atmospheric pressure CVD method using TEOS and ozone, a second insulating film for slowing the film forming rate is formed on the lower layer wiring. By forming the silicon oxide film on the wiring and making the film formation speed of the silicon oxide film different between the wiring space area and the wiring space area, a flat interlayer insulating film with a reduced wiring step can be obtained.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 9 are cross-sectional views of essential parts of a semiconductor substrate showing a method of forming an interlayer insulating film in the order of steps.

First, as shown in FIG. 1, a field insulating film 2 for element isolation is formed on the main surface of a semiconductor substrate 1, a semiconductor element is formed in an active region (not shown), and then on the field insulating film 2. The first insulating film 3 is formed. The insulating film 3 is composed of, for example, a silicon oxide film formed by a plasma CVD method using monosilane and nitrous oxide.

Next, after a conductive film for the first layer wiring and a second insulating film 5 are sequentially formed on the insulating film 3, the conductive film and the insulating film 5 are etched as shown in FIG. As a result, the first layer wiring 4 is formed. At this time, the insulating film 5 is left on the first layer wiring 4. The conductive film for the first layer wiring 4 is
For example, it is made of a refractory metal such as Al alloy or W (tungsten). Further, the insulating film 5 uses atmospheric pressure CVD using TEOS and ozone as compared with the first insulating film 3.
Plasma C using an insulating film material such as TEOS and oxygen that slows the film formation rate of the silicon oxide film by the method
It is composed of a silicon oxide film formed by the VD method or a silicon nitride film formed by a plasma CVD method using monosilane and ammonia.

Next, as shown in FIG. 3, a silicon oxide film 6 is formed on the semiconductor substrate 1 by the atmospheric pressure CVD method using TEOS and ozone. At this time, the first insulating film 3 is formed in the wiring space region of the first layer wiring 4,
Compared to the insulating film 3, the silicon oxide film 6 is formed on the layer wiring 4.
Since the second insulating film 5 having a low film forming speed is formed, the silicon oxide film 6 is formed relatively fast on the wiring space region and relatively slowly on the first layer wiring 4. . Therefore, by making the thickness of the silicon oxide film 6 sufficiently thick, the step between the wiring space region and the first layer wiring 4 can be eliminated, and the surface of the silicon oxide film 6 can be substantially flattened. it can.

As described above, in this embodiment, the deposition rate of the silicon oxide film 6 on the surface of the first insulating film 3 and the deposition rate of the silicon oxide film 6 on the surface of the second insulating film 5 are increased. Therefore, the materials of the insulating films 3 and 5 are not limited to those described above.

For example, the first insulating film 3 is replaced by the second insulating film 5
Of the same material (a silicon oxide film formed by the atmospheric pressure CVD method using TEOS and ozone), and then the surface of the first insulating film 3 is subjected to a nitrogen plasma treatment or the like. The silicon oxide film 6 may be modified so as to increase the deposition rate. Further, a passivation treatment or an aluminum chelate treatment is performed on the surface of a silicon oxide film formed by a plasma CVD method using TEOS and oxygen or a silicon nitride film formed by a plasma CVD method using monosilane and ammonia. The second insulating film 5 may be modified so that the film formation rate of the silicon oxide film 6 is reduced.

Next, as shown in FIG. 4, the silicon oxide film 6 is etched back. This etch back is performed in order to match the film thickness of the interlayer insulating film with the design value. Further, since the silicon oxide film 6 deposited on the second insulating film 5 may deteriorate in film quality, this etchback removes the deteriorated silicon oxide film 6 on the second insulating film 5. There is also a purpose to do. Therefore, this etch back is performed at least until the insulating film 5 on the first layer wiring 4 is exposed.

The etch back is carried out by the usual dry etching method or CMP (chemical mechanical pol).
ishing) method (chemical mechanical polishing method) may be used. When etching back is performed by the CMP method, it is very effective to configure the second insulating film 5 with a silicon nitride film formed by the plasma CVD method, since the second insulating film 5 also serves as a polishing stopper.

Next, as shown in FIG. 5, a third insulating film 7 is formed on the semiconductor substrate 1, and the insulating film 7 and the silicon oxide film 6 form an interlayer insulating film 11. The third insulating film 7 is made of, for example, the same material as that of the first insulating film 3. After that, the insulating film 7 on the first layer wiring 4 is etched to form the connection hole 8.

Next, after a conductive film for the second layer wiring and the fourth insulating film 10 are sequentially formed on the interlayer insulating film 11,
As shown in FIG. 6, the conductive film and the insulating film 10 are etched to form the second layer wiring 9. At this time, the insulating film 10 is left on the second layer wiring 9. The conductive film for the second layer wiring 9 is made of, for example, an Al alloy or a refractory metal such as W. Further, the insulating film 10 is an insulating film material that slows the film formation rate of the silicon oxide film by the atmospheric pressure CVD method using TEOS and ozone as compared with the third insulating film 7, that is, the second insulating film material. It is made of the same material as the insulating film 5.

Next, as shown in FIG. 7, a silicon oxide film 12 is formed on the semiconductor substrate 1 by the atmospheric pressure CVD method using TEOS and ozone, and then this silicon oxide film 12 is formed.
To etch back. The third insulating film 7 is exposed in the wiring space area of the second layer wiring 9, and the film formation rate of the silicon oxide film 12 on the second layer wiring 9 is slower than that of the third insulating film 7. Since the insulating film 10 is formed, the silicon oxide film 12 is relatively fast on the wiring space region,
The film is formed relatively slowly on the second layer wiring 9. Therefore, by making the film thickness of the silicon oxide film 12 sufficiently thick,
The step between the wiring space region and the second layer wiring 9 can be eliminated, and the surface of the silicon oxide film 12 can be substantially flattened. The purpose of the subsequent etch back is the same as the etch back of the silicon oxide film 6.

Next, as shown in FIG. 8, a fifth insulating film 13 is formed on the semiconductor substrate 1, and the fifth insulating film 13 and the silicon oxide film 12 form a second interlayer insulating film 14. Make up. The fifth insulating film 13 is made of, for example, the same material as the first insulating film 3. Then, the insulating film 13 on the second layer wiring 9 is etched to form the connection hole 15.

After that, the above-mentioned steps are repeated to form the third layer wiring 16 as shown in FIG. Reference numeral 17 in the figure is the same TEO as the silicon oxide film 12.
A silicon oxide film formed by an atmospheric pressure CVD method using S and ozone, and 18 is a final passivation film.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-mentioned embodiment, the case where the present invention is applied to a three-layer wiring structure has been described as an example, but it is also possible to apply to a four-layer or more wiring structure.

[0036]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). Since a flat interlayer insulating film that does not depend on the step of the lower layer wiring can be formed, it is possible to suppress a decrease in signal transmission speed due to an increase in the wiring length of the upper layer wiring.

(2) It is possible to relieve the stress concentration in the upper layer wiring and prevent disconnection failure due to stress migration or electromigration.

(3) Since the elevation difference between the dense wiring area and the rough area can be reduced, the upper layer wiring and the connection hole can be easily processed, and the connection reliability of the wiring is improved. be able to.

(4) The distance between the lower layer wiring and the upper layer wiring becomes uniform, and it is possible to suppress the decrease in the signal transmission speed due to the capacitance between the wirings.

(5). Since the number of wiring layers can be promoted, a high-speed and highly integrated integrated circuit can be realized.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 insulating film 4 first layer wiring 5 insulating film 6 silicon oxide film 7 insulating film 8 connection hole 9 second layer wiring 10 insulating film 11 interlayer insulating film 12 silicon oxide film 13 insulating film 14 interlayer insulating Film 15 Connection hole 16 Third layer wiring 17 Silicon oxide film 18 Final passivation film

Claims (7)

[Claims] 1. The following steps in forming an interlayer insulating film for insulating lower wiring and upper wiring of a semiconductor integrated circuit:
A method of manufacturing a semiconductor integrated circuit device, comprising: (a) to (f). (a) After forming the first insulating film on the main surface of the semiconductor substrate,
Forming a conductive film for lower layer wiring on the first insulating film; (b) Atmospheric pressure CVD using tetraethyl orthosilicate and ozone on the conductive film as compared with the first insulating film
Forming a second insulating film such that the film formation rate of the silicon oxide film is slowed by the method. (c) A step of etching the conductive film together with the second insulating film to form a lower wiring. (d) A step of forming a silicon oxide film on the semiconductor substrate by an atmospheric pressure CVD method using tetraethyl orthosilicate and ozone. (e) A step of etching back the silicon oxide film until at least the second insulating film on the lower wiring is exposed. (f) A step of forming a third insulating film on the silicon oxide film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is a silicon oxide film formed by a plasma CVD method using monosilane and nitrous oxide. . 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second insulating film is a silicon oxide film formed by a plasma CVD method using tetraethylorthosilicate and oxygen. . 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second insulating film is a silicon nitride film formed by a plasma CVD method using monosilane and ammonia. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the etch back is performed by using a chemical mechanical polishing method. 6. A connection hole for connecting a lower layer wiring and an upper layer wiring is formed in the third insulating film, a conductive film for an upper layer wiring is formed on the third insulating film, and then the step ( b) ~
2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein by repeating (f), an upper layer wiring and a second interlayer insulating film for insulating the upper layer wiring and the wiring in the upper layer from each other are formed. . 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein tetramethoxysilane, hexamethyldisilazane, or octamethylcyclotetrasiloxane is used in place of the tetraethylorthosilicate.