JPH04355951A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be lessened in through-hole resistance and enhanced in resistance to electromigration by a method wherein an upper wiring layer is formed, then a through-hole is bored, and then a metal plug is formed. CONSTITUTION:A first wiring layer 3 formed on an insulating film 101 is processed into a required pattern, a first interlayer film 104 and second wiring layers 107 and 108 are formed, and a through-hole is bored in the layers 107 and 108 using a photoresist mask. Then, a metal plug 109 is formed on the first wiring layer 103 thicker than the first interlayer film 104, whereby the first wiring layer 103 is electrically connected to the second wiring layer 106. When a wiring layer is formed furthermore, a second interlayer film 110 and a third wiring layer 111 are formed, a through-hole is bored, and a metal plug 113 is formed on the second wiring layer 107 thicker than the second interlayer film 110 so as to electrically connect the second wiring layer 107 to the third wiring layer 111.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of wiring layers and a method for manufacturing the same.

0002

[Prior Art] Conventionally, in a method for manufacturing a semiconductor device having a multilayer wiring structure, after forming a lower wiring layer, an interlayer insulating film is formed, and desired holes are opened in the interlayer insulating film using a photoresist pattern as a mask. Then, it was customary to form an upper wiring layer within the hole and on the interlayer insulating film by sputtering or the like. However, when manufacturing a semiconductor device having a fine pattern, the diameter of the hole becomes fine, and the upper wiring layer formed in the hole may be disconnected due to overhang or the film quality may deteriorate.

On the other hand, when manufacturing semiconductor devices having fine patterns, chemical vapor deposition (hereinafter abbreviated as CVD) is used.
A wiring metal film has been formed by filling a hole in an insulating film with a metal such as tungsten (W) using a method. For example, the method described in JP-A-62-31116 is
Selective chemical vapor deposition (hereinafter referred to as selective CV) is applied to contact holes.
A W film is formed using a method (abbreviated as D), and then an Al wiring connected to the W film is formed on the insulating film. In the semiconductor device manufactured by this method, as shown in FIGS. 3A and 3B, a W plug 120 is provided in a hole in an interlayer film 119 on a W wiring 118 provided on an insulating film 117. It has a unique structure. This W plug 120 and Al alloy wiring 121
Alternatively, a precipitate 122 or a reaction layer 124 is formed at the interface of the pure Al wiring 123, which increases contact resistance or causes local electromigration deterioration due to the formation of the reaction layer, resulting in problems such as disconnection between wiring layers. .

In order to solve these problems, a semiconductor device has been proposed, for example, as described in Japanese Patent Application Laid-Open No. 145774/1983. This device has a TiN film and a TiSi2 film, which are barrier metals, between the W plug and the Al wiring.

Further, a semiconductor device described in Japanese Patent Application Laid-Open No. 63-237443 has a multilayer wiring structure in which at least a first wiring layer and a second wiring layer are laminated on a semiconductor substrate with an insulating film interposed therebetween. A hole is provided that extends across the wiring layer and the second wiring layer to the diffusion layer of the semiconductor substrate, and has a conductor layer within the hole.

[0006]

[Problem to be solved by the invention] The above-mentioned Japanese Patent Application Laid-Open No. 62-31
In the prior art described in No. 116, when the material of the Al wiring formed on the W film buried in the hole of the insulating film is an Al alloy containing 0.5% or more of Si, the W film buried in the hole is There was a problem in that Si grains were selectively precipitated at the interface between the aluminum wiring and the aluminum wiring, increasing the through-hole resistance. Also,
When the material of this Al wiring is pure Al, a reaction layer is formed at the interface between the W film buried in the hole and the Al wiring, locally deteriorating the electromigration resistance, and as this progresses, the reaction layer is formed at the interface between the W film filled in the hole and the Al wiring. There was a problem in that contact failure occurred at the interface between the W film and the Al wiring.

The conventional technique described in the above-mentioned Japanese Patent Laid-Open No. 62-145774 has the problem that it is necessary to form two layers of TiN film and TiSi2 film as the barrier metal, which complicates the manufacturing process. Furthermore, when manufacturing a semiconductor device with a multilayer wiring structure having a fine pattern, the alignment margin when forming through holes between wiring layers is extremely small, making it extremely difficult to align the through holes with the underlying wiring layer. However, there was a problem in that disconnections between wiring layers occurred due to poor alignment.

[0008] In the conventional technique described in the above-mentioned Japanese Patent Laid-Open No. 63-237443, the height of the hole becomes extremely high, so when forming a conductive layer in the hole, the second wiring layer and the diffusion layer are not connected due to insufficient coverage. There was a problem that poor conduction occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has low through-hole resistance, excellent electromigration resistance characteristics of wiring, and eliminates disconnection between wiring layers, a method for manufacturing such a semiconductor device, and a through-hole between wiring layers. It is an object of the present invention to provide a method for manufacturing a semiconductor device which allows easy alignment of the semiconductor device and which can be performed using a relatively simple method.

0010

[Means for Solving the Problems] The above objects are: (1) a first wiring layer disposed on a substrate; a second wiring layer disposed on the first wiring layer with an insulating film interposed therebetween; In a semiconductor device having a metal plug that electrically connects the first and second wiring layers, the metal plug passes through a through hole provided in the second wiring layer from the top surface of the first wiring layer. (2) A semiconductor device according to item 1 above, wherein the metal plug and the material of at least the surface of the second wiring layer are different materials. A semiconductor device characterized in that an upper part of the plug is substantially at the same height as an upper part of the second wiring layer, (3) a step of forming a first wiring layer in a desired pattern on a substrate; forming an interlayer insulating film and a second wiring layer on the first wiring layer; forming a through hole in the second wiring layer and the interlayer insulating film;
(4) A method for manufacturing a semiconductor device according to item 3 above, which comprises at least the step of forming a metal plug that electrically connects the wiring layer and the second wiring layer. (5) A method for manufacturing a semiconductor device according to item 3 above, wherein the formation of the metal plug is performed by selective chemical vapor deposition. (6) A method for manufacturing a semiconductor device, characterized in that it is carried out by
In the method for manufacturing a semiconductor device according to any one of 3 to 5 above, the metal plug has an upper portion thereof substantially the same height as the upper surface of the second wiring layer. (7) In the method for manufacturing a semiconductor device according to any one of 3 to 5 above, the material of the first wiring layer and the material of at least the surface of the second wiring layer are:
This is achieved by a method of manufacturing a semiconductor device characterized in that the materials are different from each other.

[0011]

[Operation] As shown in FIG. 1, after processing the first wiring layer 103 formed on the insulating film 101 into a desired pattern, the first
An interlayer film 104 and second wiring layers 106 and 107 are formed, and through holes are opened in the two layers using photoresist as a mask. Next, the first wiring layer 10 is formed using the CVD method.
By forming the metal plug 109 thicker than the first interlayer film 104 on the first wiring layer 103 and the second wiring layer 1
06 is electrically connected.

[0012] Furthermore, when forming a further wiring layer, a second wiring layer is formed.
After forming the interlayer film 110 and the third wiring layer 111 and drilling through holes in the same manner as in the above method, a metal plug 113 is placed on the second wiring layer 107 using the CVD method.
By forming the layer thicker than 0, the second wiring layer 107 and the third wiring layer 111 are electrically connected.

[0013] Note that the metal plugs 109, 11 are
3, a metal material may be formed on the entire surface and the surface may be etched to leave a metal plug part;
It is preferable to form the metal plug only on the lower wiring layer by the VD method. In this case, the first wiring layer 103 and the second
It is necessary that the material of the wiring layer 106 and the materials of the second wiring layer 107 and the third wiring layer 111 are different metals. For example, W is used for the lower wiring layer, and Al is used for the upper wiring layer. In addition, the lower wiring layer is made of Al, and the upper wiring layer is made of M.
Use o. In either case, the metal plug is W or C.
u, Al or metal silicide.

Furthermore, as shown in FIG. 2, the first wiring layer 10
3 and the second wiring layer 106 are made of the same kind of metal, and the second wiring layer 10
A metal thin film 114 different from the second wiring layer 106 may be formed on the second wiring layer 106 . Similarly, the second wiring layer 107 and the third wiring layer 1
11 may be made of the same metal, and a metal thin film 116 of a different type from the metal thin film 115 may be formed on the third wiring layer 111. Note that the metal thin film 116 may be replaced with an insulating film. For example, W, Al, etc. are used as the material for the wiring layer, and TiN is used as the metal thin film. In addition, the insulating film is SiO
2. Use Al2O3.

Further, it is preferable to perform heat treatment after forming the metal plugs 109 and 113. This allows the second
The wiring layer 106 and the third wiring layer 111 thermally expand, and the interface between the metal plug 109 and the second wiring layer 106 and the metal plug 1
The adhesion at the interface between the wiring layer 13 and the third wiring layer 111 becomes good. Therefore, the reliability of the wiring in the through hole can be improved without forming precipitates or reaction layers at these interfaces.

Further, as shown in FIG. 4A, a metal plug 132 for electrically connecting the first wiring layer 127 and the second wiring layer 130 is connected to the first wiring layer 127 and the second wiring layer 130. It is not necessary to make the wiring width smaller than the wiring width, and it is sufficient that the wiring width is electrically insulated from the adjacent first wiring layer 128 and second wiring layer 131. Therefore, the size of the metal plug 132 can be selected with a certain margin, and is preferably larger than the wiring width of the first wiring layer 127 and the second wiring layer 130. This is the first wiring layer 127 and the second wiring layer 1.
This is because the through-hole resistance between 30 and 30 is inversely proportional to the cross-sectional area of the through-hole, so that the through-hole resistance can be minimized.

FIG. 4 (
Shown in b). Insulating film 12 provided on Si substrate 125
A first wiring layer 127 is arranged on top of the wiring layer 6 . The metal plug 132 selectively formed on the first wiring layer 127 is formed to be thicker than the first interlayer film 129 and is insulated from the second wiring layer 131 . Also, B in Fig. 4(a)
-B' is shown in FIG. 4(c). First wiring layer 12
The metal plug 132 formed only on the first wiring layer 128 is electrically insulated from the first wiring layer 128 by the first interlayer film 129.
Furthermore, in order to electrically conduct with the second wiring layer 130, it is necessary to form the film thicker than the first interlayer film 129. The height of the metal plug 132 is preferably made to match the height of the second wiring layer 130 in order to flatten the surface of the semiconductor manufacturing device.

Thereby, the through-hole resistance between the first wiring layer 127 and the second wiring layer 130 can be minimized, and the electromigration resistance of the second wiring layer 130 can be improved.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. Embodiment 1 FIGS. 5, 6, and 7 are process diagrams for manufacturing a semiconductor device according to an embodiment of the present invention. A first wiring film 102 made of W is formed on an insulating film 101 made of phosphorus glass (PSG).
first by sputtering method, then by CVD method at 150nm.
It is formed to have a thickness of m (FIG. 5(a)). Next, using the photoresist 160 as a mask (FIG. 5(b)), the first wiring film 1 is
02 by dry etching to form a first wiring layer 103 (FIG. 5(c)). Next, PSG,
SOG (spin-on glass; a material that is essentially SiO2 made by thermosetting coated glass) and PSG.
A first interlayer film 104 having a thickness of 0.4 μm is formed, and a second wiring film 105 made of Al-1%Si is formed.
is formed with a thickness of 0.5 μm by sputtering method (Fig. 5 (
d)).

Furthermore, using the photoresist as a mask, a second
The wiring film 105 is etched into a desired pattern to form second wiring layers 106 and 107 (FIG. 6(a)). Furthermore, the second wiring layer 106 is dry-etched using the photoresist as a mask, and then the first interlayer film 104 is dry-etched to open a through hole 108 (FIG. 6(b)).
). Next, in order to electrically conduct the first wiring layer 103 and the second wiring layer 106, a W metal plug 109 is formed by selective CVD (FIG. 6(c)).
). Note that the height of the metal plug 109 is higher than that of the first interlayer film 10.
The thicknesses of the two-layer film 4 and the second wiring layer 106 were made to match.

[0021] Furthermore, when forming upper layer wiring,
A second interlayer film 110 is formed using a method similar to that described above, and an Al film 111a having a thickness of 0.9 μm is formed by a sputtering method.
and a thickness of 0.1 μm formed by reactive sputtering method.
A third wiring layer 111 made of a TiN film 111b was formed (FIG. 7(a)). Hereinafter, the third wiring layer 111 and the second interlayer film 111 are connected to each other using a photoresist as a mask in the same manner as described above.
is etched to open a through hole 112 (Fig. 7
(b)). Next, through-hole 1 is made using selective CVD method.
A metal plug 113 is formed in 12 to electrically connect the second wiring layer 107 and the third wiring layer 111 (FIG. 7(c)).
. Note that the height of the metal plug 113 was made to match the thickness of the two-layer film of the second interlayer film 110 and the third wiring layer 111.

Embodiment 2 The manufacturing process of a semiconductor device according to another embodiment of the present invention is shown in FIGS. 8, 9, and 10. N-type Si
oxidizing the surface of the substrate 133 to form a SiO2 layer 134;
This SiO2 layer 134 is etched using a photoresist mask to form a desired pattern, and using this pattern as a mask, impurity doping and impurity diffusion are performed to form a P well layer 135. (Figure 8(a)).

After removing the SiO2 layer 134 and forming an oxide film 136 on the substrate surface for stabilization, and then forming a Si3N4 film 137, etching is performed using a photoresist pattern 138 to obtain a desired pattern, and then a photoresist is formed on this. A pattern 139 is formed (FIG. 8(b)
). Using these patterns as a mask, a P layer 140 is formed by doping with impurities, and a photoresist pattern 13 is formed.
After removing 8,139, field oxidation is performed to form Si3
The N4 film 137 is removed and gate oxidation is performed (FIG. 8(c)
)). A polycrystalline Si film 141 with a thickness of 0.3 μm is formed,
A desired pattern is etched using a photoresist mask (FIG. 8(d)). Next, an insulating film 143 is formed, a desired pattern is formed using a photoresist mask, and impurity doping and diffusion are performed using this insulating film 143 and the polycrystalline Si film 141 as a mask to form a highly concentrated P-type impurity diffusion layer 14.
2 (FIG. 8(e)).

An insulating film 144 is formed to cover the high concentration P-type impurity diffusion layer 142 by the same method as above except for the insulation film 143, and a high concentration N-type impurity diffusion layer 145 is formed (see FIG. 9). a)). PS is applied to the entire surface except for the insulating film 144.
A G insulating film 146 is formed to a thickness of about 0.6 μm, and contact holes are formed at desired positions (FIG. 9(b)). Next, the W film 147 of the first layer wiring is made to have a thickness of about 0.2 μm.
It is first formed by a sputtering method and then by a CVD method, and is etched into a desired pattern using a photoresist as a mask (FIG. 9(c)). Note that the steps up to this point are the same as the conventional method.

Next, TEOS is used as the first interlayer film 148.
A laminated film of a plasma SiO2 film using (tetraethoxysilane) and SOG is formed to a thickness of about 0.6 .mu.m, and an Al film 149 of a second layer wiring is formed to a thickness of about 0.3 .mu.m by a sputtering method. Next, using the photoresist as a mask, the Al film 14 is
9 and the first interlayer film 148, and the W plug 150 is attached to the Al film 149 by selective CVD.
form the same height as the surface of the In this case, W film 1
W plug 150 for the pattern width 0.3 μm of 47
The size was 0.4×0.4 μm. Furthermore, the Al film 149 is etched into a desired pattern using the photoresist as a mask (FIG. 9(d)).

Furthermore, a second interlayer film 151 is similarly formed to a thickness of about 0.8 μm, and an Al film 152 of a third layer wiring is formed to a thickness of about 0.5 μm (FIG. 10(a)). Next, Al film 1
52 is etched into a desired wiring pattern using a photoresist as a mask, and an SiO2 film 153 is formed to a thickness of about 50 nm. Furthermore, using photoresist as a mask, a through hole 154 is opened in the three-layer film of the SiO2 film 153, the Al film 152, and the second interlayer film 151 (FIG. 10(b)). Next, the Al film 149 of the second layer wiring and the Al film 15 of the third layer wiring are formed.
2, a W plug 155 with a thickness of about 1.3 μm is formed by selective CVD, and a passivation film 156 with a thickness of about 0.3 μm is formed (see FIG. 10(c).
)).

[0027] As a result, it was possible to fill the through hole with the W film and flatten it, forming a wiring film with an excellent film covering shape, and at the same time, it was possible to increase the diameter of the through hole. We were able to obtain low through-hole resistance. In addition, CMOS exhibits good resistance to electromigration and has excellent reliability.
We were able to manufacture LSI.

[0028]

[Effects of the Invention] According to the present invention, by forming a through hole after forming an upper wiring layer and then forming a metal plug, there is sufficient margin for pattern alignment in the photoresist process, and the process is relatively simple. A semiconductor device could be manufactured using this method. As a result, it was possible to obtain a semiconductor device in which the through-hole resistance of the embedded metal plug was small, the wiring had excellent electromigration resistance, and disconnection between wiring layers was eliminated.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of the main parts of a semiconductor device.

FIG. 2 is a schematic cross-sectional view of the main parts of a semiconductor device.

FIG. 3 is a schematic cross-sectional view of main parts of a conventional semiconductor device.

FIG. 4 is a schematic plan view and a schematic cross-sectional view of a semiconductor device.

FIG. 5 is a process diagram showing a method for manufacturing a semiconductor device.

FIG. 6 is a process diagram showing a method for manufacturing a semiconductor device.

FIG. 7 is a process diagram showing a method for manufacturing a semiconductor device.

FIG. 8 is a process diagram showing a method for manufacturing a semiconductor device.

FIG. 9 is a process diagram showing a method for manufacturing a semiconductor device.

FIG. 10 is a process diagram showing a method for manufacturing a semiconductor device.

[Explanation of symbols]

101, 117, 126, 143, 144, 146
Insulating film 102 First wiring film 103, 127, 128 First wiring layer 104, 129
, 148 First interlayer film 105 Second wiring film 106, 107, 130, 131 Second wiring layer 108
, 112, 154 Through hole 109, 113, 1
32 Metal plugs 110, 151 Second interlayer film
111 Third wiring layer 111a, 149, 152 Al film 111b
TiN film 114, 115, 116 Metal thin film 118,
W wiring 119 interlayer film
120, 150, 155 W plug 121 Al alloy wiring
122 Precipitate 123 Pure Al wiring
124 Reaction layer 125
Si substrate
133 N-type Si substrate 134, 153 SiO2 layer
135 P well layer 136 Oxide film
137 Si3N4 film 138, 139 Photoresist pattern 140 P
layer
141 Polycrystalline Si film 142 High concentration P-type impurity diffusion layer 145
High concentration N type impurity diffusion layer 147 W film
156 Passivation film 160 Photoresist

Claims (7)

[Claims] 1. A first wiring layer disposed on a substrate; a second wiring layer disposed on the first wiring layer with an insulating film interposed therebetween;
In a semiconductor device having a metal plug electrically connecting the first and second wiring layers, the metal plug electrically connects the first and second wiring layers.
The metal plug is disposed from the top surface of the wiring layer through a through hole provided in the second wiring layer, and the material of the metal plug and the material of at least the surface of the second wiring layer are different materials from each other. Characteristic semiconductor devices. 2. The semiconductor device according to claim 1, wherein an upper part of said metal plug is substantially at the same height as an upper part of said second wiring layer. 3. A step of forming a first wiring layer in a desired pattern on a substrate; a step of forming an interlayer insulating film and a second wiring layer on the first wiring layer; A semiconductor comprising at least the steps of forming a through hole in an interlayer insulating film, and forming a metal plug electrically connecting the first wiring layer and the second wiring layer in the through hole. Method of manufacturing the device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the metal plug is formed by chemical vapor deposition. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the metal plug is formed by selective chemical vapor deposition. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the metal plug has an upper portion substantially the same height as an upper surface of the second wiring layer. A method for manufacturing a semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the material of the first wiring layer and the material of at least the surface of the second wiring layer are different materials. A method for manufacturing a semiconductor device.