JPH09312291A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-speed operation by enabling formation of a buried wiring structure made of a wiring material having low resistance without increasing the contact resistance. SOLUTION: With respect to each of electrode wiring layers 22, 26, a lateral side part substantially perpendicular to a substrate 21 and a lateral side part substantially parallel to the substrate 21 are in contact with diffusion barrier layers 29, 30 made of different materials. The inside of a contact hole 24 is filled by burying a conductive material 28 which is the same type as the material of the electrode wiring layers 22, 26. No diffusion barrier layer exists on the interface between the buried conductive material 28 and the electrode wiring layer 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of electrode wiring layers are buried and formed on the surface of a substrate and a method for manufacturing the same, and more particularly, a diffusion barrier layer is interposed between the electrode wiring layers. First, the present invention relates to a semiconductor device capable of realizing a low resistance and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a method for realizing a highly reliable electrode wiring structure in a highly integrated circuit, a groove is formed by etching in a portion of an insulating film where an electrode wiring is formed, and a conductive material serving as a wiring metal is deposited on the entire surface of the substrate. A so-called buried wiring structure has been proposed in which the groove is filled with a wiring metal. The buried wiring structure has recently been actively studied.

It has been reported that aluminum has hitherto been used as a conductive material to be a wiring metal and that good electrical characteristics can be obtained. Such a buried wiring structure has an advantage that a fine element can be easily formed because it is not necessary to fill the space between fine electrode wirings in a later step.

However, recently, from the viewpoint of improving the operating performance of the device, copper has been studied as a conductive material to be a wiring metal, and a new problem has arisen with it. That is, since copper easily diffuses in the oxide film, when the copper embedded wiring is formed by the method described above,
There is a problem that copper is diffused into the interlayer insulating film in the subsequent thermal process and the reliability of the device is lowered. Therefore, a technique of forming a diffusion barrier layer such as a titanium nitride film on the entire surface of the substrate prior to forming the copper buried wiring is being studied.

14 to 16 are process sectional views schematically showing a method of manufacturing a semiconductor device using such a technique. The substrate 1 on which the elements are formed, as shown in FIG.
The insulating film 2 is deposited on the upper portion, and the wiring groove 3 is formed in the insulating film 2. After forming the groove 3, as shown in FIG. 14B, titanium nitride (Ti
N) The film 4 is deposited. Next, as shown in FIG. 14C, a copper film 5 is deposited on the entire surface by a sputtering method, and thereafter, as shown in FIG. 14D, the copper film 5 on the upper surface is removed by an etch back method. It is removed by etching to form the lower electrode wiring layer 5a.

Next, as shown in FIG. 14E, the titanium nitride film 4 exposed on the upper surface is removed by etching, and the titanium nitride film 4 shown in FIG.
As shown in (f), a silicon nitride (SiN) film 6 and a SiO ₂ substrate 7 are sequentially deposited on the entire surface.

Next, as shown in FIG. 15 (g), a groove 8 and a contact hole 9 for forming an upper wiring layer are formed. Thereafter, as shown in FIG. 15 (h), the entire surface is nitrided. A titanium film (diffusion barrier layer) 10 is deposited. continue,
As shown in FIG. 16 (i), a copper film 11 is deposited on the entire surface, and as shown in FIG. 16 (j), the copper film 11 on the upper surface is removed by an etch back method to form an upper electrode wiring layer. 12 is formed.

However, according to a recent study by the present inventors, when a multilayer wiring structure is formed by using such a technique for forming a diffusion barrier layer, the following (A) and (B) are obtained. Problems began to emerge. (A) That is, when forming the upper electrode wiring layer, the diffusion barrier layer is formed prior to the upper electrode wiring layer, so that the lower electrode wiring layer 5 is formed as shown in FIG. There is a problem that the diffusion barrier layer is present in the contact portion between the electrode wiring layer 12 and the upper electrode wiring layer 12, which increases the contact resistance. (B) As a result, the total resistance value of the wiring route is significantly increased, even though the low resistance copper is used as the wiring metal.
There is a problem that the desired high speed operation of the I element cannot be realized.

[0009]

As described above, when a buried wiring is formed using a wiring metal that requires a diffusion barrier layer, a diffusion barrier is formed at the interface between the upper electrode wiring layer and the lower electrode wiring layer. Intervening layers increase contact resistance,
There is a problem that the desired high speed operation of the LSI element cannot be realized.

The present invention has been made in view of the above circumstances, and a semiconductor device capable of forming a buried wiring structure of a wiring material having a low resistance without increasing contact resistance and thus realizing high-speed operation, and its manufacture. The purpose is to provide a method.

[0011]

The invention according to claim 1 has a structure in which a plurality of electrode wiring layers are formed on a semiconductor substrate and the corresponding electrode wiring layers are connected to each other through contact holes. In the semiconductor device, the electrode wiring layer may be a semiconductor device in which a side surface portion substantially vertical to the substrate and a side surface portion substantially parallel to the substrate are in contact with diffusion barrier layers made of different materials.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the inside of the contact hole is filled with a conductive material of the same kind as that of the electrode wiring layer. The diffusion barrier layer does not exist at the interface between the conductive material and the electrode wiring layer.

Further, the invention according to claim 3 is the semiconductor device according to claim 1, wherein the diffusion barrier layer is either a layer substantially perpendicular to the substrate or a layer substantially parallel to the substrate. One or both of them is a semiconductor device formed of an amorphous conductor.

The layer of the diffusion barrier layer substantially perpendicular to the substrate is made of the same material as that provided inside the contact hole and the electrode wiring layer, which simplifies the process. It is preferable from the viewpoint of conversion.

Further, the invention according to claim 4 is a semiconductor device having a structure in which at least upper and lower electrode wiring layers are formed on a semiconductor substrate and the corresponding electrode wiring layers are connected through contact holes. In the manufacturing method of the above step, a step of forming an interlayer insulating film including a first diffusion barrier layer on the lower electrode wiring layer, and forming a groove for embedding the upper electrode wiring layer in the first diffusion barrier layer. A step of forming a layer in the interlayer insulating film so as to expose the layer, a step of forming a contact hole for connecting the formed groove and the lower electrode wiring layer in the interlayer insulating film,
Depositing a second diffusion barrier layer over the substrate,
Anisotropically etching the second diffusion barrier layer, leaving the second diffusion barrier layer only on the sidewalls of the trench and the contact hole, respectively, and forming the upper electrode wiring layer on the trench and the contact. A method of manufacturing a semiconductor device, the method including burying in a hole.

Further, the invention according to claim 5 is a semiconductor device having a structure in which at least upper and lower electrode wiring layers are formed on a semiconductor substrate and the corresponding electrode wiring layers are connected through contact holes. A step of forming an interlayer insulating film on the lower electrode wiring layer, a step of forming a groove for embedding the upper electrode wiring layer in the interlayer insulating film, Forming a contact hole for connecting the groove and the upper electrode wiring layer in the interlayer insulating film; depositing a first diffusion barrier layer on the entire surface of the substrate; and the first diffusion barrier. Anisotropically etching the layer to leave the first diffusion barrier layer only on the sidewalls of the trench and the contact hole, respectively, and the second diffusion on the top of the interlayer insulating film and the bottom of the trench. Selectively forming a wall layer, a method of manufacturing a semiconductor device including a step of embedding formed in the upper layer of the electrode wiring layer and the trench and contact hole.

According to a sixth aspect of the invention, in the method of manufacturing a semiconductor device according to the fourth or fifth aspect, the first and second diffusion barrier layers are formed of different materials. And a method of manufacturing a semiconductor device.

Therefore, in the invention corresponding to claim 1, by taking the above-mentioned means, the side surface portion substantially perpendicular to the substrate and the side surface portion substantially parallel to the substrate are different from each other in each electrode wiring layer. Since it is in contact with the diffusion barrier layer made of a material, by using anisotropic etching, for example, an embedded wiring structure made of a wiring material having a low resistance can be formed without increasing the contact resistance, and thus high-speed operation can be realized. it can.

In the invention according to claim 2, the inside of the contact hole is filled with the same conductive material as that of the electrode wiring layer, and diffused at the interface between the buried conductive material and the electrode wiring layer. Since the barrier layer does not exist, the conductive material and the lower electrode wiring layer are directly connected to each other, so that the resistance can be reduced and the same operation as that of the first aspect can be achieved.

Further, in the invention according to claim 3, in the diffusion barrier layer, one or both of the layer substantially vertical to the substrate and the layer substantially parallel to the substrate are formed of an amorphous conductor. Therefore, in addition to the same effect as that of claim 1, the amorphous conductor can be used as the electrode wiring while preventing the diffusion of the conductive material into the insulating film, so that the resistance can be further reduced. You can

Further, the invention according to claim 4 is the step of forming an interlayer insulating film including a first diffusion barrier layer on a lower electrode wiring layer, and a groove for embedding and forming an upper electrode wiring layer. Forming in the interlayer insulating film so as to expose the first diffusion barrier layer, and forming a contact hole in the interlayer insulating film for connecting the formed groove and the lower electrode wiring layer. A step of depositing a second diffusion barrier layer on the entire surface of the substrate, and a step of anisotropically etching the second diffusion barrier layer, leaving the second diffusion barrier layer only on the sidewalls of the groove and the contact hole, respectively. Since it includes the step of burying the upper electrode wiring layer in the groove and the contact hole, it can be easily and surely implemented in addition to the same operation as that of the first aspect.

Further, the invention according to claim 5 is the step of forming an interlayer insulating film on the lower electrode wiring layer, and the step of forming a groove for embedding the upper electrode wiring layer in the interlayer insulating film. A step of forming a contact hole in the interlayer insulating film for connecting the formed groove and the upper electrode wiring layer, a step of depositing a first diffusion barrier layer on the entire surface of the substrate, A step of anisotropically etching the diffusion barrier layer and leaving the first diffusion barrier layer only on the sidewalls of the trench and the contact hole respectively, and selecting the second diffusion barrier layer on the top of the interlayer insulating film and the bottom of the trench. And the step of burying the upper electrode wiring layer in the groove and the contact hole. Therefore, in addition to the same operation as that of claim 1, the diffusion barrier layer is formed in the interlayer insulating film. Only around each electrode wiring layer without including Since the dispersion barrier layer can be formed, it can be carried out more easily and reliably.

In the invention according to claim 6, the first and second diffusion barrier layers according to claim 4 or claim 5 are formed of different materials from each other. The same effect as that of the fifth aspect can be achieved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view schematically showing the configuration of a semiconductor device according to the first embodiment of the present invention. This semiconductor device includes an interlayer insulating layer 2 including a lower electrode wiring layer 22 on a semiconductor substrate 21 on which elements are formed.
3 and an interlayer insulating film 25 including a contact hole 24 on the lower electrode wiring layer 22.
4 has an interlayer insulating film 27 including an upper electrode wiring layer 26, and a lower electrode wiring layer 22 has a contact hole 25.
It has a buried wiring structure connected to the upper electrode wiring layer 26 through.

Here, the inside of the contact hole 24 is
The electrode wiring layers 22 and 26 are filled with the same conductive material 28. As will be described later, there is no diffusion barrier layer at the interface between the conductive material 28 embedded in the contact hole 24 and the lower electrode wiring layer 22, and the conductive material 28 and the lower electrode wiring layer 22 are Directly connected.

On the other hand, between the conductive material 28 and the interlayer insulating layers 23, 25, 27 in the contact hole 24 and in the lower and upper electrode wiring layers 22, 26, the interlayer insulating layer of the conductive material 28 is provided. Diffusion barrier layers 29, 30 for preventing diffusion into 23, 25, 27 are provided in between.

The diffusion barrier layers 29 and 30 are composed of a layer 30 which is substantially vertical to the substrate 21 and a layer 29 which is substantially parallel to the substrate, and are made of different materials. Lower and upper electrode wiring layers 22,
It touches 26.

The diffusion barrier layer 30 that is substantially vertical to the substrate 21 is formed by utilizing the vertical component remaining by anisotropic etching, and has a higher etching rate than the diffusion barrier layer 29 that is substantially parallel to the substrate 21. High quality material is used.

The diffusion barrier layer 29 substantially parallel to the substrate 21 is a diffusion barrier layer 30 substantially perpendicular to the substrate 21 by anisotropic etching.
Is used as a protective layer for the interlayer insulating films 23, 25, and 27 when the film is formed, and a material having a low etching rate in the anisotropic etching is used.

Next, a method of manufacturing such a semiconductor device will be described with reference to process sectional views of FIGS. In the following description, the silicon nitride film (SiN) corresponds to the diffusion barrier layer 29 substantially parallel to the substrate, and the WSiN film corresponds to the diffusion barrier layer 30 substantially perpendicular to the substrate.

Now, as shown in FIG.
1) A SiO ₂ film 32 having a thickness of about 1 μm is deposited as an interlayer insulating film on the n-type silicon substrate 31 whose main surface is a main surface by a CVD method, and then a silicon nitride film 33 having a thickness of about 100 nm is deposited on the entire surface. . Further, the SiO ₂ film 34 and the silicon nitride film 35 are formed on the silicon nitride film 33 by the CVD method.
Are sequentially deposited.

Next, as shown in FIG. 2B, a groove 36 is formed in the wiring formation region of the SiO ₂ film 34 and the silicon nitride film 35 by the well-known photolithography method and reactive ion etching method (RIE). It is formed. Silicon nitride film 34 and S
A two-step etching method is used to etch the iO ₂ 35.

Since the silicon nitride film 33 having a low etching rate is exposed at the time when the SiO ₂ film 34 is completely etched, the trench 36 is not excessively dug even if overetching is performed. Groove 36
The shape of can be processed uniformly.

Next, as shown in FIG. 2C, the WSiN film 37 is uniformly deposited on the entire surface by the CVD method. Then, the entire surface of the substrate is anisotropically etched by RIE using chlorine gas. As a result, as shown in FIG. 2D, the WSiN film 37a is formed only on the side wall portion inside the groove 36. Also in this case, as in the case described above,
When the iN film 37 is removed by etching, the silicon nitride film 33 is exposed at the bottom and the progress of etching is blocked. Therefore, even if overetching is performed, the shape of the groove is not deteriorated, and a uniform processed shape is formed over the entire surface of the substrate. Is obtained. Then, a copper (Cu) film is deposited on the entire surface by the CVD method to fill the groove 36.

After the groove 36 is filled, as shown in FIG. 3E, the copper layer on the upper surface is removed by the chemical mechanical polishing (CMP) method, and the lower electrode wiring layer 38 is formed. At this time, since the silicon nitride film 35 blocks the etching of the SiO ₂ film 34, a favorable lower electrode wiring layer 38 having a flat upper portion is formed.

Next, as shown in FIG. 3F, the silicon nitride film 39, the SiO ₂ film 40, and the
The silicon nitride film 41, the SiO ₂ film 42, and the silicon nitride film 43 are sequentially deposited. These SiO ₂ films 40, 42
In the multilayer film of the silicon nitride films 39, 41 and 43, contact holes with the upper layer wiring region and the lower layer are formed by photolithography and RIE. After a while, FIG.
As shown in (g), the WSiN film 44 is deposited on the entire surface of the substrate by the CVD method.

Next, as shown in FIG. 4H, the entire surface of the substrate is anisotropically etched by RIE using chlorine gas, and the WSiN film 44a is formed only on the sidewalls inside the groove 45 and the contact hole 46. It is formed.

Next, as shown in FIG. 4I, similarly to the case of the lower electrode wiring layer 38, a copper film is deposited on the entire surface by the CVD method, and the groove 45 and the contact hole 46 are formed in the copper film. Then, the copper film on the upper surface is removed by the CMP method to form the upper electrode wiring layer 47. At this time, the upper electrode wiring layer 47 and the lower electrode wiring layer 3 are simultaneously formed.
The electrical connection with 8 is completed.

Thereafter, by repeating the same method,
A buried wiring structure having two or more layers can be easily realized. As described above, according to the first embodiment, the inside of the contact hole 46 is embedded with the same conductive material as the electrode wiring layer 38, and the embedded conductive material and the electrode wiring layer 38 are separated from each other. Since there is no diffusion barrier layer at the interface,
Since the conductive material and the lower electrode wiring layer 38 are directly connected, the contact resistance does not increase and the element resistance does not decrease, so that a desired high-speed operation of the LSI element can be realized.

Further, the diffusion barrier layers 33, 35, 37a,
39, 41, 43 and 44a are layers 37 that are substantially perpendicular to the substrate.
a, 44a and layers 33, 35, 39, 4 substantially parallel to the substrate
Since 1 and 43 are made of different materials, a sufficient etching selection ratio should be obtained when removing unnecessary portions of the diffusion barrier layer by etching (when forming the substantially vertical layers 37a and 44a). It is easy to perform, and for example, even when a device is formed using a semiconductor substrate having a large diameter of 8 inches or more, processing with good uniformity can be performed.

Further, due to the presence of the diffusion barrier layer, even if the entire surface of the substrate is exposed to a high temperature heating process of 700 ° C. or higher after the above-mentioned buried wiring structure is formed, the copper wiring is exposed to the SiO ₂ films 32 and 3.
Good element performance can be obtained without diffusion into 4, 40, and 42.

Further, since all the diffusion barrier layers can be formed in a self-aligning manner, it is not necessary to use a photo-etching process, the number of processes can be minimized, and a high performance device can be formed at low cost. .

Next, a semiconductor device according to the second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view showing the configuration of this semiconductor device. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted, and only different parts will be described here.

That is, the device of this embodiment is a modification of the first embodiment, and specifically, the diffusion barrier layer 29a which is in contact with the first wiring electrode layer 22 and is substantially parallel to the substrate 21 is provided. The buried wiring structure is formed by ion implantation and the number of diffusion barrier layers is reduced.

Next, a method of manufacturing such a semiconductor device will be described with reference to process sectional views of FIGS. In the following description, the alumina (Al ₂ O ₃ ) film corresponds to a diffusion barrier layer substantially parallel to the substrate with respect to the lower electrode wiring layer,
The contact hole and the upper electrode wiring layer correspond to a diffusion barrier layer substantially perpendicular to the substrate. The silicon nitride film and the ion implantation layer of niobium correspond to the diffusion barrier layer substantially parallel to the substrate.

Now, as shown in FIG. 6A, the SiO ₂ film 5 is formed on the semiconductor substrate 51 on which the transistor structure is formed.
2 is deposited, and a groove for wiring formation is formed on the SiO ₂ film 52 by the well-known photolithography technique and RIE method.
After that, aluminum (Al) ions 53 are implanted into the entire surface, and the surface of the SiO ₂ film 52 is converted into an alumina film 54.

Next, as shown in FIG. 6B, a silicon nitride film 55 is deposited on the entire surface, and the entire surface is anisotropically etched by the RIE method. As a result, as shown in FIG. 6C, the silicon nitride film 55a is formed only on the side wall of the groove.

Next, as shown in FIG. 7D, a copper film 56 is deposited on the entire surface by the CVD method to completely fill the groove, and as shown in FIG. 7E, by the CMP method. The copper film 56 on the upper surface is removed to form the lower electrode wiring layer 57.

After that, as shown in FIG. 7F, niobium (Nb) ions 58 are implanted into the entire surface of the substrate to form a diffusion barrier layer 58a on the surface of the copper wiring. Subsequently, FIG.
As shown in (g), a SiO ₂ film 59, a silicon nitride film 60, a SiO ₂ film 61, and a silicon nitride film 62 are sequentially deposited. As shown in FIG. 7 (h), these multilayer films have
By photolithography and RIE, the groove wiring region 63 in the upper layer and the contact hole 64 with the lower layer are formed.

Next, as shown in FIG. 8I, after the alumina film 65 is deposited on the entire surface by the CVD method, the process shown in FIG.
As shown in (j), the entire surface is anisotropically etched by the RIE method to form the groove wiring region 63 and the contact hole 6.
The alumina film 65a is left only on the side wall portion of No. 4.

Thereafter, as in FIGS. 7D and 7E, C
A copper film is deposited on the entire surface of the substrate by the VD method, as shown in FIG.
As shown in FIG. 7, the upper copper film is removed by the CMP method to form the upper electrode wiring layer 66 and the buried connection port 67.

As described above, according to the second embodiment, in addition to the effects of the first embodiment, the number of diffusion barrier layers can be reduced. Next, a semiconductor device according to the third embodiment of the present invention will be described.

FIG. 9 is a sectional view showing the structure of this semiconductor device. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here. That is, the device of the present embodiment is a modification of the first embodiment, but unlike the first and second embodiments, after the diffusion barrier layer 30 that is substantially vertical to the substrate 21 is formed. A diffusion barrier layer 29 in a region substantially parallel to the substrate 21 is formed by ion implantation, so that a diffusion wiring layer 29, 30 is provided only around the lower and upper wiring electrode layers 22, 26 to form a buried wiring structure. ing.

Next, a method of manufacturing such a semiconductor device will be described with reference to process sectional views of FIGS. In the following description, the amorphous TaSiN film corresponds to a diffusion barrier layer which is substantially parallel to and perpendicular to the substrate with respect to the lower electrode wiring layer, and substantially perpendicular to the substrate with respect to the contact hole and the upper electrode wiring layer. Corresponding to a proper diffusion barrier layer. The niobium ion implantation layer and the alumina region correspond to the diffusion barrier layer substantially parallel to the substrate.

[0055] Now, as shown in FIG. 10 (a), SiO ₂ film 72 is deposited on the semiconductor substrate 71 formed of a transistor structure, by a known photo Sawakoku technique and RIE method, SiO ₂ film 72 on A groove 73 for forming a wiring is formed in the. Thereafter, as shown in FIG. 10B, the amorphous TaSiN film 74 is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 10C, CVD
Method, a copper film 75 is deposited on the entire surface to completely fill the groove, and as shown in FIG. 11D, the copper film on the upper surface is removed by CMP to form the lower electrode wiring layer 76. It is formed.

Thereafter, as shown in FIG. 11E, Nb ions 77 are implanted into the entire surface of the substrate to form a diffusion barrier layer 77a on the surface of the lower electrode wiring layer 76. continue,
As shown in FIG. 11F, a SiO ₂ film 78 is deposited.

Here, as shown in FIG. 11G, a groove wiring region 79 in the upper layer and a contact hole 80 with the lower layer are formed by photolithography and RIE. Next, FIG.
2 (h), the amorphous TaSiN film 81 is deposited on the entire surface of the substrate by the CVD method, and then the entire surface is anisotropically etched by the RIE method as shown in FIG. 12 (i). The amorphous TaSiN film 81a is left only on the sidewall portions of the trench wiring region 79 and the contact hole 80.

Thereafter, as shown in FIG. 12 (j), Al ions 82 are implanted into the entire surface of the substrate to form an alumina region 82a on the surface substantially parallel to the substrate 71. The alumina region 82a has the same copper diffusion barrier property as the amorphous TaSiN film 81a. Further, since aluminum injected into the lower electrode wiring layer 76 made of copper forms a solid solution in copper, unlike the conventional case, the resistance at the contact portion does not increase.

Subsequently, as shown in FIG. 13 (k), CV
A copper film 83 is deposited on the entire surface by the D method, as shown in FIG.
As shown in, the upper copper film 83 and the alumina region 82a are removed by the CMP method to form the upper electrode wiring layer 84.

As described above, according to the third embodiment, in addition to the effects of the first embodiment, the interlayer insulating film 72,
Each of the electrode wiring layers 76, 84 does not include a diffusion barrier layer in 78.
Diffusion barrier layers 74, 77a, 81a, 82a only around the
Since it can be formed, it can be implemented more easily and reliably.

In the first to third embodiments described above, the case where copper is used as the conductive material forming the electrode wiring layer has been described, but the present invention is not limited to this. Even if a low resistance metal such as gold or silver is used as the material, the same effects can be obtained by carrying out the present invention in the same manner.

The diffusion barrier layer surrounding each electrode wiring layer is
As long as it is a material having sufficient diffusion barrier property with respect to the conductive material of the electrode wiring layer, regardless of whether it has conductivity or not, even if the material is changed appropriately and used The effect of can be obtained. As a diffusion barrier layer having a sufficient diffusion barrier property, for example, an amorphous metal compound is used, which includes a refractory metal such as TaSiC or TiSiN and Si.
And using a compound film with nitrogen, oxygen, or carbon,
Similarly, it has been confirmed that the effects of the present invention can be obtained.

Further, the diffusion barrier layer has a sufficient diffusion barrier property, and in the combination of the material of the layer substantially perpendicular to the substrate and the layer substantially parallel to the substrate, a combination which can sufficiently secure the etching selection ratio at the time of RIE. If so, the present invention is effective, and at least a combination having a selection ratio of 2 or more is effective. Other,
The present invention can be implemented with various modifications without departing from the scope of the invention.

[0065]

As described above, according to the invention of claim 1, as the electrode wiring layers, the side wall portions substantially vertical to the substrate and the side wall portions substantially parallel to the substrate are made of different diffusion barrier layers. Since, for example, anisotropic etching is used, a buried wiring structure made of a wiring material having a low resistance can be formed without increasing the contact resistance, and thus a semiconductor device capable of realizing high-speed operation can be provided.

According to the second aspect of the present invention, the inside of the contact hole is filled with the same conductive material as that of the electrode wiring layer, and diffused at the interface between the buried conductive material and the electrode wiring layer. Since there is no barrier layer, the conductive material and the lower electrode wiring layer are directly connected to each other, so that the resistance can be reduced, and a semiconductor device having the same effect as that of claim 1 can be provided.

Further, according to the invention of claim 3, in the diffusion barrier layer, one or both of the layer substantially perpendicular to the substrate and the layer substantially parallel to the substrate are formed of an amorphous conductor. Therefore, in addition to the same effect as that of claim 1, the amorphous conductor can be used as the electrode wiring while preventing the diffusion of the conductive material into the insulating film, so that the resistance can be further reduced. A semiconductor device can be provided.

According to the invention of claim 4, the step of forming the interlayer insulating film including the first diffusion barrier layer on the lower electrode wiring layer and the groove for embedding the upper electrode wiring layer. Forming in the interlayer insulating film so as to expose the first diffusion barrier layer, and forming a contact hole in the interlayer insulating film for connecting the formed groove and the lower electrode wiring layer. Depositing a second diffusion barrier layer on the entire surface of the substrate, and anisotropically etching the second diffusion barrier layer,
Since the step of leaving the second diffusion barrier layer only on the sidewalls of the groove and the contact hole, respectively, and the step of burying the upper electrode wiring layer in the groove and the contact hole are included, the same as in claim 1. In addition to the effects, it is possible to provide a method for manufacturing a semiconductor device that can be implemented easily and reliably.

Further, according to the invention of claim 5, a step of forming an interlayer insulating film on the lower electrode wiring layer, and a step of forming a groove for embedding the upper electrode wiring layer in the interlayer insulating film. A step of forming a contact hole in the interlayer insulating film for connecting the formed groove and the upper electrode wiring layer, a step of depositing a first diffusion barrier layer on the entire surface of the substrate, Anisotropically etch the diffusion barrier layer to form a first
Remaining diffusion barrier layer only on the sidewalls of the groove and the contact hole, a step of selectively forming a second diffusion barrier layer on the upper part of the interlayer insulating film and the bottom of the groove, and an upper electrode wiring layer. Since it includes the step of burying in the trench and the contact hole, in addition to the same function as in claim 1, the interlayer insulating film does not include a diffusion barrier layer and diffuses only around each electrode wiring layer. Since the barrier layer can be formed, it is possible to provide a method for manufacturing a semiconductor device that can be implemented more easily and reliably.

Further, according to the invention of claim 6, since the first and second diffusion barrier layers are formed of different materials, a semiconductor device having the same effect as that of claim 4 or claim 5. A manufacturing method can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention,

FIG. 2 is a process sectional view schematically showing the method of manufacturing the semiconductor device according to the embodiment.

FIG. 3 is a process cross-sectional view schematically showing the method for manufacturing a semiconductor device according to the same embodiment,

FIG. 4 is a process sectional view schematically showing the method of manufacturing the semiconductor device according to the embodiment.

FIG. 5 is a sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention,

FIG. 6 is a process sectional view schematically showing the method of manufacturing the semiconductor device according to the embodiment;

FIG. 7 is a process sectional view schematically showing the method of manufacturing the semiconductor device according to the embodiment;

FIG. 8 is a process sectional view schematically showing the manufacturing method of the semiconductor device in the embodiment;

FIG. 9 is a sectional view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention,

FIG. 10 is a process sectional view schematically showing the manufacturing method of the semiconductor device in the embodiment;

FIG. 11 is a process sectional view schematically showing the manufacturing method of the semiconductor device in the embodiment;

FIG. 12 is a process sectional view schematically showing the method of manufacturing the semiconductor device according to the embodiment;

FIG. 13 is a process sectional view schematically showing the manufacturing method of the semiconductor device in the embodiment;

FIG. 14 is a process sectional view schematically showing a conventional method for manufacturing a semiconductor device,

FIG. 15 is a process cross-sectional view schematically showing a conventional method for manufacturing a semiconductor device,

FIG. 16 is a process cross-sectional view schematically showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

21, 31, 51, 71 ... Semiconductor substrate, 22, 38, 5
7, 76 ... Lower electrode wiring layer, 23, 25, 27 ... Interlayer insulating layer, 24, 46, 64, 80 ... Contact hole,
26, 47, 66, 84 ... Upper electrode wiring layer, 28 ... Conductive material, 29, 29a, 30, 58a, 77a ... Diffusion barrier layer, 32, 34, 40, 42, 52, 59, 61,
72, 78 ... SiO ₂ film, 33, 35, 39, 41, 4
3, 55, 55a, 60, 62 ... Silicon nitride film, 3
6, 45, 73 ... Grooves, 37, 37a, 44, 44a ... W
SiN film, 53, 82 ... Aluminum ion, 54, 6
5a ... Alumina film, 56, 75, 83 ... Copper film, 58, 7
7 ... Niobium ion, 63, 79 ... Groove wiring region, 67 ... Buried connection port, 74, 81, 81a ... Amorphous TaSiN
Membrane, 82a ... Alumina region.

Claims (6)

[Claims] 1. A semiconductor device having a structure in which a plurality of electrode wiring layers are formed on a semiconductor substrate and corresponding electrode wiring layers are connected to each other through contact holes, wherein each electrode wiring layer is a substrate. A side surface portion substantially vertical to the side surface and a side surface portion substantially parallel to the substrate are in contact with diffusion barrier layers made of different materials. 2. The semiconductor device according to claim 1, wherein the inside of the contact hole is filled with a conductive material of the same kind as that of the electrode wiring layer, and the filled conductive material and the electrode wiring layer. The semiconductor device, wherein the diffusion barrier layer does not exist at the interface of the semiconductor device. 3. The semiconductor device according to claim 1, wherein one or both of a layer substantially perpendicular to the substrate and a layer substantially parallel to the substrate are amorphous conductors in the diffusion barrier layer. A semiconductor device formed by. 4. A method of manufacturing a semiconductor device having a structure in which at least upper and lower electrode wiring layers are formed on a semiconductor substrate and corresponding electrode wiring layers are connected via contact holes, the first diffusion Forming an interlayer insulating film including a barrier layer on the lower electrode wiring layer; and forming a groove for embedding the upper electrode wiring layer so as to expose the first diffusion barrier layer. A step of forming a film, a step of forming a contact hole for connecting the formed groove and the lower electrode wiring layer in the interlayer insulating film, and a second diffusion barrier layer over the entire surface of the substrate. Depositing, anisotropically etching the second diffusion barrier layer, and leaving the second diffusion barrier layer only on the sidewalls of the groove and the contact hole, respectively, the upper electrode wiring And a step of burying a layer in the trench and the contact hole. 5. A method of manufacturing a semiconductor device having a structure in which at least upper and lower electrode wiring layers are formed on a semiconductor substrate, and the corresponding electrode wiring layers are connected through contact holes, wherein the lower electrode layer is formed. A step of forming an interlayer insulating film on the wiring layer; a step of forming a groove for embedding and forming the upper electrode wiring layer in the interlayer insulating film; the groove formed and the electrode wiring layer of the upper layer; Forming a contact hole for connecting to the interlayer insulating film, depositing a first diffusion barrier layer on the entire surface of the substrate, and anisotropically etching the first diffusion barrier layer, Leaving the first diffusion barrier layer only on the sidewalls of the trench and the contact hole, and selectively forming a second diffusion barrier layer on the top of the interlayer insulating film and the bottom of the trench. And a step of burying and forming the upper electrode wiring layer in the groove and the contact hole. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the first and second diffusion barrier layers are made of different materials. Production method.