JP3463961B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a means for relaxing thermally induced stress in a wiring layer.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, interconnection wiring plays an extremely important role. At present, aluminum or aluminum alloy is mainly used as a main material for interconnection wiring of semiconductor integrated circuit devices.
In the future, it is expected that the current aluminum interconnection wiring technology or technology using copper-based interconnection wiring will be used.

With the demand for higher integration in a semiconductor integrated circuit device, when more semiconductor elements are integrated in a limited area, the interconnection wiring structure becomes more complicated, the wiring density increases, and the wiring layer The number tends to increase and the wiring width tends to narrow.

Thus, semiconductor integrated circuit devices, especially
In highly integrated semiconductor integrated circuit devices with reduced work size
Is the stress induced in the interconnect wiring during the manufacturing process.
It often causes extremely serious deterioration of the wiring structure. Mutual
Connection wiring structure is usually SiO ₂And Si₃N_FourLike
Embedded in the edging material. This structure is
It facilitates the manufacture of
Various undesirable metal surfaces that occur when metal surfaces are exposed
Reduce the effect of the surface.

However, the coefficient of thermal expansion of this insulator is usually very different from the coefficient of thermal expansion of the metal used for the interconnection wiring. For example, the coefficient of thermal expansion of Al is 23 ×
10 ^-6 / ° C, whereas plasma TEOS SiO
The expansion coefficient of the _two films is 0.55 × 10 ^-6 / ° C.

In the semiconductor device manufacturing process, temperature cycles between normal temperature and high temperature are repeated. In such a temperature cycle, a large stress is generated due to the difference in thermal expansion coefficient. For example, when the wiring layer is formed at a high temperature and then cooled to room temperature, stress is generated due to the difference in thermal expansion coefficient. Such stress is generated not only during the deposition of the wiring layer but also during the formation of an insulating film such as a passivation film, etc. during the temperature lowering process.

The stress generated between the interconnection wiring and the insulating region is caused by stress migration or void formation in the interconnection metal interconnection, void formation under the conductive plug for connecting interconnections of different interconnection layers, semiconductor device use. This may cause electromigration or the like promoted by the stress at the time. Moreover, the stress in the insulating region also causes an unpredictable crack. Cracks in the insulating region can also cross the interconnect wiring.

Stress migration in interconnect wiring can be reduced by forming large bamboo grain structures. Further, in the wiring structure using aluminum, for example, TiN / Al /
A laminated structure of TiN is generally used. When aluminum is sandwiched by a layer of TiN, stress causes Al
Even when a void is induced in the wiring, T above and below the Al layer
A conductive path is secured by the iN layer. In addition, the TiN layer increases the adhesive force between the aluminum wiring and the insulating region.

Further, a W plug is formed in the contact hole (via hole) in order to flatten the surface of the insulating layer when the wiring layer is formed. However, W is SiO
_{It has} a very weak adhesive force to the insulation film such as ₂ .
Here, if a TiN layer is formed on the surface of the W plug, the adhesive force of the W plug can be significantly increased. The TiN layer also helps enhance adhesion between the W and Al layers. Al
If a TiN layer is interposed between the layer and the W plug, TiN
The adhesion between the Al layer and the W plug is increased compared to the absence of the layer.

Further, the stress in the insulating region can be reduced by optimizing the thickness of the insulating layer to be thin.
When Cu is minutely mixed with Al, diffusion of Al atoms in the Al wiring layer can be reduced, and generation of voids induced by stress can be reduced.

[0011]

The technique explained above is
It is possible to reduce the influence of stress on the interconnection wiring, but it is not sufficient yet. Even if a large grain is formed in a wiring layer of an Al alloy mixed with copper, a void may occur due to stress migration if the stress is large. Greater stresses may occur as interconnect wiring structures become more complex, including multiple layers of wiring, and more complex in thermal cycling.

TiN as a glue metal layer above and below the Al wiring
Providing layers and providing additional conductive paths on either side of the Al conductive path does not solve all problems. This is because if a void occurs in the Al wiring that is the main wiring layer, the electrical resistance of the wiring will increase.

Further, if the stress is strong, a void may occur under the conductive plug of the via hole. Such voids cause an increase in contact resistance. Even if the stress is reduced by optimizing the thickness of the insulating layer (making it the minimum thickness), it may not be practical in the multilayer wiring structure. Moreover, even if these measures are taken, the cracks in the insulating layer cannot be solved. If a crack occurs in the insulating layer, the crack may also cut the interconnect wiring.

FIG. 6A shows an example of a multilayer wiring structure. A lower wiring layer of a TiN layer 57, an Al (Al alloy) layer 58, and a TiN layer 59 is formed on the upper surface of the insulating layer 54, and is covered with an interlayer insulating film 64. A via hole is formed in the interlayer insulating film 64, and the W plug 6 filling the via hole
6 is formed.

A TiN layer 6 is formed on the surface of the interlayer insulating film 64.
7, Al layer 68, and TiN layer 69 are stacked to form an upper wiring layer. The upper layer wiring on both sides is electrically connected to the lower layer wiring via the W plug 66. The surface of the upper wiring layer is covered with the upper interlayer insulating film 74.

In such a multi-layer wiring structure, when the thermally induced stress increases, the stress concentrates on the weak places in the multi-layer wiring, causing voids in the interconnection wiring and in the insulating region. Cracks occur.

FIG. 6B shows an example of such voids and cracks. W on the left side that connects the lower layer wiring and the upper layer wiring
A void 80a is generated on the bottom surface of the plug. Further, a slit type void 80b is generated in the Al layer 58 of the lower wiring. Further, cracks 82 occur in the interlayer insulating film 64.

FIG. 7 is a transmission electron microscope (TEM) photograph showing voids and cracks generated in an actual sample. This multilayer wiring structure has a structure in which W / TiN is formed on the lower layer wiring of W.
/ Al / TiN type multilevel structure is used. The insulating region is made of SiO ₂ . The grain size in the Al wiring layer is sufficiently large, and Cu is added to the Al wiring layer. Two Al wiring layers are shown in the photograph,
Slit-type voids are generated in the right wiring of the lower Al wiring layer, and two voids are generated on the lower surface of the W plug on the right side thereof. Also, cracks are generated in the leftmost interlayer insulating film.

An object of the present invention is to provide a semiconductor device in which the influence of stress due to the difference in thermal expansion coefficient between the wiring and the insulating region in which the wiring is embedded is reduced. Another object of the present invention is to provide a semiconductor device having a structure capable of relaxing the generated stress.

[0020]

The semiconductor device of the present invention comprises:
A semiconductor substrate having a semiconductor element formed thereon, a glue metal layer formed on the semiconductor substrate and provided on an upper surface thereof, a first interconnection wiring region used for interconnection wiring of a circuit, and a glue metal layer not provided on an upper surface; It has a first wiring layer including a first dummy region that is not used as a component of the circuit, and a first insulating layer that covers the first wiring layer.

It is preferable that the first interconnection wiring region and the first dummy region exist on the same level from the surface of the semiconductor substrate. It is preferable that the first dummy region and the first interconnect wiring region are made of the same material. Further, as a component of the circuit, a second interconnect wiring region formed above the first wiring layer and having a glue metal layer on the upper surface and used for interconnect wiring of the circuit and a glue metal layer on the upper surface are not provided. A second wiring layer including a second dummy region that is not used and a second insulating layer that covers the second wiring layer may be included.

Further, a conductive plug is provided between the first interconnection wiring region of the first wiring layer and the second interconnection wiring region of the second wiring layer to electrically connect the two. Good.

In the above structure, the glue metal layer is made of TiN, and the interconnection wiring region is made of Al or Al.
The dummy region may be formed of Al, Al alloy, W, Cu or Cu alloy.

In the above structure, the dummy region is arranged within a distance of 3D from the interconnection wiring region in the same wiring layer, where D = (H + W) / 2, where H is the height of the interconnection wiring region, W may be the width of the interconnect wiring region.

In the case of having a second wiring layer, the second interconnection wiring region of the second wiring layer may be provided with a glue metal layer also on the lower surface. In the above structure, the first
The first interconnect wiring region of the wiring layer may also include a glue metal layer on the lower surface.

[0026]

In the structure, the glue metal layer is provided in the first interconnection wiring region used for the interconnection wiring of the circuit, and the glue metal layer is not provided in the first dummy region which is not used as a component of the circuit. Selectively form weaker areas. When the stress is accumulated in the wiring structure, the stress is preferentially released at the interface of the dummy region where the strength is weak. Even if a void or a crack is generated in the vicinity of the dummy area, the dummy area is not used as a constituent element of the circuit and therefore does not have a bad influence.

If the first interconnection wiring region and the first dummy region are present at the same level from the surface of the semiconductor substrate, it is suitable to form these regions in the same process. Such a structure can be created without any additional manufacturing process.

Even when the second wiring layer is formed on the first wiring layer, by providing the second interconnection wiring region and the second dummy region in the second wiring layer, the structurally weak portion is formed. Can be selectively formed. The stress is preferentially released at the interface of the dummy area where the strength is weak.

By connecting the first interconnection wiring region and the second interconnection wiring region with a conductive plug, a semiconductor device having excellent flatness can be obtained. If the glue metal layer is made of TiN, good adhesion can be obtained. Good conductivity can be obtained by forming the interconnection wiring region with Al, Al alloy, Cu or Cu alloy. Dummy area is Al, Al
When formed of an alloy, W, Cu, or a Cu alloy, a dummy region having a weak adhesive force with respect to the insulating layer can be obtained.

Setting the distance between the dummy area and the adjacent interconnect wiring area within 3D is effective for stress relief. By providing the glue metal layer also on the lower surface of the second interconnect wiring area, the adhesive force on the lower surface of the second interconnect wiring area can be increased.

Similarly, by providing a glue metal layer also on the lower surface of the first interconnect wiring area, the adhesive force on the lower surface of the first interconnect wiring area can be increased.

[0032]

1 is a schematic diagram showing the cross-sectional structure of a semiconductor device according to an embodiment of the present invention. The lower insulating layer 2 is formed on the surface of the Si substrate 1. A first wiring layer having a laminated structure of a glue metal layer 3a, a main wiring layer 4a, and a glue metal layer 5a is formed on the surface of the lower insulating layer 2.

The first wiring layer has three wiring regions W1 in the figure.
A dummy wiring region D1 including a, W1b, and W1c and having the upper glue metal layer 5a removed between adjacent wiring regions.
a, D1b, D1c, and D1d are arranged. The dummy wiring region D1 is composed of the main wiring layer 4a and the glue metal layer 3a, and is arranged within a distance of 3D from the wiring region W1 which is a constituent element of the circuit. Where D = (H + W) / 2
Where H is the height of the interconnection wiring W1, and W is the width of the interconnection wiring W1.

The dummy area D1 has its effect if it is arranged in the vicinity of the wiring area W1, and does not necessarily have to be arranged within the distance 3D. However, the effect is high when arranged at a distance within 3D. The shape of the dummy region is not particularly limited, but it is preferable to form the dummy region with a large number of cubic structures. This is effective in widening the surface of the dummy area where the adhesive strength is weak.
However, the dummy region may have another shape. Further, these dummy regions can be arranged so as to be useful for flattening the surface of the interlayer insulating film to be formed later.

The lower wiring layer is covered with the first interlayer insulating film 8a. A via hole is provided in the first interlayer insulating film 8a, and a W plug 12 is formed in the via hole. The surface of the W plug 12 is substantially flush with the surface of the lower wiring layer 8a.

A second wiring layer having a laminated structure of a glue metal layer 3b, a main wiring layer 4b and a glue metal layer 5b is formed on the surface of the first interlayer insulating film 8a, and the surface thereof is further formed by the interlayer insulating film 8b. Is covered. The second wiring layer includes four wiring regions W2a, W2b, W2c, W2d in the drawing, and dummy regions D2a, ... D2f similar to the first wiring layer are formed between adjacent wiring regions. In the dummy area, the glue metal layer 5b on the upper surface is removed.

In the above structure, the glue metal layer is made of, for example, TiN, and the main wiring layer 4 is made of, for example, Al.
It is formed of Al alloy, Cu, Cu alloy, or the like. Al and Cu
The main wiring layer whose main component is S is used as an interlayer insulating film.
Weak adhesion to iO ₂ and Si ₃ N ₄ .

Since the glue metal layer of TiN is provided on the lower surface and the upper surface of the main wiring layer used as the interconnection wiring, the adhesive force between the main wiring layer and the insulating region is enhanced. On the other hand, in the glue region, since the glue metal layer on the upper surface is removed, a portion having weak adhesion to the insulating region and weak strength is selectively formed to form the insulating region 8 and the dummy region D. Voids are easily generated at the interface.

The present inventors experimentally confirmed that when a void or a crack is generated, other voids or cracks are extremely unlikely to occur in the vicinity thereof. When a void is generated in the dummy area, the main wiring layer will not generate a void in the vicinity thereof. If the distance between the dummy area and the wiring area is within 3D, this void prevention effect is high.

In the structure of FIG. 1, the dummy region for stress relaxation is formed of the same material as the wiring region. Therefore, the number of steps for forming the dummy region is small. Although the glue metal layer exists on the lower surface of the main wiring layer, the glue metal layer on the upper surface is removed, so that the portion where the strength is weakened can be selectively formed.

2A to 2E show a manufacturing process of a wiring structure having a wiring region and a dummy region as shown in FIG. In FIG. 2A, a lower insulating layer 2 is formed on the surface of a Si substrate 1, and a TiN layer 3 and Al are formed on the lower insulating layer 2.
A layered structure of layer 4 and TiN layer 5 is deposited. These deposition steps can be performed by, for example, sputtering (including reactive sputtering). The Si substrate 1 is not shown in the following figures.

As shown in FIG. 2B, the wiring layers 3, 4,
After forming 5, the photoresist layer 6 is applied on the surface, and an opening is formed at a place where a dummy region is to be formed. This step can be performed by a normal photolithography step. Using the resist pattern 6 thus formed as an etching mask, the upper TiN layer 5 is etched. This etching can be performed by a dry process or a wet process. Upper TiN layer 5
After patterning, the resist pattern 6 is removed by ashing or the like. Then, a new resist film is applied.

As shown in FIG. 2C, a new resist film is exposed and developed to form a resist pattern 7 for patterning the wiring layer and the dummy region. Figure 2
As shown in (D), the TiN layer 5, the Al layer 4, and the TiN layer 3 underneath are etched using the resist pattern 7 as an etching mask. This etching is preferably performed by a dry process. However, a wet process may be used. After etching the TiN layer 5, the Al layer 4, and the TiN layer 3, the resist pattern 7 is removed.

As shown in FIG. 2 (E), the wiring layer including the dummy region and the wiring region thus formed is formed of SiO 2.
Cover with insulating layer 8 such as ₂ . The insulating layer 8 can be formed by a method such as CVD, plasma-enhanced CVD, or SOG spin coating.

By the steps as shown in FIG. 2, the first wiring layer and the second wiring layer having the dummy area and the wiring area shown in FIG. 1 can be formed. The W plug is WF ₆
Can be formed by depositing a blanket W layer by CVD using a reduction reaction, and then performing etchback or the like. W selective growth may be used.

How the structure shown in FIG. 1 helps prevent the generation of harmful voids in the wiring structure will be described below. FIG. 3A is a diagram in which the central portion of the multilayer wiring structure of FIG. 1 is extracted. Dummy areas D1b and D1c are formed close to both sides of the wiring area W1b of the first wiring layer, and dummy areas D2c and D2d are formed in the area between the wiring areas W2b and W2c of the second wiring layer. There is. Ti is formed on the upper surfaces of the dummy regions D1a, D1b, D2c, and 2d.
N layers 5a and 5b are not formed.

When a thermal cycle is applied to such a structure, a large stress is generated between the insulating regions 2 and 8 and the wiring layer. In FIG. 3B, the accumulated stress becomes large,
A state where a void is generated in the multilayer wiring structure is shown. When the stress generated between the insulating region and the wiring layer becomes larger than a certain level, the void V is likely to occur.

At this time, since the TiN layers 5a and 5b are formed on the upper surfaces of the wiring layers W1b, W2b and W2c,
Strong adhesion and voids are relatively unlikely to occur. On the other hand, since there is no TiN layer on the upper surfaces of the dummy regions D1b, D1c, D2c, D2d, the adhesive strength is weak.

When the stress is high, voids V are preferentially generated near the interface where the adhesive strength is weak. Dummy areas D1b and D1
When the void V is generated in c, D2c, and D2d, the stress between the insulating region and the wiring layer around the void V is released by the void, and further voids are less likely to occur. When the stress is released, the stress-induced various adverse phenomena mentioned above will be prevented.

As described above, by preferentially generating voids or cracks at locations unrelated to the circuit elements of the semiconductor integrated circuit device, the multilayer wiring structure itself is prevented from harmful voids or cracks, and the reliability of the multilayer wiring structure is improved. You can improve your sex.

Although the two-layer wiring structure in the semiconductor integrated circuit device is illustrated in FIG. 1, the wiring structure is not limited to the two-layer wiring. FIG. 4 schematically shows the configuration of another semiconductor integrated circuit device to which the embodiment of the present invention can be applied. A field oxide film 14 is selectively formed on the surface of the Si substrate 1. Transistors Tr1 and Tr2 are formed in the active region defined by the field oxide film 14.

Each transistor Tr has a gate oxide film 1
5. It has an insulated gate electrode formed of a polycrystalline Si (or polycide) gate electrode 16. Sidewall oxide regions 17 are formed on the sidewalls of the gate electrode, and source / drain regions 18 having an LDD structure are formed on both sides of the gate electrode. A silicide electrode 19 is formed on the surface of these source / drain regions.

The surfaces of these transistors Tr1 and Tr2 are covered with an insulating layer 21 such as SiO ₂ .
A contact hole is formed in the insulating layer 21, a first wiring layer formed of a laminated structure of a barrier metal layer 22 and a main wiring layer 23 is formed, and is electrically connected to the source / drain electrode 19.

The barrier metal layer 22 is made of, for example, Ti / Ti.
It is formed with an N laminated structure. The wiring layer 23 is, for example, A
It is formed of 1, W, silicide or the like. A first interlayer insulating film 24 such as SiO ₂ is formed so as to cover the surface of the first wiring layer,
The contact hole (via hole) is the first interlayer insulating film 24.
Is provided to penetrate. A conductive plug including a glue metal layer 25 and a W layer 26 is formed in the contact hole. The glue metal layer is, for example, a TiN layer.

A second wiring layer is formed on the surface of the first interlayer insulating film 24. The second wiring layer, like the first wiring layer, includes the lower glue metal layer 27, the main wiring layer 28, and the upper glue metal layer 2.
9 is formed. The above-mentioned dummy area is arbitrarily arranged near the second wiring layer. The surface of the second wiring layer is S
It is covered with a second interlayer insulating film 34 such as iO ₂ .

A contact hole is formed in the second interlayer insulating film 34, and the conductive plug formed by the glue metal layer 35 and the W region 36 fills the contact hole. The lower glue metal layer and the main wiring layer 3 are formed on the surface of the second interlayer insulating film 34.
8. A third wiring layer formed of the upper glue metal layer 39 is formed. The above-mentioned dummy region is also arbitrarily formed around the third wiring layer.

The surface of the third wiring layer is formed on the third interlayer insulating film 44.
Covered by. A contact hole is formed in the third interlayer insulating film, and a conductive plug composed of the glue metal layer 45 and the W region 46 is formed.

In this way, an arbitrary multilayer wiring structure is formed, and a dummy region is provided in the desired wiring layer close to the wiring. The case has been described above in which a part of the material of the wiring layer is commonly used and the dummy region is provided in the vicinity of the wiring region.
In order to further enhance the stress relaxation effect of the dummy area, it is desired that the dummy area does not have a glue metal layer having a strong adhesive force.

FIG. 5 schematically shows a process of manufacturing a wiring layer according to another embodiment of the present invention. FIG. 5 (A) is shown in FIG.
After the upper glue metal layer 5 is patterned according to the resist pattern 6 by the steps (A) and (B), the main wiring layer 4 and the lower glue metal layer 3 are also patterned. After patterning the lower glue metal layer 3, the main wiring layer 4, and the upper glue metal layer 5, the resist pattern 6 is removed.

As shown in FIG. 5B, a blanket W, for example, is formed on the upper surface of the wiring layer pattern thus formed.
The layer is deposited by CVD to form a dummy metal layer 9.
It is desirable that the dummy metal layer 9 completely fills back the holes formed in the wiring layer.

As shown in FIG. 5C, the dummy metal layer 9
By performing etch back from the upper surface, the dummy metal layer 9 deposited on the surface of the wiring layer is removed. In this way, the plug region 9 of the dummy metal layer that fills the hole is formed.

As shown in FIG. 5D, a resist pattern 10 is formed on the flattened surface, and the region exposed in the opening of the resist pattern 10 is removed by etching. The glue metal layers 3 and 5 and the main wiring layer 4 around the dummy metal region 9 are thus removed. After this patterning step, the resist pattern 10 is removed. In addition,
The shape and arrangement of the dummy area 9 are the same as those in the above-described embodiment.

As shown in FIG. 5E, an interlayer insulating film 8 is formed on the surface of the patterned wiring layer by CVD and plasma CV.
D, spin coating, or the like. The dummy region 9, which has a significantly low adhesion to the interlayer insulating film, does not have a glue metal layer at all and directly contacts the insulating region. By forming the dummy region 9 with W or the like having a weak adhesive force between the dummy region 9 and the insulator, a weak portion is positively formed.

Such a dummy area is arbitrarily set in FIG.
It can be applied to the semiconductor device as shown in FIG. When the stress generated between the insulating layer 8 and the wiring layer becomes high, voids and the like preferentially occur at the interface between the dummy region 9 and the insulating regions 8 and 2, and the stress is relaxed.

Although the case of the aluminum wiring layer has been described, the same structure and method can be used for the case of Cu or a wiring layer containing Cu as a main component. By positively arranging a dummy region having a weak adhesive force in the vicinity of the wiring layer, voids can be preferentially generated and the voids in the wiring layer can be prevented.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0067]

As described above, according to the present invention,
By generating voids and the like preferentially in the dummy region, it is possible to prevent harmful voids in the wiring structure.

By relaxing the stress in the dummy region, the reliability of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a sectional structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a main manufacturing process of the wiring structure shown in FIG.

FIG. 3 is a schematic cross-sectional view for explaining a void reduction effect in the structure of FIG.

FIG. 4 is a schematic cross-sectional view showing another configuration example of the semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view schematically showing a manufacturing process of a wiring structure according to another embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view for explaining voids and cracks that occur in a conventional multi-layer wiring structure.

FIG. 7 is an electron micrograph showing a cross section of a thin film of a semiconductor integrated circuit device manufactured by a conventional technique.

[Explanation of symbols]

1 Semiconductor substrate 2 insulating layers 3,5 glue metal layer 4 Main wiring layer 6, 7 Resist layer (resist pattern) 8 Interlayer insulation film 9 W dummy area 12 W plug W1, W2 wiring layer D1, D2 dummy area

Claims (9)

(57) [Claims] 1. A semiconductor substrate on which a semiconductor element is formed, a first interconnect wiring region formed above the semiconductor substrate and provided with a glue metal layer on an upper surface and used for interconnect wiring of a circuit, and a glue metal on the upper surface. A semiconductor device comprising: a first wiring layer that does not include a layer and includes a first dummy region that is not used as a component of a circuit; and a first insulating layer that covers the first wiring layer. 2. The semiconductor device according to claim 1, wherein the first interconnection wiring region and the first dummy region are present at the same level from the surface of the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the first dummy region and the first interconnection wiring region are made of the same material. 4. A second interconnect wiring region formed above the first wiring layer and having a glue metal layer on an upper surface thereof, which is used for interconnect wiring of a circuit, and a glue metal layer not provided on an upper surface, A second wiring layer including a second dummy region that is not used as a component of a circuit, and a second insulating layer that covers the second wiring layer.
4. The semiconductor device according to any one of 3 above. 5. A conductive plug, which is arranged between the first interconnection wiring region of the first wiring layer and the second interconnection wiring region of the second wiring layer and electrically connects the two. The semiconductor device according to claim 4, which has. 6. The glue metal layer is formed of TiN,
The interconnection wiring region is made of Al, Al alloy, Cu or C
u alloy, the dummy region is made of Al, Al alloy,
It is formed of W, Cu or a Cu alloy.
The semiconductor device according to claim 1. 7. The dummy region is arranged within a distance of 3D from the interconnection wiring region in the same wiring layer, where D = (H + W) / 2, where H is the height of the interconnection wiring region, W
7. The semiconductor device according to claim 1, wherein is a width of the interconnection wiring region. 8. The semiconductor device according to claim 4, wherein the second interconnection wiring region of the second wiring layer is also provided with a glue metal layer on the lower surface. 9. The semiconductor device according to claim 1, wherein the first interconnection wiring region of the first wiring layer also has a glue metal layer on the lower surface.