JPH02284447A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02284447A JPH02284447A JP10460489A JP10460489A JPH02284447A JP H02284447 A JPH02284447 A JP H02284447A JP 10460489 A JP10460489 A JP 10460489A JP 10460489 A JP10460489 A JP 10460489A JP H02284447 A JPH02284447 A JP H02284447A
- Authority
- JP
- Japan
- Prior art keywords
- film
- lower layer
- insulating film
- interlayer insulating
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010410 layer Substances 0.000 claims abstract description 76
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 17
- 239000002184 metal Substances 0.000 abstract description 16
- 230000007547 defect Effects 0.000 abstract description 11
- 238000000576 coating method Methods 0.000 abstract description 10
- 239000011248 coating agent Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 230000006835 compression Effects 0.000 abstract 2
- 238000007906 compression Methods 0.000 abstract 2
- 230000006866 deterioration Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101150070475 SIT1 gene Proteins 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置の製造方法に係り、特に多層配線
構造における層間絶縁膜の形成方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an interlayer insulating film in a multilayer wiring structure.
（従来の技術）
従来、多層配線構造における層間絶縁膜としては公知の
ＣＶＤ技術による絶縁膜（ＳｉＯ□膜、 ＰＳＧ膜）を
使用しているが、多層配線での段差形状を考えて眉間絶
縁膜の平坦化が行われており、その結果として層間絶縁
膜構成は複雑になっている。(Conventional technology) Conventionally, an insulating film (SiO□ film, PSG film) made by known CVD technology has been used as an interlayer insulating film in a multilayer wiring structure. As a result, the interlayer insulation film structure has become more complex.
公知の層間絶縁膜平坦化技術として代表的なものは、Ｓ
ＯＧ中塗り法、エッチハックによる平坦化法がある。A typical known interlayer insulating film planarization technique is S
There are OG intermediate coating method and flattening method using etch hack.
第１図はＳＯＧ中塗り法を採用した半導体装置の一例を
示す。この図において、１は半導体基板、２は絶縁膜で
あり、その上に第１層メタル配ｖＡ３を形成した後、層
間絶縁膜の下層膜４を形成する。FIG. 1 shows an example of a semiconductor device employing the SOG intermediate coating method. In this figure, 1 is a semiconductor substrate, 2 is an insulating film, and after forming a first layer metal interconnection layer A3 thereon, a lower layer film 4 of an interlayer insulating film is formed.
その後、下層膜４上に層間絶縁膜の中間層としてＳＯＧ
塗布膜（スピンオンガラス膜）５を形成し、表面を平坦
化する。その後、このＳＯＧ塗布膜５上に層間絶縁膜の
上層膜６を形成した後、その上に第２Ｎメタル配線７を
形成する。After that, SOG is applied as an intermediate layer of the interlayer insulating film on the lower layer film 4.
A coating film (spin-on glass film) 5 is formed and the surface is planarized. Thereafter, an upper film 6 of an interlayer insulating film is formed on this SOG coating film 5, and then a second N metal wiring 7 is formed thereon.
第２図はエッチバックによる平坦化法を採用した半導体
装置の一例を示す。この図において、１１は半導体基板
、１２は絶縁膜であり、その上に第１層メタル配線１３
を形成した後、層間絶縁膜の下層膜１４を形成する。そ
の後、図示していないが、下層膜１４上にレジストを塗
布した上で、そのレジストと下層膜Ｉ４とでエツチング
速度が同一になる条件でレジストがすべて除去されるま
で全面エッチハックを施し、図のように下層膜１４の平
坦化を図る。その後、下層膜１４上に層間絶縁膜の上層
膜１５を形成し、その」二に第２層メタル配線１６を形
成する。FIG. 2 shows an example of a semiconductor device employing a planarization method using etchback. In this figure, 11 is a semiconductor substrate, 12 is an insulating film, and a first layer metal wiring 13 is placed on top of it.
After forming, a lower layer film 14 of an interlayer insulating film is formed. Thereafter, although not shown in the figure, a resist is applied on the lower layer film 14, and the entire surface is etched under conditions such that the resist and the lower layer film I4 are etched at the same rate until all the resist is removed. The lower layer film 14 is planarized as shown in FIG. Thereafter, an upper layer film 15 of an interlayer insulating film is formed on the lower layer film 14, and a second layer metal wiring 16 is formed on top of the upper layer film 15.
以上の説明から明らかなように、ＳＯＧ中塗り法では層
間絶縁膜は３層構造、エッヂハックによる平坦化法では
２層構造となり、いずれの場合にも上層膜と下層膜を有
する。As is clear from the above description, the interlayer insulating film has a three-layer structure in the SOG intermediate coating method, and a two-layer structure in the edge hack planarization method, and in both cases, it has an upper layer film and a lower layer film.
この上層膜と下層膜には、一方がＰＳＧ膜、他方が３４
０□膜というようにＰＳＧ膜とＳｉＯ□膜の組合わせ、
あるいは上層膜と下層膜の両方にＰＳＧ膜または５ｉＯ
ｚ膜のいずれか一方を使用している。The upper layer film and the lower layer film include one PSG film and the other 34
A combination of PSG film and SiO□ film, such as 0□ film,
Or PSG film or 5iO for both the upper layer film and the lower layer film.
Either one of the Z films is used.
（発明が解決しようとする課題）
しかるに、眉間絶縁膜の上層膜と下層膜が上記のような
膜構成の場合には、メタル配線での欠損の発生、眉間絶
縁膜に対するボッＩ・キャリア注入によるトランジスタ
寿命の劣化のどちらか一方が、あるいは両方が同時に起
こるという問題がある。(Problem to be Solved by the Invention) However, if the upper and lower layers of the glabellar insulating film have the above-mentioned film structure, defects may occur in the metal wiring, and defects may occur due to the injection of boron I and carriers into the glabellar insulating film. There is a problem in that either one of the transistor life degradations or both occur simultaneously.
この問題点について従来例を種々実験した結果を下記表
１に示す。The results of various experiments on conventional examples regarding this problem are shown in Table 1 below.
表 １
ここで、ＰＳＧ膜は公知の常圧ＣＶＤ膜であり、Ｐ−３
ｉ０２膜ば公知のプラズマＣＶＤ膜である。膜厚はそれ
ぞれでのトータル膜厚が同一になるように設定しており
、表１では約８０００人である。メタル配線は第１層、
第２層ともにＡｌ−５ｉ配線（５０００人）である。ト
ランジスタの寿命ばＶｄ＝８Ｖ、Ｖ。Table 1 Here, the PSG film is a known normal pressure CVD film, and P-3
The i02 film is a known plasma CVD film. The film thickness is set so that the total film thickness in each case is the same, and in Table 1, it is about 8,000 people. The metal wiring is the first layer,
Both of the second layers are made of Al-5i wiring (5000 wires). The life of the transistor is Vd=8V, V.
＝４ｖでのｇｍの１０％劣化で求めている。メタル配線
の欠損は、×印が配線の１７３以上の欠損を示し、Δ印
が１７３未満の欠損を示している。= 10% deterioration of gm at 4v. Regarding defects in the metal wiring, an x mark indicates a defect of 173 or more in the wiring, and a Δ mark indicates a defect of less than 173.
この表１から分ることは、第１Ｎメタル配線の欠損は下
層膜がＰＳＧ膜であれば発生しないし、第２層メタル配
線の欠損は上層膜がＰ −５ｉＯ□膜であれば発生しな
いし、トランジスタ寿命の劣化は下層膜と上層膜がＰ−
３ｉＯ□膜であれば起こらないということである。しか
るに、従来技術の膜構成では、これらのすべてを満足す
ることはできない。Table 1 shows that defects in the first N metal wiring will not occur if the lower layer film is a PSG film, and defects in the second layer metal wiring will not occur if the upper layer film is a P-5iO□ film. , the deterioration of transistor life occurs when the lower and upper layers are P-
This means that this does not occur if the film is 3iO□. However, the membrane structure of the prior art cannot satisfy all of these requirements.
この発明は上記の点に鑑みなされたもので、層間絶縁膜
による配線の欠損とトランジスタ寿命の劣化のすべてを
解決できる半導体装置の製造方法を提供することを目的
とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve all of the problems of wiring defects caused by interlayer insulating films and deterioration of transistor life.
（課題を解決するための手段）
この発明は、半導体装置の製造方法、特に多層配線構造
での眉間絶縁膜形成方法において、積層構造層間絶縁膜
の下層膜として引張り応力のプラズマＣＶＤ ５ｉＯｚ
膜を形成し、同絶縁膜の」二層膜として圧縮応力のプラ
ズマＣＶＤ ＳｉＯ□膜を形成するものである。(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device, particularly a method for forming a glabella insulating film in a multilayer wiring structure, in which tensile stress plasma CVD 5iOz is used as a lower layer film of an interlayer insulating film in a laminated structure.
A compressive stress plasma CVD SiO□ film is formed as a two-layer film of the same insulating film.
（作 用）
ＰＳＧ膜は、引張り応力である。この発明において、下
層膜として引張り応力のプラズマＣＶＤ５ｉＯｚ膜を形
成すれば、応力的には下層膜としてＰＳＧ膜を形成した
場合と同等になり、下層配線の欠損を防止できることは
表１から明らかである。(Function) The PSG film has tensile stress. In this invention, it is clear from Table 1 that if a plasma CVD 5iOz film with tensile stress is formed as the lower layer film, the stress will be equivalent to that when a PSG film is formed as the lower layer film, and damage to the lower layer wiring can be prevented. .
一方、上層膜として、通常圧縮応力のプラズマＣＶＤ
５ｉＯｚ膜を形成すれば、」二層配線の欠損を防止でき
ることは表１から明らかである。また、」二層膜と下層
膜の両方をプラズマＣＶＤ ＳｉＯ□膜で形成すれば、
ホットキャリア注入による１−ランジスタ寿命の劣化を
防止できることは表１から明らかである。On the other hand, for the upper layer film, plasma CVD with normal compressive stress is used.
It is clear from Table 1 that defects in the two-layer wiring can be prevented by forming a 5iOz film. In addition, if both the double layer film and the lower layer film are made of plasma CVD SiO□ film,
It is clear from Table 1 that deterioration of the 1-transistor life due to hot carrier injection can be prevented.
なお、プラズマＣＶＤ ＳｉＯ□膜は通常前述のように
圧縮応力であるが、例えばＳ １ｔｌ ４ガスとＮ２０
ガスを用いてプラズマＣＶＤ ５ｉｎ２膜を形成する場
合、−例としてＳ ｉ Ｈａ／Ｎ ｚ Ｏ流量比を変え
ることにより引張り応ノｊとすることができる。すなわ
ち、通常Ｓ ｉ １１ ｔ ／ Ｎ ２０流量比が０１
０６未満で圧縮応力の膜が形成されるが、流量比を０．
０６〜０．２０程度とすることにより引張り応力の膜が
形成される。Note that the plasma CVD SiO
When forming a plasma CVD 5in2 film using a gas, the tensile response can be achieved by changing the SiHa/NzO flow rate ratio, for example. That is, normally the S i 11 t / N 20 flow rate ratio is 01
If the flow rate ratio is less than 0.06, a film with compressive stress will be formed.
A film with tensile stress is formed by setting it to about 0.06 to 0.20.
（実施例）
以下この発明の一実施例を説明する。この発明の一実施
例で製造される半導体装置の構造は第１図と同一である
。そこで、この第１図を再度用いてこの発明の一実施例
を説明することとする。(Example) An example of the present invention will be described below. The structure of a semiconductor device manufactured according to an embodiment of the present invention is the same as that shown in FIG. Therefore, one embodiment of the present invention will be explained using FIG. 1 again.
第１図において、１は半導体基板、２はその表面の絶縁
膜であり、この絶縁膜２上に第１層メタル配線３を形成
した後、層間絶縁膜の下層膜４を形成する。ここで、層
間絶縁膜の下層膜４としては、プラズマＣＶＤ技術を用
いて引張り応力のプラグ７ＣＶＤ ＳｉＯｚ膜（以下Ｐ
−３ｉｎ２膜と記す）を形成する。In FIG. 1, 1 is a semiconductor substrate, 2 is an insulating film on the surface thereof, and after forming a first layer metal wiring 3 on this insulating film 2, a lower layer 4 of an interlayer insulating film is formed. Here, as the lower layer film 4 of the interlayer insulating film, a tensile stress plug 7CVD SiOz film (hereinafter P
-3in2 film) is formed.
通常、プラズマＣＶＤ技術によるＰ −３ｉＯ□膜は圧
縮応力膜である。したがって、ＣＶＤ条件の変更により
引張り応力膜を形成する。例えばＳ ｉ １１４ガスと
Ｎ２０ガスを用いてＰ−８ｉＯ２膜を形成する場合では
、−例として５ｉ１１４／ＮｚＯ流量比を０．０６〜０
．２０程度の範囲で変えることにより、必要な引張り応
力値（例えばＩ Ｘ １０９ｄｙｎ ／ ｃＪ ）のＰ
Ｓ ｉ Ｏｚ膜を形成する。この時、ＣＶＤの他の
条件としては、ＲＦパワー３００Ｗ程度、圧力３００
ｍＴｏｒｒ程度、ＣＶＤ温度温度３御０〜４００
ｐ−５ｉ０２膜の膜厚は、ＳＯＣ中塗り法に適した厚さ
とする。Usually, a P-3iO□ film produced by plasma CVD technology is a compressive stress film. Therefore, a tensile stress film is formed by changing the CVD conditions. For example, when forming a P-8iO2 film using S i 114 gas and N20 gas, - for example, the 5i114/NzO flow rate ratio is set to 0.06 to 0.
．． P of the required tensile stress value (for example, I
A SiOz film is formed. At this time, other conditions for CVD include RF power of about 300W and pressure of about 300W.
About mTorr, CVD temperature 3 degrees, 0 to 400 The thickness of the p-5i02 film is suitable for the SOC intermediate coating method.
このようにして引張り応力のＰ ５ｉＯｚ膜（下層膜
４）を形成したら、次にその上に眉間絶縁膜の中間層と
してＳＯＧ塗布膜５を形成し、表面を平坦とする。その
後、その上に層間絶縁膜の上層膜６を形成する。この上
層膜６としては、通常のプラズマＣＶＤ技術（Ｓｉｔ１
４／ Ｎ２０流量比０．０６未満、他の条件は下層膜４
形成時と同し）により、圧縮応力（応力値は下層膜４と
同じで例えば１×１０９ｄｙｎ／ｃＪ）のプラズマＣＶ
Ｄ ＳｉＯ□膜を形成する。その後、その上に第２層メ
タル配線７を形成する。After the tensile stress P 5iOz film (lower layer film 4) is formed in this manner, an SOG coating film 5 is formed thereon as an intermediate layer of the glabella insulating film to flatten the surface. Thereafter, an upper film 6 of an interlayer insulating film is formed thereon. This upper layer film 6 is formed using the normal plasma CVD technique (Sit1
4/ N20 flow rate ratio less than 0.06, other conditions are lower layer film 4
Plasma CV of compressive stress (stress value is the same as that of the lower layer film 4, for example, 1×109 dyn/cJ) (same as during formation)
D A SiO□ film is formed. Thereafter, second layer metal wiring 7 is formed thereon.
なお、この一実施例は、ＳＯＧ中塗り法で平坦化層間絶
縁膜を形成する場合であるが、第２図のエッチハック法
で層間絶縁膜の平坦化を図る場合にも同様にして下層膜
として引張り応力のプラズマＣＶＤ ５ｉｎ２膜、上層
膜として圧縮応力のプラズマＣＶＤ ５ｉＯｚ膜を形成
することができる。Note that this example deals with forming a flattened interlayer insulating film using the SOG intermediate coating method, but the lower layer insulation film can also be formed in the same way when planarizing the interlayer insulating film using the etch hack method shown in FIG. A tensile stress plasma CVD 5in2 film can be formed as the upper layer, and a compressive stress plasma CVD 5iOz film can be formed as the upper layer film.
（発明の効果）
以上詳細に説明したように、この発明によれば、積層構
造層間絶縁膜の下層膜として引張り応力のプラズマＣＶ
Ｄ ＳｉＯ□膜を形成したので、下層配線の欠損を防止
でき、また上層膜としては圧縮応力のプラズマＣＶＤ
ＳｉＯ□膜を形成したので上層配線の欠損も防止でき、
さらに上層膜と下層膜の両方が５ｉ０２膜であるから、
ポットキャリア注入による１−ランジスタ寿命の劣化を
防くことができる。このように、この発明は、配線とト
ランジスタの信頼性を格段に向上させることができる。(Effects of the Invention) As described above in detail, according to the present invention, a tensile stress plasma CV
D Since the SiO□ film is formed, damage to the lower layer wiring can be prevented, and the upper layer film can be formed using compressive stress plasma CVD.
Since the SiO□ film is formed, damage to the upper layer wiring can be prevented.
Furthermore, since both the upper layer film and the lower layer film are 5i02 films,
Deterioration of the 1-transistor life due to pot carrier injection can be prevented. In this way, the present invention can significantly improve the reliability of wiring and transistors.
第１図はＳＯＧ中塗り法による層間絶縁膜平坦化技術を
採用した半導体装置を示す断面図、第２図はエッチハッ
クによる平坦化技術を採用した半導体装置を示す断面図
である。
１、１１・・・半導体基板、３．１３・・・第１層メタ
ル配線、４，１４・・・下層膜、６．１５・・・上層膜
、７、１６・・・第２層メタル配線。
４稗蟇析５
７ ： 第２ 層メづｌ）し■口１会魯しＳＯＧ中Ｗ
１，１ ＋ｐ化＋−ｓｂ＊＃第
図
１１：手１１本基本反
エツナバッフ干担イヒ〉天）二λ◇衰面第２図FIG. 1 is a cross-sectional view showing a semiconductor device employing an interlayer insulating film planarization technique using the SOG intermediate coating method, and FIG. 2 is a cross-sectional view showing a semiconductor device employing a planarization technique using etch hacking. 1, 11... Semiconductor substrate, 3.13... First layer metal wiring, 4, 14... Lower layer film, 6.15... Upper layer film, 7, 16... Second layer metal wiring . 4th grade analysis 5 7: 2nd layer mezl) and ■mouth 1 meeting and SOG middle W
1,1 + p conversion + - sb * # Figure 11: 11 hands basic anti-Etsuna buff bearing Ihi〉Heaven) 2λ◇ Decline plane Figure 2
Claims (1)
を形成し、その上に上層配線を形成するようにした半導
体装置の製造方法において、積層構造層間絶縁膜の下層
膜として引張り応力のプラズマＣＶＤＳｉＯ＿２膜を形
成し、同絶縁膜の上層膜として圧縮応力のプラズマＣＶ
ＤＳｉＯ＿２膜を形成することを特徴とする半導体装置
の製造方法。In a method of manufacturing a semiconductor device in which a lower layer wiring is formed on a semiconductor substrate, an interlayer insulating film is formed on the lower layer wiring, and an upper layer wiring is formed on top of the lower layer wiring, the lower layer of the interlayer insulating film in a stacked structure is Plasma CVDS SiO_2 film is formed, and compressive stress plasma CV is used as the upper layer film of the same insulating film.
A method for manufacturing a semiconductor device, characterized by forming a DSiO_2 film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10460489A JPH02284447A (en) | 1989-04-26 | 1989-04-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10460489A JPH02284447A (en) | 1989-04-26 | 1989-04-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02284447A true JPH02284447A (en) | 1990-11-21 |
Family
ID=14385026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10460489A Pending JPH02284447A (en) | 1989-04-26 | 1989-04-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02284447A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02100054A (en) * | 1988-10-07 | 1990-04-12 | Fuji Photo Film Co Ltd | Positive type photosensitive composition |
| JPH07106330A (en) * | 1993-10-08 | 1995-04-21 | Nippon Precision Circuits Kk | Formation of insulating layer in semiconductor device |
| US5514624A (en) * | 1990-08-07 | 1996-05-07 | Seiko Epson Corporation | Method of manufacturing a microelectronic interlayer dielectric structure |
-
1989
- 1989-04-26 JP JP10460489A patent/JPH02284447A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02100054A (en) * | 1988-10-07 | 1990-04-12 | Fuji Photo Film Co Ltd | Positive type photosensitive composition |
| US5514624A (en) * | 1990-08-07 | 1996-05-07 | Seiko Epson Corporation | Method of manufacturing a microelectronic interlayer dielectric structure |
| JPH07106330A (en) * | 1993-10-08 | 1995-04-21 | Nippon Precision Circuits Kk | Formation of insulating layer in semiconductor device |
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