JPH07106330A - Formation of insulating layer in semiconductor device - Google Patents
Formation of insulating layer in semiconductor deviceInfo
- Publication number
- JPH07106330A JPH07106330A JP25326493A JP25326493A JPH07106330A JP H07106330 A JPH07106330 A JP H07106330A JP 25326493 A JP25326493 A JP 25326493A JP 25326493 A JP25326493 A JP 25326493A JP H07106330 A JPH07106330 A JP H07106330A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- forming
- layer
- film
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置における絶
縁層の形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating layer in a semiconductor device.
【0002】[0002]
【従来の技術】多層配線構造を有する半導体装置におけ
る層間絶縁層の平坦化技術として、SOG(Spin
On Glass)が多用される。SOGを用いた平坦
化技術において、従来は、Alを主材料とする配線層直
上部にプラズマCVD装置で成膜されたSiO膜(以下
プラズマ酸化膜と称する)を形成し、その後SOG層を
塗布形成するのが一般的であった。2. Description of the Related Art SOG (Spin) is a technique for planarizing an interlayer insulating layer in a semiconductor device having a multilayer wiring structure.
On Glass) is often used. In the planarization technique using SOG, conventionally, an SiO film (hereinafter referred to as a plasma oxide film) formed by a plasma CVD apparatus is formed immediately above a wiring layer containing Al as a main material, and then an SOG layer is applied. It was common to form.
【0003】図3は、上記従来技術の一例を模式的に示
した断面図で、31はシリコン基板、32はフィールド
絶縁層、33はAlを主材料とする金属層、34はプラ
ズマ酸化膜、35はSOG層である。FIG. 3 is a cross-sectional view schematically showing an example of the above-mentioned prior art. 31 is a silicon substrate, 32 is a field insulating layer, 33 is a metal layer containing Al as a main material, 34 is a plasma oxide film, Reference numeral 35 is an SOG layer.
【0004】[0004]
【発明が解決しようとする課題】従来の技術において、
プラズマ酸化膜34は、層間絶縁層として、絶縁耐圧が
高く、膜応力が低く、段差被覆性が良好でなければなら
ない。また、SOGキュア時の熱負荷に対する耐熱性も
必要である。そこで、従来は、1×109 dyn/cm
2 程度の圧縮応力を持ち、しかも他の膜特性が良好とな
るように成膜条件が設定されたプラズマ酸化膜が主に用
いられていた。しかし、このような膜特性をすべて兼ね
備えたプラズマ酸化膜を形成するのは、製造工程での制
御が困難であるという問題点があった。SUMMARY OF THE INVENTION In the prior art,
As the interlayer insulating layer, the plasma oxide film 34 must have high withstand voltage, low film stress, and good step coverage. Further, heat resistance against heat load during SOG curing is also required. Therefore, conventionally, 1 × 10 9 dyn / cm
A plasma oxide film, which has a compressive stress of about 2 and whose film forming conditions are set so that other film characteristics are good, was mainly used. However, forming a plasma oxide film having all of these film characteristics has a problem that it is difficult to control in the manufacturing process.
【0005】本発明の目的は、絶縁層の製造工程におけ
る制御を容易にし、しかも耐熱性・絶縁耐圧・膜応力等
の絶縁層としての性能や信頼性の向上を可能にする半導
体装置における絶縁層の形成方法を提供することであ
る。An object of the present invention is to provide an insulating layer in a semiconductor device, which facilitates control in the manufacturing process of the insulating layer and can improve performance and reliability as an insulating layer such as heat resistance, dielectric strength, and film stress. It is to provide a method of forming.
【0006】[0006]
【課題を解決するための手段】第一の発明における半導
体装置の絶縁層の形成方法は、半導体基板の主表面側に
金属層を形成する工程と、前記金属層を覆う第一の絶縁
層を形成する工程と、前記第一の絶縁層を覆う第二の絶
縁層を形成する工程とを有し、前記第一の絶縁層は前記
第二の絶縁層より膜応力が低くしかも絶縁耐圧が高くな
るようにするものである。また、第二の発明における半
導体装置の絶縁層の形成方法は、前記第一の絶縁層と前
記第二の絶縁層を同一プラズマCVD装置で連続的に形
成し、前記第一の絶縁層と前記第二の絶縁層とでプラズ
マの放電パワーを変化させるものである。According to a first aspect of the present invention, there is provided a method of forming an insulating layer of a semiconductor device, comprising a step of forming a metal layer on a main surface side of a semiconductor substrate and a step of forming a first insulating layer covering the metal layer. And a step of forming a second insulating layer that covers the first insulating layer, wherein the first insulating layer has a lower film stress than the second insulating layer and a high withstand voltage. To be A method of forming an insulating layer of a semiconductor device according to a second aspect of the invention is the method of forming the first insulating layer and the second insulating layer continuously by the same plasma CVD apparatus, The discharge power of plasma is changed with the second insulating layer.
【0007】[0007]
【実施例】図2は、SiH4 とN2 Oを使用したプラズ
マCVD装置において形成されるプラズマ酸化膜の特性
の、プラズマ放電パワー依存性を示した図である。図2
において、aに示した放電パワーの方がbで示した放電
パワーより低いが、放電パワー以外の成膜条件は同一に
設定されている。bで示した放電パワーで成膜すると、
1×109 dyn/cm2 程度の圧縮応力を持つ従来例
と同様のプラズマ酸化膜となる。これに対して、aで示
した放電パワーで成膜すると、5×109 dyn/cm
2 程度の圧縮応力を持つプラズマ酸化膜となる。そこ
で、bで示した放電パワーで成膜するのに比べて、絶縁
耐圧が高く(図示せず)、BOE(Buffered
Oxide Etchent)によるエッチング速度と
膜応力が低くなり、膜厚均一性が良くなる。EXAMPLE FIG. 2 is a diagram showing the plasma discharge power dependence of the characteristics of the plasma oxide film formed in the plasma CVD apparatus using SiH4 and N2O. Figure 2
In, the discharge power indicated by a is lower than the discharge power indicated by b, but the film forming conditions other than the discharge power are set to be the same. When a film is formed with the discharge power shown in b,
The same plasma oxide film as the conventional example has a compressive stress of about 1.times.10@9 dyn / cm @ 2. On the other hand, when the film is formed with the discharge power indicated by a, 5 × 10 9 dyn / cm
It becomes a plasma oxide film with a compressive stress of about 2. Therefore, the withstand voltage is higher (not shown) as compared with the case where the film is formed with the discharge power shown in b, and BOE (Buffered) is used.
The etching rate and film stress due to the oxide etch are reduced, and the film thickness uniformity is improved.
【0008】図1は、本発明の実施例を模式的に示した
断面図であり、11は半導体基板、12はフィールド絶
縁層、13はAlを主材料とする金属層、14は第一の
プラズマ酸化膜、15は第二のプラズマ酸化膜、16は
SOG層である。FIG. 1 is a sectional view schematically showing an embodiment of the present invention. 11 is a semiconductor substrate, 12 is a field insulating layer, 13 is a metal layer containing Al as a main material, and 14 is a first layer. A plasma oxide film, 15 is a second plasma oxide film, and 16 is an SOG layer.
【0009】次に、図1にしたがって、実施例のプラズ
マ酸化膜(絶縁層)の形成方法を説明する。Next, a method of forming a plasma oxide film (insulating layer) of the embodiment will be described with reference to FIG.
【0010】半導体基板11の主表面側にフィールド絶
縁層12を形成し、Alを主材料とする金属層13を通
常の成膜工程とフォトリソグラフィー工程とエッチング
工程を用いて形成する。ここで、金属層13の膜厚は、
700〜900nmである。つぎに、プラズマCVD装
置において、第一のプラズマ酸化膜14を図2のaの放
電パワーで50〜150nm形成し、続いて同一プラズ
マCVD装置で、第二のプラズマ酸化膜15を図2のb
の放電パワーで200〜500nm形成する。その後、
通常の方法で、SOG層16を塗布した後、キュアす
る。A field insulating layer 12 is formed on the main surface side of a semiconductor substrate 11, and a metal layer 13 containing Al as a main material is formed by a normal film forming process, a photolithography process and an etching process. Here, the film thickness of the metal layer 13 is
It is 700 to 900 nm. Next, in the plasma CVD apparatus, the first plasma oxide film 14 is formed with a discharge power of 50 to 150 nm in FIG. 2A, and then the second plasma oxide film 15 is formed in the same plasma CVD apparatus as in FIG.
With a discharge power of 200 to 500 nm. afterwards,
After applying the SOG layer 16 by a usual method, it is cured.
【0011】上記実施例では、絶縁層を二層構造とし、
第一の絶縁層を低応力・高絶縁耐圧層、第二の絶縁層を
高耐熱層のように、それぞれの絶縁層の目的を異ならせ
ているため、それぞれの目的に応じて、製造工程におけ
る最適条件設定が可能となる。そこで、製造工程におけ
る制御が簡単になり、耐熱性・絶縁耐圧・膜応力等の絶
縁層としての性能や信頼性が、絶縁層全体として、向上
する。In the above embodiment, the insulating layer has a two-layer structure,
The purpose of each insulating layer is different, such as the first insulating layer is a low stress / high withstand voltage layer and the second insulating layer is a high heat resistant layer. Optimal conditions can be set. Therefore, the control in the manufacturing process is simplified, and the performance and reliability of the insulating layer such as heat resistance, dielectric strength, and film stress are improved as the entire insulating layer.
【0012】また、上記実施例では、同一プラズマCV
D装置で放電パワー条件だけを変更した連続ステップで
形成するため、新たな成膜装置やガス系の供給・排気配
管が不要である。In the above embodiment, the same plasma CV is used.
Since the device D is formed by successive steps in which only the discharge power condition is changed, a new film forming device and a gas system supply / exhaust pipe are not required.
【0013】尚、上記実施例では、多層配線構造を有す
る半導体装置における平坦化技術に用いるSOG層の下
に形成されるプラズマ酸化膜に適用したが、最終保護層
として用いるプラズマ窒化膜の下に形成されるプラズマ
酸化膜に適用してもかまわない。Although the above-mentioned embodiment is applied to the plasma oxide film formed under the SOG layer used for the planarization technique in the semiconductor device having the multilayer wiring structure, it is applied under the plasma nitride film used as the final protective layer. It may be applied to the formed plasma oxide film.
【0014】[0014]
【発明の効果】本発明の半導体装置における絶縁層の形
成方法では、絶縁層を二層構造とし、第一の絶縁層を低
応力・高絶縁耐圧層、第二の絶縁層を高耐熱層のよう
に、それぞれの絶縁層の目的を異ならせているため、そ
れぞれの目的に応じて、製造工程における最適条件設定
が可能となる。したがって、絶縁層の製造工程における
制御が容易になり、しかも耐熱性・絶縁耐圧・膜応力等
の絶縁層としての性能や信頼性の向上が可能になる。According to the method for forming an insulating layer in a semiconductor device of the present invention, the insulating layer has a two-layer structure, the first insulating layer is a low stress / high withstand voltage layer, and the second insulating layer is a high heat resistant layer. As described above, since the purpose of each insulating layer is different, it is possible to set the optimum conditions in the manufacturing process according to each purpose. Therefore, control in the manufacturing process of the insulating layer becomes easy, and the performance and reliability of the insulating layer such as heat resistance, dielectric strength, and film stress can be improved.
【図1】本発明の実施例を模式的に示した断面図であ
る。FIG. 1 is a sectional view schematically showing an embodiment of the present invention.
【図2】本発明の実施例におけるプラズマ酸化膜特性の
プラズマ放電パワー依存性を示した図である。FIG. 2 is a diagram showing plasma discharge power dependence of plasma oxide film characteristics in the example of the present invention.
【図3】従来例を模式的に示した断面図である。FIG. 3 is a sectional view schematically showing a conventional example.
11………半導体基板 13………金属層 14………第一のプラズマ酸化膜(第一の絶縁層) 15………第二のプラズマ酸化膜(第二の絶縁層) 11 ... Semiconductor substrate 13 Metal layer 14 First plasma oxide film (first insulating layer) 15 Second plasma oxide film (second insulating layer)
Claims (4)
る工程と、 上記金属層を覆う第一の絶縁層を形成する工程と、 上記第一の絶縁層を覆う第二の絶縁層を形成する工程と
を有し、 上記第一の絶縁層は上記第二の絶縁層より膜応力が低く
しかも絶縁耐圧が高くなるようにすることを特徴とする
半導体装置における絶縁層の形成方法。1. A step of forming a metal layer on the main surface side of a semiconductor substrate, a step of forming a first insulating layer covering the metal layer, and a second insulating layer covering the first insulating layer. And a step of forming the insulating layer, wherein the first insulating layer has a lower film stress and a higher dielectric strength than the second insulating layer.
る工程と、 上記金属層を覆う第一の絶縁層をプラズマCVD装置で
形成する工程と、 上記第一の絶縁層を覆う第二の絶縁層を上記プラズマC
VD装置で連続的に形成する工程とを有し、 上記第一の絶縁層と上記第二の絶縁層とでプラズマの放
電パワーを変化させることを特徴とする半導体装置にお
ける絶縁層の形成方法。2. A step of forming a metal layer on the main surface side of a semiconductor substrate, a step of forming a first insulating layer covering the metal layer with a plasma CVD apparatus, and a second step of covering the first insulating layer. The insulating layer of the plasma C
And a step of continuously forming with a VD device, wherein the discharge power of plasma is changed between the first insulating layer and the second insulating layer.
あることを特徴とする請求項1または請求項2に記載の
半導体装置における絶縁層の形成方法。3. The method for forming an insulating layer in a semiconductor device according to claim 1, wherein the metal layer has Al as a main material.
酸化シリコンを主成分とした層であることを特徴とする
請求項1または請求項2に記載の半導体装置における絶
縁層の形成方法。4. The insulating layer in a semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are layers containing silicon oxide as a main component. Forming method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25326493A JPH07106330A (en) | 1993-10-08 | 1993-10-08 | Formation of insulating layer in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25326493A JPH07106330A (en) | 1993-10-08 | 1993-10-08 | Formation of insulating layer in semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07106330A true JPH07106330A (en) | 1995-04-21 |
Family
ID=17248865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25326493A Pending JPH07106330A (en) | 1993-10-08 | 1993-10-08 | Formation of insulating layer in semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07106330A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09102494A (en) * | 1995-10-09 | 1997-04-15 | Toshiba Corp | Protective film for semiconductor device and forming method therefor |
JP2009170544A (en) * | 2008-01-11 | 2009-07-30 | Rohm Co Ltd | Semiconductor apparatus |
JP2012156356A (en) * | 2011-01-27 | 2012-08-16 | Elpida Memory Inc | Method for manufacturing semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02284447A (en) * | 1989-04-26 | 1990-11-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH03280539A (en) * | 1990-03-29 | 1991-12-11 | Fuji Electric Co Ltd | Fabrication method for semiconductor device with insulation layer |
JPH04177751A (en) * | 1990-11-09 | 1992-06-24 | Sony Corp | Formation of insulating film |
JPH0745610A (en) * | 1993-07-28 | 1995-02-14 | Matsushita Electron Corp | Manufacture of semiconductor device |
-
1993
- 1993-10-08 JP JP25326493A patent/JPH07106330A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02284447A (en) * | 1989-04-26 | 1990-11-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH03280539A (en) * | 1990-03-29 | 1991-12-11 | Fuji Electric Co Ltd | Fabrication method for semiconductor device with insulation layer |
JPH04177751A (en) * | 1990-11-09 | 1992-06-24 | Sony Corp | Formation of insulating film |
JPH0745610A (en) * | 1993-07-28 | 1995-02-14 | Matsushita Electron Corp | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09102494A (en) * | 1995-10-09 | 1997-04-15 | Toshiba Corp | Protective film for semiconductor device and forming method therefor |
JP2009170544A (en) * | 2008-01-11 | 2009-07-30 | Rohm Co Ltd | Semiconductor apparatus |
JP2012156356A (en) * | 2011-01-27 | 2012-08-16 | Elpida Memory Inc | Method for manufacturing semiconductor device |
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