JP3676034B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

【００３５】
【表２】

【００３６】
なお、表１の条件で成長させたSiOF膜の誘電率は３．６となり、表２の条件で成長させたSiO₂膜の誘電率は４．２となった。
ＥＣＲ−ＣＶＤ装置
第２図は本発明に関するECR-CVD 装置の概略図である。
ECR-CVＤ装置はプラズマ室３１と反応室３２を有し、プラズマ室３１にはマイクロ波導波管３４を介してマイクロ波電源３３が接続されていて、マイクロ波電源３３からマイクロ波をプラズマ室３１に導入することにより、プラズマ室３１内に導入したガスが励起されて、プラズマが形成するようになっている。
【００３７】
また、反応室３２の上方に配置したメインソレノイドコイル（ＭＳＣ）３５によって反応室３２内に磁界を発生させることにより、反応室３２内のプラズマ密度とエネルギーを増幅するようになっている。そのプラズマ密度とプラズマエネルギーは、メインソレノイドコイル３５に流す電流量によって変化させることができる。
【００３８】
また、プラズマ室３１内には、SiO₂またはSiOFの膜成長のために第一のマスフローコントローラ３６、第一のガス管３７を介してアルゴン源３８が接続され、さらに第２のマスフローコントローラ３９、第２のガス管４０を介して酸素源４１が接続されている。さらに、反応室３２には、SiO₂の膜成長のために第３のマスフローコントローラ４２、第３のガス管４３を介してシリコン源のSiH₄ボンベ４４が接続され、さらにSiOFの膜成長のために第４のマスフローコントローラ４５、第４のガス管４６を介してフッ素源のSiF₄ボンベ４７が接続されている。
【００３９】
なお、第１〜第４のマスフローコントローラ３６、３９、４２、４５は、ガス流量を制御するものである。
さらに、反応室３２内ではプラズマ室３１の下方にプレート４８が配置され、その上には、半導体基板Ｗを吸着するための静電チャック４９が配置されている。静電チャック４９には13.56MHzの高周波（RF）電源５０が接続されていて、RF電極５０の印加によって半導体ウエハＷとプラズマ室３１の間に電位が発生する。この電位よってプラズマ室３１からArイオンが加速され、スパッタリング現象が起こる。スパッタリングと原料ガス(SiF₄, SiH₄)の堆積が半導体基板Ｗ上で協奏的に起こり、後述するように、狭い半導体基板Ｗ上の配線間に絶縁膜が埋め込まれる。静電チャック４９は抵抗加熱によって例えば２００℃まで加熱されているが、スパッタリングによる成膜時の温度は２５０℃に到達する。
【００４０】
プレート４８の下方にはサブソレノイドコイル（ＳＳＣ）５１が配置されていて、サブソレノイドコイル５１はプラズマ室３１から発散するプラズマを磁界によって収束させる役割をする。即ち、サブソレノイドコイル５１は、そこに流される電流量によってプラズマ形状を変化させる機能を有している。
半導体ウエハＷを中心に対称形状のプラズマを形成すると、膜厚分布が改善され、半導体装置に与えるブラズマダメージを軽減することができる。
【００４１】
なお、反応室３２にはターボモレキュラーポンブ５２が接続されており、これにより反応室３２内にあるガスを排気し減圧する。
そのＥＣＲ−ＣＶＤ装置を用いてSiOF成長を行う条件の一例を表３に示し、SiO₂成長を行う条件の一例を表４に示す。
【００４２】
【表３】

【００４３】
【表４】

【００４４】
ここで、表３の条件で成長させたSiOF膜の誘電率は３．５、表４の条件で成長させたSiO₂膜の誘電率は４．２となった。
なお、ＥＣＲ−ＣＶＤ装置を用いた膜の成長は、平行平板型プラズマＣＶＤ装置を用いて膜を形成する場合に比べて高密度の配線層間を埋める能力が高い。
次に、上記した装置を用いた配線構造の形成方法を示す。なお、以下に示す膜厚は、特に領域を特定しない場合には、パッドのような幅の広い配線上の最も厚い膜厚の部分を示している。
（第１実施形態）
本発明における第一の実施形態を図３、図４に示す。
【００４５】
まず、図３(a) に示すように、平行平板型のプラズマＣＶＤ装置を用いてシリコン基板（半導体基板）６１上にSiO₂よりなる下地絶縁膜６２を５０００Åの厚さに成長する。続いて、下地絶縁膜６２の上に、チタン（Ti）膜を３００Å、窒化チタン（TiN)膜を５００Å、アルミニウム（Al）膜を６０００Å、TiN 膜を５００Å及びTi膜を３００Åの厚さに順に成長する。このような５層の金属膜をパターニングして一層目の配線６３を形成する。一層目の配線６３の形成領域には、配線幅が狭く且つ配線間隔が狭い高配線密度領域６３ａと、その逆の低配線密度領域６３ｂがある。
【００４６】
次に、図３(b) に示すように、ＥＣＲ−ＣＶＤ装置を用いて一層目の配線６３を覆うための第一のSiOF膜６４を１４０００Åの厚さに成長する。ＥＣＲ−ＣＶＤ装置を使用すると、高配線密度領域６３ａでは薄く、低配線密度領域６３ｂでは厚くなる。この第一のSiOF膜６４は、上記した表３に示した条件により成長したものであって誘電率が３．５となっている。
【００４７】
そのＥＣＲ−ＣＶＤ装置によれば、横方向の配線同士の間でArイオンによるエッチング効果を伴って膜が成長するために、横方向の配線同士の間を完全に埋め込む。これにより、第一のSiOF膜６４の配線上の膜厚は、高配線密度領域６３ａで６０００Åと薄く、低配線密度領域６３ｂでは１４０００Å程度と厚くなる。
次に、図３(c) に示すように、上記した平行平板型プラズマＣＶＤ装置を用いて表２の条件で第一のSiO₂膜（絶縁膜）６５を７０００Åの膜厚に形成する。その第一のSiO₂膜６５は、全体にほぼ均一の厚さに成長されるが、その上面にはSiOF膜６４の凹凸が反映するので、低配線密度領域６３ｂでの第一のSiO₂膜６５の上面は他の領域の第一のSiO₂膜６５よりも高い位置に存在することになる。
【００４８】
第二のSiO₂膜６５を平行平板型プラズマＣＶＤ装置を用いて成長したのは、ＥＣＲ−ＣＶＤ装置を用いる場合よりも膜の成長が速いからである。
次に、第一のSiO₂膜６５をＣＭＰによって研磨して、図３(d) に示すように、一層目の配線６３の上の絶縁膜（第一のSiOF膜６４及び第一のSiO₂膜６５）が一層目の配線６３上面から９０００Åとなるまで平坦化する。
【００４９】
低配線密度領域６３ｂで第一のSiOF膜６４が露出する場合には、図４(a) に示すように、平行平板型プラズマＣＶＤ装置によってSiO₂よりなる第一の絶縁性キャップ膜６６を１０００Åの厚さに成長する。
次に、図４(b) に示すように、第一のSiOF膜６４及び第一のSiO₂膜６５をパターニングして例えば高配線密度領域６３ａ内の１つの配線６３の上にリソグラフィーによりビアホール６７を開口する。続いて、ビアホール６７内壁に沿ってグルーレイヤー６８として窒化チタン（TiN ）をスパッタリングによって成長し、続いてＣＶＤ法によってプラグ６９となるタングステン（Ｗ）を成長した。それらのグルーレイヤー６８とプラグ６９はエッチバックによりビアホール６７内に残される。ビアホール６７の形成は、図のように高密度配線領域６３ａのみならず低密度配線領域６３ｂに形成される。
【００５０】
この後に、図３(a) 〜(d) 、図４(a),(b) の工程をもう１度繰り返して二層目の配線構造を形成する。
即ち、第一の絶縁性キャップ膜６６の上に二層目の配線７０を成長し、さらに二層目の配線７０を覆う第二のSiOF膜７１を成長し、ついで第二のSiOF膜７１を覆う第二のSiO₂膜７２を成長する。その後に、第二のSiO₂膜７２及び第二のSiOF膜７１をＣＭＰにより研磨して平坦化する。さらに、研磨により露出した第二のSiOF膜７１を覆うためにSiO₂よりなる第二の絶縁性キャップ膜７３を成長する。これにより、図４(c) に示すような断面が得られる。
【００５１】
なお、そのような多層配線構造において、SiOF膜と絶縁性キャップ膜は層間絶縁として機能する。
以上で、二層構造配線の形成が終了するが、その後にさらに三、四層目の配線を形成してもよい。
上述した第一及び第二の絶縁性キャップ膜６６，７３は、第一及び第二のSiOF膜６４，７１が大気に曝されるのを防止するために形成したものである。仮に、第一の絶縁性キャップ膜６６を成長せずに、第一のSiOF膜６４の一部を大気に曝した状態で、コンタクトホール６７形成に続いてTiN 膜とＷ膜を膜成長すると、第一のSiOF膜６４とTiN 膜との密着性の悪さに起因して、第一のSiOF膜６４とTiN 膜の界面でTiN 膜が剥がれてしまう。
【００５２】
しかし、本実施形態では、ＣＭＰにより露出した第一及び第二のSiOF膜６４，７１の吸湿が第一及び第二の絶縁性キャップ膜６６，７３により阻止される。なお、SiOF膜とSiO₂膜との密着性は極めて高い。
なお、第一及び第二のSiO₂膜（第一、第二のキャップ膜）６６，７３の形成前にアニール炉（不図示）で第一及び第二のSiOF膜６４，７１を３００℃以上の温度で加熱するか、或いは、膜成長装置内で３００℃以上の温度でプレヒートを行うと、第一及び第二のSiOF膜６４，７１の吸湿による誘電率の増加が抑制される。本実施形態では後者の方法を３０秒間行った。
（第２実施形態）
本発明における第２の実施形態を第５図に示す。
【００５３】
まず、第１実施形態で説明したと同様な方法により、図５(a) に示すように、シリコン基板上６１にSiO₂よりなる下地絶縁膜６２を成長し、その上に一層目の配線６３を形成する。この一層目の配線６３は、高密度配線領域６３ａと低密度配線領域６３ｂとを有する。この場合の下地絶縁膜６２及び一層目の配線６３の成長条件について、第１実施形態と同様にする。
【００５４】
その後に、一層目の配線６３上にＥＣＲ−ＣＶＤ装置により誘電率３．５の第一のSiOF膜６４ａを１４０００Åの厚さに膜成長する。この場合、配線６３上の第一のSiOF膜６４ａは、高密度配線領域６３ａで６０００Åと薄く、低密度配線領域６３ｂで１４０００Åと厚く成長する。これに続いて、表１の条件で、平行平板型プラズマＣＶＤ装置によって誘電率３．６の第二のSiOF膜６５ａを７０００Åの厚さに膜成長した。
【００５５】
次に、第一及び第二のSiOF膜６４ａ，６５ａを研磨して一層目の配線６３上での膜厚が９０００ÅとなるまでＣＭＰにより研磨する。
その後に、平坦化された第一及び第二のSiOF膜６４ａ，６５ａの上にSiO₂よりなる第一の絶縁性キャップ膜６６ａを１０００Åの厚さに成長する。この第一の絶縁性キャップ６６ａの形成目的は、第１実施形態と同様に、第一及び第二のSiOF膜６４ａ，６５ａの吸湿防止と金属膜の膜剥がれ防止のためである。
【００５６】
次に、図５(d) に示すように、第一及び第二のSiOF膜６４ａ，６５ａ及び第一の絶縁性キャップ膜６６ａのうち一層目の配線６３の上にリソグラフィーによりビアホール６７を開口する。続いて、ビアホール６７内壁に沿ってグルーレイヤー６８として窒化チタン（TiN ）をスパッタリングによって形成し、続いてＣＶＤ法によってプラグ６９となるタングステン（Ｗ）を成長した。それらのグルーレイヤー６８とプラグ６９はエッチバックによりビアホール６７内に残される。
【００５７】
この後に、配線形成からキャップ膜形成までの工程をもう１度繰り返して二層目の配線構造を形成する。即ち、第一の絶縁性キャップ膜６６ａの上に二層目の配線７０を成長し、さらに二層目の配線７０を覆う第三のSiOF膜７１ａをＥＣＲ−ＣＶＤ装置内で成長し、ついで、その上に第四のSiOF膜７２ａを平行平板型プラズマＣＶＤ装置内で成長する。その後に、第三及び第四のSiOF膜７１ａ，７２ａをＣＭＰにより研磨して平坦化した後に、第三及び第四のSiOF膜７１ａ，７２ａを覆うために第二のキャップ膜として第二の絶縁性キャップ膜７３ａを成長する。
【００５８】
以上のような多層配線構造において、SiOF膜と絶縁性キャップ膜は層間絶縁として機能する。
この第２実施形態では、一層目と二層目の配線６３，７０の間に形成される層間絶縁膜を第一及び第二のSiOF膜６４ａ，６５ａから構成したので、第１実施形態に比べて、誘電率を低下させて配線間の寄生容量が減ることになる。
【００５９】
また、フッ素含有量を減らすことによって、層間絶縁膜となる上側の第二のSiOF膜６５ａの誘電率を下側の第一のSiOF膜６４ａの誘電率よりも高くしているので、層間絶縁膜の大気からの吸湿性は低下する。
なお、第一及び第二のSiOF膜６４ａ，６５ａ自体は、金属との膜剥がれが生じやすい。しかし、第一及び第二のSiOF膜６４ａ，６５ａの上に絶縁性キャップ膜６６ａを形成しているので、第１実施形態と同様に、その第二のSiO₂膜６６ａによってグルーレイヤー６８の膜剥れは生じない。
（第３の実施の形態）
本発明における第３実施形態を図６、図７に基づいて説明する。
【００６０】
まず、平行平板型プラズマＣＶＤ装置によって膜厚５０００ÅのSiO₂よりなる下地絶縁膜８２をシリコン基板８１の上に形成した後に、第１実施形態と同じ多層構造を有する一層目の電極８３を形成する。一層目の配線８３の形成領域には、配線幅が狭く且つ配線間隔が狭い高配線密度領域８３ａと、その逆の低配線密度領域８３ｂがある。
【００６１】
続いて、一層目の電極８３及び下地絶縁膜８２を覆う第一のSiOF膜８４を、表３の条件で、ＥＣＲ−ＣＶＤ装置によって２１０００Åの厚さに成長する。
その後に、第一のSiOF膜８４が吸湿した水分を除去するために、アニール炉で３００℃以上の温度で第一のSiOF膜８４を加熱するか、膜成長装置内で３００℃以上の温度でプレヒートする。本実施形態では後者を30秒間行った。
【００６２】
次に、図６(b) に示すように、第一のSiOF膜８４をＣＭＰにより研磨して一層目の配線８３上での厚さが９０００Åとなるまで平坦化する。
この後に、図６(c) に示すように、SiO₂よりなる絶縁性キャップ膜８５を平行平板プラズマＣＶＤ装置によって表２の条件で１０００Åの厚さに成長し、これにより第一のSiOF膜８４の大気からの吸湿を防止するとともにその後の工程で成長される金属膜の膜剥がれを防止する。
【００６３】
次に、フォトリソグラフィーにより第一のSiOF膜８４及び絶縁性キャップ膜８５の一部をエッチングして、一層目の配線に繋がるビアホール８６を形成する。そして、図７(a) に示すように、ビアホール８６内壁に沿ってグルーレイヤー８７として窒化チタン（TiN ）をスパッタリングによって成長し、続いてＣＶＤ法によってプラグ８８となるタングステン（Ｗ）を成長した。それらのグルーレイヤー８７とプラグ８８はエッチバックによってビアホール８６内に残される。
【００６４】
この後に、図６(a) 〜(c) に示す工程をもう１度繰り返して二層目の配線構造を形成する。即ち、第一の絶縁性キャップ膜８５の上に二層目の配線９０を成長し、さらに二層目の配線９０を覆う第二のSiOF膜９１を成長し、ついで、第二のSiOF膜９１をＣＭＰにより研磨して平坦化した後に、露出した第二のSiOF膜９１を覆うためにSiO₂よりなる第二の絶縁性キャップ膜９２を成長する。これにより図７(b) に示すような断面構造が得られる。
【００６５】
以上で、二層構造配線の形成が終了するが、その後にさらに三、四層目の配線を形成して多層配線構造としてもよい。
以上のような構成の多層配線構造によれば、一層目の配線８３をSiOF膜８４によって覆った後にそのSiOF膜８４を研磨して平坦化し、さらに、その平坦化された面を薄い第一の絶縁性キャップ膜８５によって覆うようにしたので、吸湿性が低下し、しかも層間絶縁膜の上に形成される金属の膜剥がれは防止される。
【００６６】
なお、上記した３つの実施形態において、絶縁性キャップ膜をSiO₂から形成しているが、Si₃N₄ から形成してもよい。
次に、上記した実施形態の配線容量と動作速度の改善について説明する。
第１〜３の実施形態と従来技術との配線容量の比較
配線容量を比較する試料は、一層目の配線と二層目の配線の間にある層間絶縁膜の材料以外の構成を全て同じにした。また、従来技術として図１０〜図１２に示した２つの製造方法によって形成された半導体装置を用いた。
【００６７】
まず、図１０(c) に示した、SiO₂のみからなる層間絶縁膜を有する試料について配線容量を調べ、その容量を基準容量値Ｃ₀ とした。ただし、図１０(c) の一層目のSiO₂膜は表４の条件で成長され、二層目のSiO₂膜は表２の条件で成長されたものである。
そして、第１〜第３の実施形態の装置と図１2 (b) に示した従来装置の配線容量が基準容量値Ｃ₀ に対してどのような値（配線容量比）をとるか調べたところ図８(a) に示すような結果が得られた。
【００６８】
図８(a) では、基準容量Ｃ₀ を１とした場合の配線容量比を示しており、配線容量比の値が小さいほど効果的な配線容量の低下がなされている。
第２実施形態の容量比が７９％と最も低い値を示した。また、第１実施形態の容量比が低く８２％であった。本来であれば、一層目と二層目の配線間の層間絶縁膜の大部分が誘電率３．５のSiOFからなっている第３実施形態の容量比が最も低い値を示すと予想したが、実測の値は８４％であった。この理由は、図６(c) に示すまでの工程、即ち第一のSiOF膜８４を第一の絶縁性キャップ膜８５により覆うまでの間に、上面が露出した第一のSiOF膜８４が大気中の水分を吸湿したためであり、これは第一の絶縁性キャップ膜８５の膜成長前に行ったプレヒートが十分ではなかったからである。
【００６９】
水分の吸収は配線幅の狭い高密度配線の信頼性を低下させるため、0.２５μｍ以後のデザインルールで作製される半導体装置の懸念材料となる。従って、実施形態のように、キャップ膜を形成するまでの間も、高密度配線領域の配線を覆うSiOF膜を、SiO₂膜または誘電率３．６以上の吸湿の小さい別のSiOF膜により覆うことが好ましい。
【００７０】
従来法図１１〜図１２によって作製した場合の配線間の容量比は８８％と他に比べて高かった。この理由は、従来技術の欄で述べたように、層間絶縁膜の大部分がSiO₂からなっているためである。この程度の容量の低下では、デバイスの動作速度の改善には繋がらない。
第１〜第３の実施の形態と２つの従来技術例の各々の試料における一層目の配線と二層目の配線の形状の概略は図８(b) に示すようであり、横方向の配線間の距離は４５００Åである。また、配線の一層当たりの高さは７６００Åである。一層目の配線と二層目の配線の膜厚方向の距離、即ち、層間絶縁膜の膜厚は１００００Åである。
【００７１】
そして、一層目の配線と二層目の配線にパッドを接続し、そのパッドに電圧を印加して配線間容量を測定した。
第１〜３の実施形態と従来技術との動作速度の比較
動作速度を比較するための試料は、一層目の配線と二層目の配線の間にある層間絶縁膜の材料以外の構成を全て同じにした。また、従来技術として、図１０〜図１２で示した２つの製造方法によって形成された多層配線構造を有する半導体装置を用いた。
【００７２】
まず、図１０に示した、SiO₂のみからなる層間絶縁膜を有する試料について動作速度を調べ、その動作速度を基準速度Ｔ₀ とした。
そして、第１〜第３の実施形態の装置と図１０(c) 、図１２(b) に示した２つの従来装置のそれぞれの動作速度を調べたところ、図９(a) に示すような結果が得られた。
【００７３】
図９(a) では、図１０(c) の基準動作速度Ｔ₀ に対する他の資料の割合（動作速度比）を示しており、動作速度比の値が小さいほど動作速度が速いことになる。第２の実施形態と同じ方法によって作製した半導体装置の動作速度比が最も低く８６％であった。続いて、第一の実施形態による半導体装置の速度比が８８％であった。第３の実施形態による半導体装置の速度比は８９％と第１及び第２の実施形態に比べて高い値を示した。即ち、配線容量の実験結果について述べたように、第３実施形態で形成された装置では、SiOF膜をSiO₂膜でキャッピングするまでの間に吸湿が起こり、配線容量が十分低下していないことが理由に考えられる。図１１、図１２の従来法による半導体装置の動作速度比は９４％とあまり改善されていなかった。
【００７４】
以上のことから、動作速度の測定結果は配線容量の測定結果と相関がとれていることがわかった。
なお、動作速度の測定は、図９(b) に示すように、直列に２００個のトランジスタを接続した試験回路の途中に上記した一層目と二層目の配線を接続して行われている。これにより試験回路の配線容量の負荷が変わり、その配線容量が大きいと動作速度が遅くなることになる。
【００７５】
【発明の効果】
以上述べたように本発明によれば、配線を覆うフッ素含有シリコン酸化膜（SiOF膜）をSiO2のような絶縁膜で覆った後、SiOF膜の一部が露出するまで絶縁膜を研磨して平坦化した後に、露出したSiOF膜を覆うSiO₂のような吸湿防止用の絶縁性キャップ膜を形成したので、SiOF膜は、絶縁膜によって大気からの水分の吸収が妨げられ、しかも低誘電率の層間絶縁膜からの金属膜の剥がれを防止でき、さらに、SiOF膜の直上の絶縁膜を研磨することによって層間絶縁膜に占めるSiOF膜の膜厚の割合を大きくして配線間の寄生容量を効果的に低容量化できる。
【００７６】
さらに、１つの層間絶縁膜を単層又は複数のSiOF膜から形成し、少なくともその最上層を研磨することにより平坦化するとともに、その上を吸湿防止用の絶縁性キャップ膜により覆うようにしたので、フッ素含有シリコン酸化膜は、絶縁性キャップ膜によって大気からの水分の吸収が妨げられ、低誘電率の層間絶縁膜からの金属膜の剥がれを防止でき、さらに、SiOF膜を研磨することによって高密度配線領域の上の層間絶縁膜に占めるSiOF膜の膜厚を他の領域とほぼ同じ厚さににして配線間の寄生容量の効果的な低容量化を可能にする。
【００７７】
また、複数のSiOF膜のうちその最上のSiOF膜のフッ素含有量を減らしてその誘電率を高くしたので、防湿用の絶縁性キャップ膜を形成する前の状態でのSiOF膜の吸湿性を抑えて、層間絶縁膜としてのSiOF膜の誘電率の増加を抑制することができる。
【図面の簡単な説明】
【図１】図１は、本発明の実施形態に使用する平行平板型プラズマＣＶＤ装置の一例を示す概要構成図である。
【図２】図２は、本発明の実施形態に提供するＥＣＲ−ＣＶＤ装置の一例を示す概要構成図である。
【図３】図３は、本発明の第１実施形態の半導体装置の配線構造の製造工程を示す断面図（その１）である。
【図４】図４は、本発明の第１実施形態の半導体装置の配線構造の製造工程を示す断面図（その２）である。
【図５】図５は、本発明の第２実施形態の半導体装置の配線構造の製造工程を示す断面図である。
【図６】図６は、本発明の第３実施形態の半導体装置の配線構造の製造工程を示す断面図（その１）である。
【図７】図７は、本発明の第３実施形態の半導体装置の配線構造の製造工程を示す断面図（その２）である。
【図８】図８（ａ）は、本発明の第１〜第３実施形態の配線構造の試料と２つの従来例の試料との配線容量の大きさを比較するための実験結果であり、図８（ｂ）は、それらの試料の共通した配線構造を示す図である。
【図９】図９（ａ）は、本発明の第１〜第３実施形態の配線構造の試料と２つの従来例の試料との動作速度を比較するための実験結果であり、図９（ｂ）は、その試験に用いる回路図である。
【図１０】第１の従来例による半導体装置の配線構造の製造工程を示す断面図である。
【図１１】第２の従来例による半導体装置の配線構造の製造工程を示す断面図（その１）である。
【図１２】第２の従来例による半導体装置の配線構造の製造工程を示す断面図（その２）である。
【符号の説明】
６１…シリコン基板（半導体基板）、６２…下地絶縁膜、６３…一層目の配線、６３ａ…高密度配線領域、６３ｂ…低密度配線領域、６４…第一のSiOF膜、６５…第一の絶縁膜、６６…第一の絶縁性キャップ膜、６４ａ…第一のSiOF膜、６５ａ…第二のSiOF膜、６６ａ…第一の絶縁性キャップ膜、６７…ビアホール、６８…グルーレイヤー、６９…プラグ、７０…二層目の配線、７１…第二のSiOF膜、７２…第二の絶縁膜、７３…第二の絶縁性キャップ膜、７１ａ…第三のSiOF膜、７２ａ…第四のSiOF膜、７３ａ…第二の絶縁性キャップ膜、８１…シリコン基板（半導体基板）、８２…下地絶縁膜、８３…一層目の配線、８３ａ…高密度配線領域、８３ｂ 低密度配線領域、８４…第一のSiOF膜、８５…第一の絶縁性キャップ膜、８６…ビアホール、８７…グルーレイヤー、８８…プラグ、９０…二層目の配線、９１…第二のSiOF膜、９２…第二の絶縁性キャップ膜。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a multilayer wiring structure and a method for manufacturing a semiconductor device including a step of forming the multilayer wiring structure.
[0002]
[Prior art]
In recent years, due to the demand for higher integration and higher speed of semiconductor devices, review of insulating layer materials for multilayer wiring layers in semiconductor devices has been carried out. Silicon dioxide (SiO₂) Is a conventionally used insulating material for semiconductor devices. However, since the dielectric constant is as high as 4.2, the parasitic capacitance between the wirings is large, which increases the signal propagation delay time of the wirings. An increase in signal propagation delay is a factor that decreases the operating speed of the semiconductor device. In the future, as the miniaturization progresses, the distance between the wirings will become shorter and further, the parasitic capacitance becomes larger, and the increase in signal propagation delay time becomes a problem.
[0003]
Next, SiO₂A method for forming a multilayer wiring structure in the case where is used as an interlayer insulating film will be briefly described.
First, as shown in FIG. 10A, a first SiO 2 film is formed on the wiring 103 patterned on the silicon substrate 101 by CVD (Chemical Vepor Deposition).₂The film 104 is grown to a thickness of, for example, 7000 mm to embed wiring. Its first SiO₂The film 104 is thin in a region where the wiring density is high, and is thick in a region where the wiring density having a pad or the like is low. Subsequently, the second SiO₂The film 105 is formed to a thickness of 14000 mm, for example. These first and second SiO₂The films 104 and 105 are used as interlayer insulating films. In this case, the first SiO₂The growth of the film 104 is performed under the condition that the wiring between the lateral wirings is completely buried, and the second SiO 2₂The growth of the film 105 is performed under such a condition that unevenness does not occur so much.
[0004]
Next, as shown in FIG. 10 (b), the second SiO₂The film 105 is polished and planarized by CMP (ChemicaI MechanicaI Polishing). Then the first and second SiO₂Via holes 106 are opened in the films 104 and 105, a TiN glue layer is grown at the bottom of the via holes 106, and a plug is grown to fill the contact holes 106 with a conductive material such as tungsten or aluminum. The first SiO was polished by CMP.₂Under the growth conditions of the film 104, the first SiO₂This is because the film 104 is thin in a region where the wiring density is high and grows thick in a low region. The unevenness caused by this is the second SiO₂This is because the film 105 is also uneven.
[0005]
If such a process is repeated twice, SiO having a two-layer structure as shown in FIG.₂A two-layer wiring layer is formed.
In order to reduce the parasitic capacitance between the wirings, it is effective to use a substance having a low dielectric constant as the interlayer insulating film material, thereby shortening the signal propagation delay time. For example, a silicon oxyfluoride (SiOF) film formed by adding fluorine (F) to silicon dioxide has a low dielectric constant. By applying this material to an insulating film of a multilayer wiring, parasitic capacitance between wirings is reduced. Speeding up the device.
[0006]
  Up to now, SiOF has high hygroscopicity, and when moisture is absorbed, the dielectric constant becomes high and becomes ineffective as a material for interlayer insulation.
  In order to suppress the moisture absorption, oxygen (O₂) Or after the SiOF film formationplasmaIt has been reported to perform annealing or control the plasma density and energy during SiOF growth.
[0007]
  However, if the dielectric constant of SiOF is made 3.5 or less, the hygroscopicity becomes high, and it becomes difficult to control the hygroscopicity even by such a method. Also, when water becomes contained in the SiOF film due to its hygroscopicity, it is formed on itMetal wiringThere is a risk of corrosion.
  Those problems are SiO₂This can be avoided by capping of the SiOF film by the method, which has already been proposed in Japanese Patent Laid-Open No. 7-74245. The multi-layer forming method proposed here uses a conventional parallel plate type plasma CVD apparatus, using tetraethylorthosilicate (TEOS) as a silicon (Si) source and triethoxyfluorosilane (TEFS) or three fluorine as an F source. Nitrogenide (NF_Three). Parallel plate type plasma CVD and these reaction systems can be applied to generations of semiconductor devices with a wide wiring spacing and low wiring aspect ratio (0.35 μm or less in terms of design rules). Other technologies are essential.
[0008]
  HDP (High Density Plasma) -CVD has narrow wiring spacing and high aspect ratioThe lateral direction of the wiringThis is a CVD technique for interposing an insulating film between each other. Further, a polishing method called CMP is applied to planarize the insulating film. Although a combination of HDP-CVD and CMP is considered to be effective as a multilayer wiring formation technique after the design rule of 0.25 μm, the capacity reduction between wirings using SiOF has not been sufficiently achieved.
[0009]
Therefore, a method for forming a multilayer interlayer insulating film when SiOF is used will be described below.
First, as shown in FIG. 11A, after patterning the wiring 103 on the silicon substrate 101, the SiOF film 110 is grown to a thickness of, eg, 7000 mm by HDP-CVD to cover the wiring 103. The film thickness of the SiOF film 110 is thin in a region where the wiring density is high, and is thick in a region where the wiring density having a pad or the like is low.
[0010]
Next, as shown in FIG.₂The film 111 is formed to a thickness of 14000 mm, for example. Its SiO₂The growth of the film 111 may be either parallel plate CVD or HDP-CVD. FIG. 11B shows the uneven shape of the insulating film when HDP-CVD is used. In the parallel plate type CVD, there is no big difference as long as the unevenness of the insulating film formed on the wiring becomes somewhat gentler than HDP.
[0011]
If a plurality of wirings and an interlayer insulating film are further stacked in this state, a step due to unevenness is likely to occur. A CMP technique is used to eliminate such a step.
Therefore, as shown in FIG.₂The surface of the film 111 is polished and flattened. At this time, the polishing amount must be set so that the SiOF film 110 on the low-density wiring is not exposed. This is because when the SiOF film 110 is exposed, a metal film formed in a subsequent process is easily peeled off from the SiOF film 110.
[0012]
Subsequently, as shown in FIG.₂A via hole 112 is opened in the film 111 and the SiOF film 110, a TiN glue layer 113 is grown on the bottom of the via hole 112, and the via hole 112 is filled with a tungsten plug 114.
If such a process is repeated twice, a two-layer wiring layer as shown in FIG. 12B is formed.
[0013]
[Problems to be solved by the invention]
By the way, in the wiring structure as shown in FIG. 12B, the SiOF film thickness in the high wiring density region is larger than that in the low wiring density region.₂Since the ratio of the film thickness increases, the following problem occurs.
That is, the horizontal wiring T₁The parasitic capacitance is reduced by the interposition of the SiOF film.₂Is mostly SiO₂Therefore, the parasitic capacitance between the wirings in the film thickness direction in this region becomes high. As a result, the effect of lowering the wiring capacitance by the SiOF film is diminished.
[0014]
  In contrast, SiO₂It is conceivable to use a SiOF film instead of the film 111. When the dielectric constant of the SiOF film is 3.5 or less, a TiN film as a glue layer is grown directly on the SiOF film, and the via hole is further filled. Tungsten (W)As you grow upTheir adhesion is weak at the interface between the SiOF film and the TiN film, and the tungsten film easily peels off from the SiOF film due to the strong film stress of tungsten. The decrease in adhesion between the SiOF film and the TiN film occurs because F and TiN in the SiOF film react at the interface.
[0015]
In addition, SiO on high-density wiring₂In order to reduce the ratio of the film, it is conceivable to increase the thickness of the SiOF film. However, this increases the aspect ratio of the via hole, which may cause a defect in the plug.
An object of the present invention is to provide a semiconductor device capable of reducing a capacitance between wirings in a film thickness direction in a region having a high wiring density and preventing peeling of a metal film on an interlayer insulating film having fluorine-containing silicon oxide, and its manufacture It is to provide a method.
[0016]
[Means for Solving the Problems]
(means)
As illustrated in FIGS. 3 and 4, the above-described problems include a step of forming the wiring 63 on the semiconductor substrate 61 and a step of covering the wiring 63 with a fluorine-containing silicon oxide film 64 having a dielectric constant of 3.5 or less. A step of growing an insulating film 65 of a material different from that of the fluorine-containing silicon oxide film 64 on the fluorine-containing silicon oxide film 64, and polishing is started from the surface of the insulating film 65 to Unlike the fluorine-containing silicon oxide film 64, the step of polishing and flattening the fluorine-containing silicon oxide film 64, the surface of the insulating film 65 and the fluorine-containing silicon oxide film 64 exposed by polishing, And a step of growing an insulating cap film 66 made of a material having a hygroscopicity lower than that of the fluorine-containing silicon oxide film 64. Resolve. In this case, the insulating film 65 is formed by growing silicon oxide. The insulating cap film 66 is formed by growing silicon oxide or silicon nitride. Further, before the insulating cap film 66 is formed, the fluorinated silicon oxide film 64 is annealed at a temperature of 300 ° C. or higher.
[0019]
As illustrated in FIG. 4B, the above-described problem is that the wiring 63 formed in each of the first wiring region 63a and the second wiring region 63b on the semiconductor substrate 61, and fluorine-containing covering the wiring 63 are included. The silicon oxide film 64, the first wiring region 63a covers the fluorine-containing silicon oxide film 64, and the fluorine-containing silicon film 64 is made of a different material, and the second wiring region 63b is the fluorine. Unlike the fluorine-containing silicon oxide film 64, which is formed on the silicon-containing silicon oxide film 64, is formed on the insulating film 65 in the first wiring region 63a, and is more hygroscopic than the fluorine-containing silicon oxide film 64. This problem is solved by a semiconductor device having an insulating cap film 66 made of a low material. In this case, the fluorine-containing silicon oxide film has a dielectric constant of 3.5 or less. The insulating film 65 is a silicon oxide film. The insulating cap film 66 is a silicon oxide film or a silicon nitride film.
[0020]
As illustrated in FIG. 5C, the above-described problem is caused by the wiring 63 formed in the first wiring region 63a and the second wiring region 63b on the semiconductor substrate 61, and the first wiring region. A first fluorine-containing silicon oxide film 64a covering the wiring 63 in the wiring region 63a and the second wiring region 63b; and the first wiring region 63a covers the first fluorine-containing silicon oxide film 64a and A second fluorine-containing silicon oxide film 65a having a fluorine content lower than that of the first fluorine-containing silicon oxide film 64a and the first wiring region 63a are formed on the second fluorine-containing silicon oxide film 65a. A moisture-proof insulating cap formed on the first fluorine-containing silicon oxide film 64a and made of a material different from that of the first and second fluorine-containing silicon oxide films 64a and 65a. This is solved by a semiconductor device including the film 66a. In this case, the first fluorine-containing silicon oxide film 64a has a dielectric constant of 3.5 or less. The second fluorine-containing silicon oxide film 65a has a dielectric constant of 3.6 or more. Further, the insulating cap film 66a is a silicon oxide film or a silicon nitride film.
[0021]
In the semiconductor device described above, an insulating base film is formed between the semiconductor substrate and the wiring. Further, another wiring is formed on the insulating cap film.
Next, the operation of the present invention will be described.
According to the present invention, a fluorine-containing silicon oxide film (SiOF film) that covers the wiring is made of another material, SiO.₂Then, the insulating film is polished and planarized until a part of the SiOF film is exposed, and then an insulating cap film for preventing moisture absorption is formed to cover the exposed SiOF film.
[0022]
Therefore, the SiOF film is prevented from absorbing moisture from the atmosphere by the insulating film and the insulating cap film. Further, since the metal film is not directly formed on the SiOF film constituting the interlayer insulating film, peeling of the metal film formed on the interlayer insulating film is prevented. Furthermore, since the insulating film on the SiOF film is thinned by polishing until the SiOF film is exposed, the ratio of the SiOF film thickness to the interlayer insulating film is increased to effectively reduce the parasitic capacitance between wirings. it can.
[0023]
Further, the interlayer insulating film was formed from a single layer or a plurality of SiOF films, and at least the uppermost layer thereof was flattened by polishing, and the insulating cap film for preventing moisture absorption was covered thereon.
Therefore, the insulating cap film prevents moisture absorption of the SiOF film from the atmosphere. In addition, since the metal film is not formed directly on the SiOF film constituting the interlayer insulating film, peeling of the metal film on the interlayer insulating film can be prevented.
[0024]
Further, when the SiOF film has a multilayer structure, the fluorine content of the uppermost SiOF film is reduced, so that absorption of moisture from the atmosphere is suppressed by the uppermost SiOF film. Further, by polishing the uppermost SiOF film, the thickness of the high dielectric constant SiOF film occupying the interlayer insulating film is reduced, so that the parasitic capacitance between the wirings can be effectively reduced.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
  Accordingly, embodiments of the present invention will be described below with reference to the drawings.
  Before explaining the formation of the multilayer wiring layer in the semiconductor device of the present invention, the outline of the configuration of the parallel plate type plasma CVD apparatus and ECR (EIectron Cyclotron Resonance) -CVD apparatus used for the growth of the interlayer insulating film of the present invention, and Of insulation film by the equipment ofFilm formationAn example of the conditions and the dielectric constant of the insulating film will be described.
[0026]
Parallel plate type plasma CVD equipment
FIG. 1 is a schematic view of a parallel plate type plasma CVD apparatus used in a semiconductor device manufacturing process.
In the parallel plate type plasma CVD apparatus, the inside of the sealed reaction chamber 1 is exhausted by a vacuum pump 3 via a vacuum pipe 2. The ultimate vacuum in the reaction chamber 1 due to the exhaust is, for example, 0.01 Torr. Inside the reaction chamber 1, a first electrode 4 for installing a semiconductor wafer W is attached, and a shower head 5 for ejecting a source gas to the semiconductor substrate W is disposed at a position facing the first electrode 4. ing. The shower head 5 functions as a second electrode, to which a high frequency power source 6 of 13.56 MHz, for example, is connected.
[0027]
In addition, heating means 7 for heating the semiconductor substrate W, for example, a lamp, is disposed in the reaction chamber 1 or under the first electrode 4.
In the reaction chamber 1, the raw material gas supply pipe 8, the first mass flow controller 9, and the first pipe 10 are used for C.₂F₆Cylinder 11 is connected and C₂F₆The flow rate of gas into the reaction chamber 1 is controlled by a mass flow controller 9.
[0028]
Further, the reaction chamber 1 is supplied with O through a source gas supply pipe 8, a second mass flow controller 12 and a second pipe 13.₂The cylinder 14 is connected and O₂The gas flow rate is controlled by the mass flow controller 12.
Further, a TEOS source 18 is connected to the reaction chamber 1 through a source gas supply pipe 8, a vaporizer 15, a liquid mass flow controller 16 and a liquid supply pipe 17.
[0029]
The TEOS source 18 includes a container 20 that stores the TEOS liquid 19 and a third pipe 22 that sends the compressed helium (He) gas from the helium source 21 to the container 20, and the TEOS liquid 19 in the container 20. A liquid supply pipe 17 is inserted into the pipe. When supplying the TEOS liquid 19 to the vaporizer 15, the pressure from 0.5 to 1.0 kg / cm from the helium source 21.²Then, the He gas is sent into the third pipe 22, and the TEOS liquid 19 is sent into the liquid supply pipe 17 by the pressure in the container 20. The supply amount of the TEOS liquid 19 is controlled by the liquid mass flow controller 16.
[0030]
The TEOS liquid 19 controlled by the liquid mass flow controller 16 is vaporized in the vaporizer 15 to become TEOS gas.
A He cylinder 25 is connected to the vaporizer 15 via a fourth pipe 23 and a third mass flow controller 24, and the amount of He gas introduced is controlled by the third mass flow controller 24. The He gas sent to the vaporizer 15 is sent into the reaction chamber 1 through the source gas supply pipe 8 together with the TEOS gas in the vaporizer 15. The He gas serves as a carrier gas for TEOS, and is used to stabilize the supply amount of TEOS gas.
[0031]
A heater 26 for preventing the liquefaction of the TEOS gas is wound around the raw material gas supply pipe 8 through which the TEOS gas flows. The raw material gas supply pipe 8 is heated to, for example, 100 ° C. by the heater 26.
A method of supplying the vaporized gas directly into the reaction chamber 1 without using a bubbler in this way is called direct injection. In the following description, the flow rate of the TEOS gas indicates a value not including the He gas.
[0032]
When the SiOF film is grown on the semiconductor substrate W by the parallel plate type plasma CVD apparatus described above, the COS is supplied simultaneously with the TEOS gas supply.₂F₆Gas and O₂Gas is supplied into the reaction chamber 1, and high frequency power is applied between the first electrode 4 and the shower head (second electrode) 5 by the high frequency power source 6, whereby plasma of each gas is generated in the reaction chamber 1. generate.
[0033]
In addition, SiO on the semiconductor substrate W₂In the case of forming a film, OOS is supplied simultaneously with the supply of TEOS gas.₂Gases are supplied into the reaction chamber 1, and high-frequency power is applied between the first electrode 4 and the shower head (second electrode) 5 by a high-frequency power source 6, so that plasma of those gases is generated in the reaction chamber 1. generate.
Next, an example of SiOF growth conditions is shown in Table 1, and SiOF₂Table 2 shows the growth conditions.
[0034]
[Table 1]

[0035]
[Table 2]

[0036]
The dielectric constant of the SiOF film grown under the conditions shown in Table 1 is 3.6, and the SiOF film grown under the conditions shown in Table 2 is used.₂The dielectric constant of the film was 4.2.
ECR-CVD equipment
FIG. 2 is a schematic view of an ECR-CVD apparatus according to the present invention.
The ECR-CVD apparatus has a plasma chamber 31 and a reaction chamber 32, and a microwave power source 33 is connected to the plasma chamber 31 via a microwave waveguide 34, and microwaves are transmitted from the microwave power source 33 to the plasma chamber 31. By introducing into the gas, the gas introduced into the plasma chamber 31 is excited and plasma is formed.
[0037]
In addition, a plasma density and energy in the reaction chamber 32 are amplified by generating a magnetic field in the reaction chamber 32 by a main solenoid coil (MSC) 35 disposed above the reaction chamber 32. The plasma density and plasma energy can be changed by the amount of current flowing through the main solenoid coil 35.
[0038]
In the plasma chamber 31, SiO 2₂Alternatively, an argon source 38 is connected via a first mass flow controller 36 and a first gas pipe 37 for SiOF film growth, and an oxygen source is further connected via a second mass flow controller 39 and a second gas pipe 40. 41 is connected. Further, the reaction chamber 32 includes SiO 2.₂For the film growth of the silicon source, the silicon source SiH is passed through the third mass flow controller 42 and the third gas pipe 43._FourA cylinder 44 is connected, and further a SiF as a fluorine source is passed through a fourth mass flow controller 45 and a fourth gas pipe 46 for growing a SiOF film._FourA cylinder 47 is connected.
[0039]
The first to fourth mass flow controllers 36, 39, 42, and 45 control the gas flow rate.
Furthermore, a plate 48 is disposed below the plasma chamber 31 in the reaction chamber 32, and an electrostatic chuck 49 for adsorbing the semiconductor substrate W is disposed thereon. A 13.56 MHz radio frequency (RF) power supply 50 is connected to the electrostatic chuck 49, and a potential is generated between the semiconductor wafer W and the plasma chamber 31 by application of the RF electrode 50. This potential accelerates Ar ions from the plasma chamber 31 and causes a sputtering phenomenon. Sputtering and source gas (SiF_Four, SiH_Four) Occurs in concert on the semiconductor substrate W, and an insulating film is embedded between the wirings on the narrow semiconductor substrate W, as will be described later. The electrostatic chuck 49 is heated to, for example, 200 ° C. by resistance heating, but the temperature during film formation by sputtering reaches 250 ° C.
[0040]
A sub-solenoid coil (SSC) 51 is disposed below the plate 48, and the sub-solenoid coil 51 serves to converge the plasma emanating from the plasma chamber 31 by a magnetic field. That is, the sub solenoid coil 51 has a function of changing the plasma shape according to the amount of current flowing therethrough.
When a symmetrical plasma is formed around the semiconductor wafer W, the film thickness distribution is improved and plasma damage to the semiconductor device can be reduced.
[0041]
Note that a turbomolecular pump 52 is connected to the reaction chamber 32, whereby the gas in the reaction chamber 32 is exhausted and decompressed.
Table 3 shows an example of conditions for performing SiOF growth using the ECR-CVD apparatus.₂An example of conditions for growth is shown in Table 4.
[0042]
[Table 3]

[0043]
[Table 4]

[0044]
Here, the dielectric constant of the SiOF film grown under the conditions shown in Table 3 is 3.5, and the SiOF film grown under the conditions shown in Table 4 is used.₂The dielectric constant of the film was 4.2.
Note that the growth of a film using an ECR-CVD apparatus has a higher ability to fill a high-density wiring layer than a case where a film is formed using a parallel plate type plasma CVD apparatus.
Next, a method for forming a wiring structure using the above-described apparatus will be described. Note that the film thickness shown below indicates the thickest film thickness portion on a wide wiring such as a pad unless a region is specified.
(First embodiment)
A first embodiment of the present invention is shown in FIGS.
[0045]
First, as shown in FIG. 3A, a parallel plate type plasma CVD apparatus is used to form SiO on a silicon substrate (semiconductor substrate) 61.₂A base insulating film 62 is grown to a thickness of 5000 mm. Subsequently, on the base insulating film 62, the thickness of the titanium (Ti) film is 300 mm, the thickness of the titanium nitride (TiN) film is 500 mm, the aluminum (Al) film is 6000 mm, the thickness of the TiN film is 500 mm, and the thickness of the Ti film is 300 mm. grow up. The five-layer metal film is patterned to form the first-layer wiring 63. In the formation region of the first-layer wiring 63, there are a high wiring density region 63a having a narrow wiring width and a narrow wiring interval, and a low wiring density region 63b on the contrary.
[0046]
Next, as shown in FIG. 3B, a first SiOF film 64 for covering the first-layer wiring 63 is grown to a thickness of 14,000 by using an ECR-CVD apparatus. When the ECR-CVD apparatus is used, the high wiring density region 63a is thin and the low wiring density region 63b is thick. The first SiOF film 64 is grown under the conditions shown in Table 3 above and has a dielectric constant of 3.5.
[0047]
According to the ECR-CVD apparatus, since the film grows with the etching effect by Ar ions between the lateral wirings, the space between the lateral wirings is completely buried. As a result, the film thickness of the first SiOF film 64 on the wiring is as thin as 6000 mm in the high wiring density region 63a and as thick as about 14000 mm in the low wiring density region 63b.
Next, as shown in FIG. 3 (c), the first SiO 2 film under the conditions shown in Table 2 using the parallel plate type plasma CVD apparatus described above.₂A film (insulating film) 65 is formed to a thickness of 7000 mm. Its first SiO₂The film 65 is grown to a substantially uniform thickness as a whole, but the upper and lower surfaces thereof reflect the unevenness of the SiOF film 64, so that the first SiO in the low wiring density region 63b is reflected.₂The upper surface of the film 65 is the first SiO in the other region.₂It exists in a position higher than the film 65.
[0048]
Second SiO₂The reason why the film 65 is grown using the parallel plate type plasma CVD apparatus is that the film grows faster than when the ECR-CVD apparatus is used.
Next, the first SiO₂The film 65 is polished by CMP, and as shown in FIG. 3D, an insulating film (first SiOF film 64 and first SiOF film on the first-layer wiring 63 is formed.₂The film 65) is flattened until it reaches 9000 mm from the upper surface of the wiring 63 of the first layer.
[0049]
When the first SiOF film 64 is exposed in the low wiring density region 63b, as shown in FIG.₂A first insulating cap film 66 is grown to a thickness of 1000 mm.
Next, as shown in FIG. 4B, the first SiOF film 64 and the first SiOF film 64₂The film 65 is patterned to open a via hole 67 by lithography, for example, on one wiring 63 in the high wiring density region 63a. Subsequently, titanium nitride (TiN) was grown as a glue layer 68 along the inner wall of the via hole 67 by sputtering, and then tungsten (W) serving as the plug 69 was grown by CVD. The glue layer 68 and the plug 69 are left in the via hole 67 by etch back. The via hole 67 is formed not only in the high density wiring region 63a but also in the low density wiring region 63b as shown in the figure.
[0050]
Thereafter, the steps of FIGS. 3A to 3D and FIGS. 4A and 4B are repeated once again to form the second-layer wiring structure.
That is, a second layer wiring 70 is grown on the first insulating cap film 66, a second SiOF film 71 covering the second layer wiring 70 is grown, and then the second SiOF film 71 is formed. Covering second SiO₂A film 72 is grown. After that, the second SiO₂The film 72 and the second SiOF film 71 are polished and planarized by CMP. Furthermore, in order to cover the second SiOF film 71 exposed by polishing, SiO₂A second insulating cap film 73 is grown. As a result, a cross section as shown in FIG.
[0051]
In such a multilayer wiring structure, the SiOF film and the insulating cap film function as interlayer insulation.
Although the formation of the two-layer structure wiring is completed as described above, the third and fourth layer wirings may be formed thereafter.
The first and second insulating cap films 66 and 73 described above are formed to prevent the first and second SiOF films 64 and 71 from being exposed to the atmosphere. If the first insulating cap film 66 is not grown and a part of the first SiOF film 64 is exposed to the atmosphere and then the contact hole 67 is formed and then the TiN film and the W film are grown, Due to the poor adhesion between the first SiOF film 64 and the TiN film, the TiN film is peeled off at the interface between the first SiOF film 64 and the TiN film.
[0052]
However, in this embodiment, the first and second insulating cap films 66 and 73 prevent moisture absorption of the first and second SiOF films 64 and 71 exposed by CMP. SiOF film and SiO₂Adhesion with the film is extremely high.
The first and second SiO₂Before forming the films (first and second cap films) 66 and 73, the first and second SiOF films 64 and 71 are heated at a temperature of 300 ° C. or higher in an annealing furnace (not shown), or the films When preheating is performed at a temperature of 300 ° C. or higher in the growth apparatus, an increase in dielectric constant due to moisture absorption of the first and second SiOF films 64 and 71 is suppressed. In this embodiment, the latter method was performed for 30 seconds.
(Second Embodiment)
A second embodiment of the present invention is shown in FIG.
[0053]
First, by a method similar to that described in the first embodiment, as shown in FIG.₂A base insulating film 62 is grown, and a first-layer wiring 63 is formed thereon. This first-layer wiring 63 has a high-density wiring region 63a and a low-density wiring region 63b. In this case, the growth conditions of the base insulating film 62 and the first-layer wiring 63 are the same as those in the first embodiment.
[0054]
Thereafter, a first SiOF film 64a having a dielectric constant of 3.5 is grown on the wiring 63 of the first layer to a thickness of 14000 mm by an ECR-CVD apparatus. In this case, the first SiOF film 64a on the wiring 63 grows as thin as 6000 cm in the high density wiring region 63a and as thick as 14000 cm in the low density wiring region 63b. Subsequently, under the conditions shown in Table 1, a second SiOF film 65a having a dielectric constant of 3.6 was grown to a thickness of 7000 mm using a parallel plate plasma CVD apparatus.
[0055]
Next, the first and second SiOF films 64a and 65a are polished and polished by CMP until the film thickness on the first-layer wiring 63 reaches 9000 mm.
Thereafter, SiO2 on the flattened first and second SiOF films 64a and 65a is formed.₂A first insulating cap film 66a is grown to a thickness of 1000 mm. The purpose of forming the first insulating cap 66a is to prevent moisture absorption of the first and second SiOF films 64a and 65a and to prevent peeling of the metal film, as in the first embodiment.
[0056]
Next, as shown in FIG. 5D, a via hole 67 is opened by lithography on the first-layer wiring 63 of the first and second SiOF films 64a and 65a and the first insulating cap film 66a. . Subsequently, titanium nitride (TiN) was formed as a glue layer 68 along the inner wall of the via hole 67 by sputtering, and then tungsten (W) serving as a plug 69 was grown by CVD. The glue layer 68 and the plug 69 are left in the via hole 67 by etch back.
[0057]
Thereafter, the steps from the wiring formation to the cap film formation are repeated once again to form a second-layer wiring structure. That is, a second-layer wiring 70 is grown on the first insulating cap film 66a, and a third SiOF film 71a covering the second-layer wiring 70 is further grown in the ECR-CVD apparatus. A fourth SiOF film 72a is grown thereon in a parallel plate plasma CVD apparatus. Thereafter, the third and fourth SiOF films 71a and 72a are polished and planarized by CMP, and then the second insulating film is used as a second cap film to cover the third and fourth SiOF films 71a and 72a. The conductive cap film 73a is grown.
[0058]
In the multilayer wiring structure as described above, the SiOF film and the insulating cap film function as interlayer insulation.
In the second embodiment, since the interlayer insulating film formed between the first and second wirings 63 and 70 is composed of the first and second SiOF films 64a and 65a, compared to the first embodiment. As a result, the dielectric constant is lowered and the parasitic capacitance between the wirings is reduced.
[0059]
Further, by reducing the fluorine content, the dielectric constant of the upper second SiOF film 65a serving as the interlayer insulating film is made higher than the dielectric constant of the lower first SiOF film 64a. Hygroscopicity from the atmosphere decreases.
The first and second SiOF films 64a and 65a themselves are liable to peel off from the metal. However, since the insulating cap film 66a is formed on the first and second SiOF films 64a and 65a, the second SiOF film is the same as in the first embodiment.₂The film 66a does not peel off the glue layer 68.
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS.
[0060]
First, a SiO2 film having a thickness of 5000 mm is measured by a parallel plate type plasma CVD apparatus.₂After forming the underlying insulating film 82 on the silicon substrate 81, a first-layer electrode 83 having the same multilayer structure as in the first embodiment is formed. In the formation region of the first-layer wiring 83, there are a high wiring density region 83a having a narrow wiring width and a narrow wiring interval and a low wiring density region 83b on the contrary.
[0061]
Subsequently, a first SiOF film 84 covering the first-layer electrode 83 and the base insulating film 82 is grown to a thickness of 21000 mm by an ECR-CVD apparatus under the conditions shown in Table 3.
Thereafter, in order to remove moisture absorbed by the first SiOF film 84, the first SiOF film 84 is heated at a temperature of 300 ° C. or higher in an annealing furnace, or at a temperature of 300 ° C. or higher in a film growth apparatus. Preheat. In this embodiment, the latter is performed for 30 seconds.
[0062]
Next, as shown in FIG. 6B, the first SiOF film 84 is polished by CMP and flattened until the thickness on the first-layer wiring 83 reaches 9000 mm.
After this, as shown in FIG.₂The insulating cap film 85 is grown to a thickness of 1000 mm under the conditions shown in Table 2 using a parallel plate plasma CVD apparatus, thereby preventing the first SiOF film 84 from absorbing moisture from the atmosphere and growing in the subsequent steps. Prevents peeling of the metal film.
[0063]
Next, a part of the first SiOF film 84 and the insulating cap film 85 is etched by photolithography to form a via hole 86 connected to the first layer wiring. Then, as shown in FIG. 7 (a), titanium nitride (TiN) was grown as a glue layer 87 along the inner wall of the via hole 86 by sputtering, and then tungsten (W) serving as a plug 88 was grown by CVD. The glue layer 87 and the plug 88 are left in the via hole 86 by etch back.
[0064]
Thereafter, the steps shown in FIGS. 6A to 6C are repeated once again to form a second-layer wiring structure. That is, a second-layer wiring 90 is grown on the first insulating cap film 85, a second SiOF film 91 covering the second-layer wiring 90 is grown, and then the second SiOF film 91 is grown. In order to cover the exposed second SiOF film 91 after polishing and planarizing by CMP₂A second insulating cap film 92 is grown. As a result, a cross-sectional structure as shown in FIG. 7B is obtained.
[0065]
Although the formation of the two-layer structure wiring is completed as described above, the third and fourth layer wirings may be formed after that to form a multilayer wiring structure.
According to the multilayer wiring structure configured as described above, the first-layer wiring 83 is covered with the SiOF film 84, and then the SiOF film 84 is polished and flattened. Since it is covered with the insulating cap film 85, the hygroscopicity is lowered, and the metal film formed on the interlayer insulating film is prevented from peeling off.
[0066]
In the above three embodiments, the insulating cap film is made of SiO.₂Formed from but Si_ThreeN_FourYou may form from.
Next, the improvement of the wiring capacity and operation speed of the above embodiment will be described.
Comparison of wiring capacity between the first to third embodiments and the prior art
In the samples for comparing the wiring capacities, all the configurations other than the material of the interlayer insulating film between the first layer wiring and the second layer wiring were made the same. Further, as a conventional technique, a semiconductor device formed by the two manufacturing methods shown in FIGS.
[0067]
First, the SiO shown in FIG.₂The wiring capacity of a sample having an interlayer insulating film consisting of only the above is investigated, and the capacity is determined as a reference capacity value C.₀It was. However, the first layer SiO in FIG.₂The film was grown under the conditions of Table 4 and the second layer of SiO₂The film was grown under the conditions in Table 2.
The wiring capacitance of the devices of the first to third embodiments and the conventional device shown in FIG.₀As a result of examining what value (wiring capacitance ratio) is taken with respect to the above, a result as shown in FIG. 8 (a) was obtained.
[0068]
In FIG. 8 (a), the reference capacity C₀The wiring capacity ratio is shown in the case where is set to 1. The smaller the value of the wiring capacity ratio is, the more effective the wiring capacity is reduced.
The capacity ratio of the second embodiment was the lowest value of 79%. Further, the capacity ratio of the first embodiment was low and 82%. Originally, it was predicted that the capacitance ratio of the third embodiment in which most of the interlayer insulating film between the first and second wiring layers is made of SiOF having a dielectric constant of 3.5 shows the lowest value. The measured value was 84%. The reason for this is that the first SiOF film 84 whose upper surface is exposed during the steps up to the step shown in FIG. 6C, that is, until the first SiOF film 84 is covered with the first insulating cap film 85, This is because the moisture contained therein was absorbed, and this was because the preheating performed before the growth of the first insulating cap film 85 was not sufficient.
[0069]
Moisture absorption lowers the reliability of high-density wiring with a narrow wiring width, and is therefore a concern for semiconductor devices manufactured with design rules of 0.25 μm and later. Therefore, as in the embodiment, the SiOF film that covers the wiring in the high-density wiring region is made SiO 2 until the cap film is formed.₂It is preferable to cover with a film or another SiOF film having a dielectric constant of 3.6 or more and low moisture absorption.
[0070]
The capacitance ratio between wirings in the case of manufacturing by the conventional method FIGS. 11 to 12 was 88%, which was higher than the others. The reason for this is that, as described in the prior art section, most of the interlayer insulating film is made of SiO.₂It is because it consists of. Such a decrease in capacity does not lead to an improvement in the operation speed of the device.
The outline of the shape of the first layer wiring and the second layer wiring in each of the samples of the first to third embodiments and the two prior art examples is as shown in FIG. The distance between them is 4500 mm. The height per layer of the wiring is 7600 mm. The distance in the film thickness direction between the first-layer wiring and the second-layer wiring, that is, the film thickness of the interlayer insulating film is 10,000 mm.
[0071]
A pad was connected to the first-layer wiring and the second-layer wiring, and a voltage was applied to the pad to measure the capacitance between the wirings.
Comparison of operation speed between the first to third embodiments and the prior art
Samples for comparing operation speeds were all the same except for the material of the interlayer insulating film between the first-layer wiring and the second-layer wiring. As a conventional technique, a semiconductor device having a multilayer wiring structure formed by the two manufacturing methods shown in FIGS.
[0072]
First, the SiO shown in FIG.₂The operating speed of a sample having an interlayer insulating film made of only the material is examined, and the operating speed is determined as the reference speed T₀It was.
Then, when the operating speeds of the devices of the first to third embodiments and the two conventional devices shown in FIGS. 10 (c) and 12 (b) were examined, as shown in FIG. 9 (a). Results were obtained.
[0073]
In FIG. 9 (a), the reference operating speed T in FIG.₀The ratio (operation speed ratio) of other materials with respect to is shown. The smaller the value of the operation speed ratio, the faster the operation speed. The operation speed ratio of the semiconductor device manufactured by the same method as in the second embodiment was the lowest, 86%. Subsequently, the speed ratio of the semiconductor device according to the first embodiment was 88%. The speed ratio of the semiconductor device according to the third embodiment was 89%, which was higher than that in the first and second embodiments. In other words, as described in the experimental results of the wiring capacitance, in the device formed in the third embodiment, the SiOF film is made of SiO2.₂It is considered that moisture absorption occurs before the film is capped and the wiring capacity is not sufficiently reduced. The operation speed ratio of the semiconductor device according to the conventional method of FIGS. 11 and 12 was not improved so much as 94%.
[0074]
From the above, it was found that the measurement result of the operation speed is correlated with the measurement result of the wiring capacitance.
As shown in FIG. 9 (b), the operation speed is measured by connecting the first and second wirings in the middle of a test circuit in which 200 transistors are connected in series. . As a result, the load of the wiring capacity of the test circuit changes, and if the wiring capacity is large, the operation speed becomes slow.
[0075]
【The invention's effect】
As described above, according to the present invention, after covering the wiring with a fluorine-containing silicon oxide film (SiOF film) with an insulating film such as SiO2, the insulating film is polished until a part of the SiOF film is exposed. SiO that covers the exposed SiOF film after planarization₂Since the insulating cap film for preventing moisture absorption is formed, the SiOF film prevents the moisture absorption from the atmosphere by the insulating film and prevents the metal film from peeling off from the low dielectric constant interlayer insulating film. Further, by polishing the insulating film immediately above the SiOF film, the ratio of the thickness of the SiOF film to the interlayer insulating film can be increased, and the parasitic capacitance between the wirings can be effectively reduced.
[0076]
Furthermore, one interlayer insulating film is formed from a single layer or a plurality of SiOF films, and at least the uppermost layer thereof is flattened by polishing and covered with an insulating cap film for preventing moisture absorption. The fluorine-containing silicon oxide film prevents moisture from being absorbed from the atmosphere by the insulating cap film, prevents the metal film from peeling off from the low dielectric constant interlayer insulating film, and further improves the polishing performance by polishing the SiOF film. The thickness of the SiOF film occupying the interlayer insulating film above the density wiring region is made substantially the same as that of the other regions, and the parasitic capacitance between the wirings can be effectively reduced.
[0077]
In addition, the fluorine content of the uppermost SiOF film among the multiple SiOF films has been reduced to increase its dielectric constant, thereby suppressing the hygroscopicity of the SiOF film before forming the moisture-proof insulating cap film. Thus, an increase in the dielectric constant of the SiOF film as the interlayer insulating film can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an example of a parallel plate type plasma CVD apparatus used in an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram showing an example of an ECR-CVD apparatus provided in an embodiment of the present invention.
FIG. 3 is a sectional view (No. 1) showing a step of manufacturing the wiring structure of the semiconductor device according to the first embodiment of the invention;
FIG. 4 is a cross-sectional view (part 2) illustrating the manufacturing process of the wiring structure of the semiconductor device according to the first embodiment of the present invention;
FIG. 5 is a cross-sectional view showing a manufacturing process of a wiring structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a sectional view (No. 1) showing a manufacturing step of a wiring structure of a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a sectional view (No. 2) showing the manufacturing process of the wiring structure of the semiconductor device according to the third embodiment of the present invention;
FIG. 8 (a) is a result of an experiment for comparing the magnitude of the wiring capacity between the sample of the wiring structure of the first to third embodiments of the present invention and the sample of two conventional examples; FIG. 8B is a diagram showing a common wiring structure of these samples.
FIG. 9A is a result of an experiment for comparing the operation speeds of the wiring structure sample of the first to third embodiments of the present invention and the two conventional samples. b) is a circuit diagram used for the test.
FIG. 10 is a cross-sectional view showing a manufacturing process of a wiring structure of a semiconductor device according to a first conventional example.
11 is a sectional view (No. 1) showing a manufacturing step of a wiring structure of a semiconductor device according to a second conventional example; FIG.
FIG. 12 is a sectional view (No. 2) showing a manufacturing step of a wiring structure of a semiconductor device according to a second conventional example;
[Explanation of symbols]
61 ... Silicon substrate (semiconductor substrate), 62 ... Base insulating film, 63 ... First-layer wiring, 63a ... High-density wiring region, 63b ... Low-density wiring region, 64 ... First SiOF film, 65 ... First insulation Film 66 ... first insulating cap film 64a ... first SiOF film 65a ... second SiOF film 66a ... first insulating cap film 67 ... via hole 68 ... glue layer 69 ... plug , 70 ... second layer wiring, 71 ... second SiOF film, 72 ... second insulating film, 73 ... second insulating cap film, 71a ... third SiOF film, 72a ... fourth SiOF film 73a ... second insulating cap film, 81 ... silicon substrate (semiconductor substrate), 82 ... underlying insulating film, 83 ... first layer wiring, 83a ... high density wiring region, 83b low density wiring region, 84 ... first SiOF film, 85 ... first insulating cap film, 86 ... via hole, 8 ... glue layer, 88 ... plug, 90 ... second layer of wiring 91 ... second SiOF film, 92 ... second insulating cap film.

Claims (10)

Forming a wiring on a semiconductor substrate;
Covering the wiring with a fluorine-containing silicon oxide film having a dielectric constant of 3.5 or less;
Growing an insulating film made of a material different from the fluorine-containing silicon oxide film on the fluorine-containing silicon oxide film;
Polishing the surface of the insulating film and polishing and planarizing the insulating film and the fluorine-containing silicon oxide film;
Unlike the fluorine-containing silicon oxide film, an insulating cap film made of a material that is less hygroscopic than the fluorine-containing silicon oxide film is formed on the surface of the insulating film and the fluorine-containing silicon oxide film exposed by polishing. And a step of growing the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film and the insulating cap film are formed by growing silicon oxide. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the fluorinated silicon oxide film is annealed at a temperature of 300 [deg.] C. or higher before forming the insulating cap film. Wiring formed in each of the first wiring region and the second wiring region on the semiconductor substrate;
A fluorine-containing silicon oxide film covering the wiring;
An insulating film that covers the fluorine-containing silicon oxide film in the first wiring region and is made of a material different from the fluorine-containing silicon film;
Unlike the fluorine-containing silicon oxide film, the fluorine-containing silicon oxide film is formed on the fluorine-containing silicon oxide film in the second wiring region, formed on the insulating film in the first wiring region. And an insulating cap film made of a material having a lower hygroscopic property. The semiconductor device according to claim 4, wherein the insulating film is a silicon oxide film. The semiconductor device according to claim 4, wherein the insulating cap film is a silicon oxide film or a silicon nitride film. Wiring formed in each of the first wiring region and the second wiring region on the semiconductor substrate;
A first fluorine-containing silicon oxide film covering the wiring of the first wiring region and the second wiring region;
A second fluorine-containing silicon oxide film covering the first fluorine-containing silicon oxide film in the first wiring region and having a fluorine content lower than that of the first fluorine-containing silicon oxide film;
Formed on the second fluorine-containing silicon oxide film in the first wiring region, formed on the first fluorine-containing silicon oxide film in the second wiring region, and the first and second Unlike the fluorine-containing silicon oxide film, the semiconductor device has an insulating cap film made of a material having a lower hygroscopic property than the first and second fluorine-containing silicon oxide films. The semiconductor device according to claim 7, wherein the first fluorine-containing silicon oxide film has a dielectric constant of 3.5 or less. The semiconductor device according to claim 7, wherein the second fluorine-containing silicon oxide film has a dielectric constant of 3.6 or more. The semiconductor device according to claim 7, wherein the insulating cap film is a silicon oxide film or a silicon nitride film.

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