JPS63164344A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63164344A
JPS63164344A JP30892386A JP30892386A JPS63164344A JP S63164344 A JPS63164344 A JP S63164344A JP 30892386 A JP30892386 A JP 30892386A JP 30892386 A JP30892386 A JP 30892386A JP S63164344 A JPS63164344 A JP S63164344A
Authority
JP
Japan
Prior art keywords
wiring
stress
protective film
silicon oxide
insulating protective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30892386A
Other languages
Japanese (ja)
Other versions
JPH0332214B2 (en
Inventor
Yasunobu Kodaira
小平 靖宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP30892386A priority Critical patent/JPS63164344A/en
Publication of JPS63164344A publication Critical patent/JPS63164344A/en
Publication of JPH0332214B2 publication Critical patent/JPH0332214B2/ja
Granted legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To inhibit the generation of voids in an electrode wiring, and to improve reliability by forming an insulating protective film having compressive stress, covering the side section of the electrode wiring and shaping an insulating protective film having tensile stress to coat an upper section. CONSTITUTION:A first silicon oxide film 11 having compressive stress is formed so as to coat an Al wiring 5 through a plasma CVD method or a sputtering method, and a photo-resist agent 5 is applied onto the first silicon oxide film 11 after the formation of the oxide film 11. The photo-resist agent 15 on the upper section of the Al wiring 5 and the first silicon oxide film 11 are removed through a reactive ion etching method, the photo-resist agent 15 left without being removed is gotten rid of, and a second silicon oxide film 13 having tensile stress is shaped onto the Al wiring 5 through the plasma CVD method, a low- pressure CVD method or a normal-pressure CVD method. Only compressive force works on the Al wiring 5, and the generation of voids due to stress migration is prevented.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) この発明は、絶縁保S!膜で被覆された電極配線の信頼
性を向上した半導体装置に関する。
[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention provides insulation protection S! The present invention relates to a semiconductor device with improved reliability of electrode wiring covered with a film.

(従来の技術) 近年、半導体装置の高集積化、微細化に伴ない、電極配
線例えばアルミニウム(AΩ)配線の幅は著しく狭くな
ってきている。このように、All配線幅が狭くなると
、従来から知られている所謂エレクトロマイグレーショ
ンに起因する不良が発生する。さらに、最近rはストレ
スマイグレーションと呼ばれるAΩ配線の周辺部からA
Ω配線に作用する応力により引き起こされる不良が注目
されはじめている。以下、このストレスマイグレーショ
ンについて、第3図及び第4図を用いて説明する。
(Prior Art) In recent years, as semiconductor devices have become highly integrated and miniaturized, the width of electrode wiring, such as aluminum (AΩ) wiring, has become significantly narrower. As described above, when the All wiring width becomes narrow, defects due to so-called electromigration, which is conventionally known, occur. Furthermore, recently r has been caused by AΩ from the periphery of the AΩ wiring, which is called stress migration.
Defects caused by stress acting on Ω wiring are beginning to attract attention. This stress migration will be explained below using FIGS. 3 and 4.

第3図及び第4図は、A9配線が絶縁保護膜で被覆され
た半導体装置の要部断面図である。両図においC1半導
体基板1上の絶縁膜3上に△交配線5が形成されている
。このへΩ配線5には、その表面を被覆するために薄膜
形成法の一つであるC V D (chemical 
 vapor  deposition)法により、絶
縁保護膜7が形成されている。
FIGS. 3 and 4 are sectional views of essential parts of a semiconductor device in which the A9 wiring is covered with an insulating protective film. In both figures, a Δ crossing line 5 is formed on the insulating film 3 on the C1 semiconductor substrate 1. This Ω wiring 5 is coated with C V D (chemical
The insulating protective film 7 is formed by a vapor deposition method.

この絶縁保護I8!7は、用いるCVD法により圧縮応
力を有する場合と、引張り応力を有する場合がある。第
3図は、絶縁保護膜7が圧縮応力を有する場合を示して
おり、第4図は、絶縁保護膜7が引張り応力を有する場
合を示している。
This insulation protection I8!7 may have compressive stress or tensile stress depending on the CVD method used. FIG. 3 shows the case where the insulating protective film 7 has compressive stress, and FIG. 4 shows the case where the insulating protective film 7 has tensile stress.

第3図において、絶縁保護膜7が圧縮応力を有する場合
には、AC配線5の上部に形成された絶縁膜i1膜7は
、All配線5に対して引張り力として作用し、AΩ配
lI25の側部に形成された絶縁膜Ig17は、AΩ配
線5に対して圧縮力として作用することになる。
In FIG. 3, when the insulating protective film 7 has compressive stress, the insulating film i1 film 7 formed on the top of the AC wiring 5 acts as a tensile force on the All wiring 5, and the AΩ wiring I125 The insulating film Ig17 formed on the side portion acts on the AΩ wiring 5 as a compressive force.

一方、第4図において、絶縁保護膜7が引張り応力を有
する場合には、A】配線5の上部に形成された絶縁保護
膜7は、A】配線5に対して圧縮力として作用し、An
配線5の側部に形成された絶縁保護膜7は、A1配線5
に対して引張り力として作用することになる。
On the other hand, in FIG. 4, when the insulating protective film 7 has tensile stress, the insulating protective film 7 formed on the upper part of the A] wiring 5 acts as a compressive force on the wiring 5, and
The insulating protective film 7 formed on the side of the wiring 5 is connected to the A1 wiring 5.
This will act as a tensile force on the

このように、An配線5を被覆するために形成された絶
縁保護FI7が、第3図に示すように圧縮応力を有する
場合にあっても、また、第4図に示すように引張り応力
を有する場合であっても、絶縁膜ff1g17は、An
配線5に対して点線で示す部分において引張り力として
作用することになり、この引張り力がストレスマイグレ
ーションの原因となる。
In this way, even if the insulation protection FI 7 formed to cover the An wiring 5 has compressive stress as shown in FIG. 3, it also has tensile stress as shown in FIG. Even if the insulating film ff1g17 is An
A tensile force acts on the wiring 5 at the portion indicated by the dotted line, and this tensile force causes stress migration.

(発明が解決しようとする問題点) 以上説明したように、All配線5を被覆する絶縁保護
膜7に内在する応力は、AQ配線5に対して引張り力と
して作用し、A9配線5にストレスマイグレーションを
引き起こす。したがって、このストレスマイグレーショ
ンににす、ボイド(亀裂)9が、第5図(A)及びその
v−■断面図である第5図(B)に示す如く、AΩ配線
5に発生する。そして、このボイド9が成長すると、△
Ω配線5は断線に至り、An配線5の開放不良を招くと
いう問題があった。
(Problems to be Solved by the Invention) As explained above, the stress inherent in the insulating protective film 7 covering the All wiring 5 acts as a tensile force on the AQ wiring 5, causing stress migration to the A9 wiring 5. cause. Therefore, due to this stress migration, voids (cracks) 9 are generated in the AΩ wiring 5, as shown in FIG. 5A and FIG. And when this void 9 grows, △
There was a problem in that the Ω wiring 5 was disconnected, leading to an open failure in the An wiring 5.

そこで、この発明は、上記に鑑みてなされたものであり
、その目的とするところは、電極配線に作用する引張り
力を緩和することにより、電極配線におけるボイドの発
生を抑制して、電極配線の信頼性を向上した半導体装置
を提供することにある。
The present invention has been made in view of the above, and its purpose is to suppress the generation of voids in the electrode wiring by relieving the tensile force acting on the electrode wiring. An object of the present invention is to provide a semiconductor device with improved reliability.

[発明の構成] (問題点を解決するための手段) 上記目的を達成するために、この発明は、半導体基板上
に形成された電極配線の側部を被覆するように圧縮応力
を有する絶縁保護膜を形成し、前記電極配線の上部を被
覆するように引張り応力を有する絶縁膜護膜を形成した
ことを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an insulating protection having compressive stress so as to cover the sides of electrode wiring formed on a semiconductor substrate. A film is formed, and an insulating film protective film having tensile stress is formed to cover the upper part of the electrode wiring.

(作用) この発明の半導体装置にあっては、電極配線の側部を被
覆するように形成された圧縮応力を有する絶縁保護膜及
び、電極配線の上部を被覆するように形成された引張り
応力を有する絶縁保護膜は、電極配線に対して圧縮力と
して作用する。
(Function) In the semiconductor device of the present invention, an insulating protective film having compressive stress is formed to cover the sides of the electrode wiring, and a tensile stress protecting film is formed to cover the upper part of the electrode wiring. The insulating protective film has a compressive force on the electrode wiring.

(実施例) 以下、図面を用いてこの発明の一実施例を説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例に係る半導体装置の要部断
面図である。なお、第3図及び第4図と同符号のものは
同一機能を有するものであり、そ゛の説明は省略する。
FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention. Components with the same reference numerals as in FIGS. 3 and 4 have the same functions, and their explanation will be omitted.

第1図において、半導体基板1上には絶縁113が形成
されており、この絶縁1113の上部にA9配線5が形
成されている。さらに、圧縮応力を有する第1のシリコ
ン酸化l1111が、絶縁113の上部におけるAΩ配
線5の間に、A9配線5を被覆する絶縁保護膜として形
成されている。また、引張り応力を有する第2のシリコ
ン酸化膜13が、A1配線3の上部にAn配線5を被覆
する絶縁保護膜として形成されている。
In FIG. 1, an insulation 113 is formed on the semiconductor substrate 1, and an A9 wiring 5 is formed on the insulation 1113. Further, a first silicon oxide l1111 having compressive stress is formed between the AΩ wirings 5 on the insulation 113 as an insulating protective film covering the A9 wirings 5. Further, a second silicon oxide film 13 having tensile stress is formed as an insulating protective film covering the An wiring 5 over the A1 wiring 3.

次に、このような構造の半導体装置の製造工程の一例を
、第2図(A)〜第2図(E)を用いて説明する。
Next, an example of a manufacturing process for a semiconductor device having such a structure will be described with reference to FIGS. 2(A) to 2(E).

まず、半導体基板1上に絶縁膜3を形成した後、絶縁膜
3上にA9配線5を形成する(第2図(A))。
First, the insulating film 3 is formed on the semiconductor substrate 1, and then the A9 wiring 5 is formed on the insulating film 3 (FIG. 2(A)).

次に、圧縮応力を有する第1のシリコン酸化膜11を、
プラズマCVD法あるいはスパッタ法によりAΩ配線5
を被覆するように形成、し、形成後、第1シリコン酸化
l!11の上にフォトレジスト剤15を塗布する(第2
図(B))。
Next, the first silicon oxide film 11 having compressive stress is
AΩ wiring 5 by plasma CVD method or sputtering method
After the formation, the first silicon oxide l! Apply photoresist agent 15 on top of 11 (second
Figure (B)).

フォトレジスト剤15を塗布した後、All配線5の上
部の7オトレジスト剤15及び第1シリコン酸化膜11
を、反応性イオンエツチング法によりエツチング処理し
て除去する(第2図(C))。
After applying the photoresist agent 15, the photoresist agent 15 and the first silicon oxide film 11 on the upper part of the All wiring 5 are applied.
is removed by etching using a reactive ion etching method (FIG. 2(C)).

次に、前記工程で除去されず残ったフォトレジスト剤1
5を除去する(第2図(D))。
Next, the remaining photoresist agent 1 that was not removed in the above step is
5 (Figure 2 (D)).

フォトレジスト剤15をすべて除去した後、引張り応力
を有する第2のシリコン酸化1113を、プラズマCv
D法、低圧CVD法あるいは常圧CVD法により、AΩ
配線5の上に形成する(第2図(E))。
After removing all the photoresist agent 15, the second silicon oxide 1113 having tensile stress is removed by plasma Cv
AΩ by D method, low pressure CVD method or normal pressure CVD method.
It is formed on the wiring 5 (FIG. 2(E)).

このような製造工程により、第1図に示す如く、AQ配
線5を被覆する絶縁保護膜として、圧縮応力を右する第
1のシリコン酸化膜11をA9配線5の間に形成し、引
張り応力を有する第2のシリコン酸化1113をAΩ配
線5の上部に形成すれば、AΩ配線5には圧縮力のみが
作用することになる。
Through this manufacturing process, as shown in FIG. 1, the first silicon oxide film 11, which acts as an insulating protective film covering the AQ wiring 5, is formed between the A9 wirings 5, which absorbs compressive stress, and reduces tensile stress. If the second silicon oxide 1113 having the above structure is formed on top of the AΩ wiring 5, only compressive force will act on the AΩ wiring 5.

したがって、Aρ配線5への引張り力を抑制することが
できる。
Therefore, the tensile force applied to the Aρ wiring 5 can be suppressed.

なお、この実施例にあっては、AQ配I!!5の絶縁保
護膜として、シリコン酸化膜11.13を用いたが、こ
れに限定されるものではなく、圧縮応力及び引張り応力
を有する絶縁膜であればよい。
In addition, in this embodiment, AQ distribution I! ! Although silicon oxide films 11 and 13 are used as the insulating protective film in No. 5, the present invention is not limited thereto, and any insulating film having compressive stress and tensile stress may be used.

また、このような絶縁保護膜の配置構造は、Aρの多層
配線においても適用することも可能であり、多層配線に
適用した場合には、上述した配置構造を得るための形成
工程は、積層されたへ〇配線の段差による断線を防止す
るための平坦化工程を含むために極めて好都合である。
Furthermore, such an arrangement structure of the insulating protective film can also be applied to multilayer wiring of Aρ, and when applied to multilayer wiring, the formation process for obtaining the above arrangement structure may be performed by stacking layers. Furthermore, it is extremely convenient because it includes a planarization process to prevent wire breakage due to level differences in the wiring.

[発明の効果] 以上説明したように、この発明によれば、圧縮応力を有
する絶縁保護膜を、電極配線の側部を被覆ツるように形
成し、引張り応力を有する絶縁保護膜を、電極配線の上
部を被覆するように形成したので、絶縁保護膜から電極
配線に作用する力は圧縮力となり、電極配線におけるボ
イドの発生を抑制することが可能となる。この結果、電
極配線の信頼性を向上した半導体装置を提供づることが
できる。
[Effects of the Invention] As explained above, according to the present invention, an insulating protective film having compressive stress is formed so as to cover the sides of the electrode wiring, and an insulating protective film having tensile stress is formed to cover the sides of the electrode wiring. Since it is formed to cover the upper part of the wiring, the force acting on the electrode wiring from the insulating protective film becomes a compressive force, making it possible to suppress the generation of voids in the electrode wiring. As a result, a semiconductor device with improved reliability of electrode wiring can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例に係る半導体装置の要部断
面図、第2図(A)〜第2図(E)は第1図の製造工程
を示す断面図、第3図及び第4図は絶縁保護膜により被
覆された電極配線を有する従来の半導体装置の要部断面
図、第5図(A)は電極配線におけるボイドを示す平面
図、第5図(B)は第5図(A>の断面図である。 (図面の主要な部分を表わす符号の説明)5・・・AΩ
配線
FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention, FIGS. 2(A) to 2(E) are sectional views showing the manufacturing process of FIG. 1, and FIGS. 4 is a cross-sectional view of a main part of a conventional semiconductor device having electrode wiring covered with an insulating protective film, FIG. 5(A) is a plan view showing voids in the electrode wiring, and FIG. (This is a cross-sectional view of A>. (Explanation of symbols representing main parts of the drawing) 5...AΩ
wiring

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された電極配線の側部を被覆するよ
うに圧縮応力を有する絶縁保護膜を形成し、前記電極配
線の上部を被覆するように引張り応力を有する絶縁保護
膜を形成したことを特徴とする半導体装置。
An insulating protective film having compressive stress is formed to cover the sides of the electrode wiring formed on the semiconductor substrate, and an insulating protective film having tensile stress is formed to cover the upper part of the electrode wiring. Characteristic semiconductor devices.
JP30892386A 1986-12-26 1986-12-26 Semiconductor device Granted JPS63164344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30892386A JPS63164344A (en) 1986-12-26 1986-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30892386A JPS63164344A (en) 1986-12-26 1986-12-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63164344A true JPS63164344A (en) 1988-07-07
JPH0332214B2 JPH0332214B2 (en) 1991-05-10

Family

ID=17986906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30892386A Granted JPS63164344A (en) 1986-12-26 1986-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63164344A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133131A (en) * 1989-10-18 1991-06-06 Mitsubishi Electric Corp Semiconductor device
JPH04213829A (en) * 1990-02-02 1992-08-04 Applied Materials Inc Two stem method forming oxide layer which does not contain voids on stepwise sur- face of semiconductor wafer
US5442223A (en) * 1990-10-17 1995-08-15 Nippondenso Co., Ltd. Semiconductor device with stress relief
JP2010511299A (en) * 2006-11-29 2010-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor device having a double liner capping layer interconnection structure and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57149752A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Structure of multilayer wiring

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57149752A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Structure of multilayer wiring

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133131A (en) * 1989-10-18 1991-06-06 Mitsubishi Electric Corp Semiconductor device
JPH04213829A (en) * 1990-02-02 1992-08-04 Applied Materials Inc Two stem method forming oxide layer which does not contain voids on stepwise sur- face of semiconductor wafer
US5442223A (en) * 1990-10-17 1995-08-15 Nippondenso Co., Ltd. Semiconductor device with stress relief
JP2010511299A (en) * 2006-11-29 2010-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor device having a double liner capping layer interconnection structure and method of manufacturing the same

Also Published As

Publication number Publication date
JPH0332214B2 (en) 1991-05-10

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