JPS5928358A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5928358A
JPS5928358A JP13868482A JP13868482A JPS5928358A JP S5928358 A JPS5928358 A JP S5928358A JP 13868482 A JP13868482 A JP 13868482A JP 13868482 A JP13868482 A JP 13868482A JP S5928358 A JPS5928358 A JP S5928358A
Authority
JP
Japan
Prior art keywords
film
etching
resist
insulating film
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13868482A
Other languages
Japanese (ja)
Other versions
JPH0427703B2 (en
Inventor
Katsuhiko Hieda
克彦 稗田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13868482A priority Critical patent/JPS5928358A/en
Publication of JPS5928358A publication Critical patent/JPS5928358A/en
Publication of JPH0427703B2 publication Critical patent/JPH0427703B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Abstract

PURPOSE:To contrive to change fine elements into high density and integration ones without contamination by a method wherein elements are isolated by one time photoetching, and an insulation film is buried flat into a field region by low temperature treatment. CONSTITUTION:After reactive ion etching is performed by applying a resist mask 13 on a thermal oxide film 12 of a P type Si substrate 11, resulting in the formation of a recess, an inversion prevention layer 14 is formed by ion implantation. A SiO2 15 is superposed by plasma CVD method and treated with buffer fluoric solution, and accordingly a V-groove 16 is formed in the periphery of the recess by the difference of etching speeds. A resist film 17 is coated, the surface flatted approximately is etched by reactive ion, etched at the same speed by selecting the conditions of heat-treating and etching the resist 17, and then the resist 17 is removed by exposing the projection film 15. When a CVD SiO2 18 is uniformly deposited, a resist 19 is superposed, and the substrate is exposed by likewise etching the flatted surface by reactive ion, the SiO2 15 and 16 is buried flat in the field part. In this constitution, contamination does not occur because of no use of Al or resist mask for forming the film 15, and accordingly the element characterististic is stabilized.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法に係り、特にフィールド
領域に比較的厚い絶縁膜を埋め込んで平坦構造を得る方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of embedding a relatively thick insulating film in a field region to obtain a flat structure.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来、半導体としてシリコンを用いた半導体装置、特に
MO8型半導体集積回路装置では寄生チャンネルによる
絶縁不良をなくシ、かつ寄生容量を小さくするために素
子間のいわゆるフィールド領域に厚い絶縁膜を形成する
方法として、選択酸化法が知られている、しかしながら
、この選択酸化法をますます微細化、高密度化が進む集
積回路の素子間分離法として用いるには、tλ 次のような問題があるため高集積化のNげとなる。第1
にフィールド酸化膜が鳥のくちばしくバースビーク)状
に食い込むことにより素子領域の寸法誤差が生じる。第
2に、フィールド酸化時に高温、長時間の熱処理(例え
ば1000℃5時間)を必要とするため既にドーグされ
ているフィールド領域の不純物が再拡散してしまい、素
子形成領域にまでしみ出すことによシ素子特性が劣化す
る。第3に、フィールド酸化膜の膜厚の約半分を半導体
基板に埋没する事が出来るが基板表面にはフィールド酸
化膜厚の約半分の段差が出来ることによ多金属配線のこ
の段差部での信頼性が著しく低下する。
Conventionally, in semiconductor devices using silicon as a semiconductor, especially MO8 type semiconductor integrated circuit devices, there has been a method of forming a thick insulating film in the so-called field region between elements in order to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance. However, when using this selective oxidation method as a method for isolating elements in integrated circuits that are becoming increasingly finer and denser, it is difficult to use the selective oxidation method due to the following problems: This will become a hindrance to integration. 1st
The field oxide film digs into the device in the shape of a bird's beak, causing dimensional errors in the device area. Second, because field oxidation requires high-temperature and long-time heat treatment (for example, 1000°C for 5 hours), impurities in the field region that have already been doped will be re-diffused and seep into the device formation region. Element characteristics deteriorate. Thirdly, although about half of the field oxide film thickness can be buried in the semiconductor substrate, a step of about half the field oxide film thickness is created on the substrate surface, which causes the multi-metal wiring to be buried at this step. Reliability is significantly reduced.

以上のような問題を解決するために、従来半導体装置の
製造において半導体基板のフィールド領域に凹部を形成
し、との凹部に比較的厚い絶縁膜を低温プロセスにより
埋め込んで、平坦構造を得る方法が用いられている。そ
の−例を第1図(a)〜(h)をもって以下に説明する
In order to solve the above-mentioned problems, a conventional method of manufacturing semiconductor devices is to form a recess in the field region of a semiconductor substrate and fill the recess with a relatively thick insulating film using a low-temperature process to obtain a flat structure. It is used. An example thereof will be explained below with reference to FIGS. 1(a) to (h).

第1図(&)に示すように、面方位(100)、比抵抗
5〜50QtrnのP型シリコン基板1を用意し、この
表面に300X程度の熱酸化膜2及び0.5μm程度の
Al膜3を順次形成する。次に同図(blに示すように
、通常の写真蝕刻工程により素子形成領域上をレジスト
膜4でおおう。同図(C)に示すように、レジスト膜4
をマスクにしてフィールド領域上のAJ膜3及び熱酸化
膜2を順次例えば反応性イオンエツチング技術を用いて
エツチングし、さらにレジスト膜4及びAI!膜3をマ
スクにして、例えばCF4ガスを用いた反応性イオンエ
ツチングによりフィールド領域を約0.8μmエツチン
グして凹部を形成し、さらにレジスト膜4、及びAJ膜
3をマスクにしてフィールド領域のシリコン基板中にイ
オン注入を行って反転防止層5を形成する。次に同図(
d)に示すように、表面全面に第1の絶縁膜として例え
ばプラズマCVD法によシリコン基板中(5to2膜)
6を約1.2μm堆積する。その後、例えば弗化’77
−ey二・ラム液で5tO2膜6を全面エツチングする
と、段差部側面の5i02膜のエツチング速度は平坦部
での5io2膜のエツチング速度より約20倍太きいた
め、同図(e)に示すように、5102膜6がフィール
ド領域の凹部と素子形成領域とに完全に分離され、凹部
周辺部にV字形の溝7が形成される。
As shown in FIG. 1 (&), a P-type silicon substrate 1 with a plane orientation (100) and a specific resistance of 5 to 50 Qtrn is prepared, and a thermal oxide film 2 of about 300X and an Al film of about 0.5 μm are coated on the surface. 3 are formed one after another. Next, as shown in FIG.
Using the AJ film 3 and the thermal oxide film 2 on the field region as a mask, the AJ film 3 and the thermal oxide film 2 are sequentially etched using, for example, a reactive ion etching technique, and then the resist film 4 and the AI! Using the film 3 as a mask, the field region is etched by about 0.8 μm by reactive ion etching using, for example, CF4 gas to form a recess. Furthermore, using the resist film 4 and the AJ film 3 as a mask, silicon in the field region is etched. The anti-inversion layer 5 is formed by ion implantation into the substrate. Next, the same figure (
As shown in d), a first insulating film is formed on the entire surface of the silicon substrate (5to2 film) by, for example, plasma CVD.
6 to a thickness of about 1.2 μm. After that, for example, fluoride '77
When the entire surface of the 5tO2 film 6 is etched with the -ey 2-lam solution, the etching rate of the 5i02 film on the side surface of the stepped portion is approximately 20 times greater than the etching rate of the 5io2 film on the flat portion, as shown in Figure (e). Then, the 5102 film 6 is completely separated into the recess in the field region and the element forming region, and a V-shaped groove 7 is formed around the recess.

その後例えば硫酸と過酸化水素水の混液によシウエハを
処理すると、エツチングマスクとして用いたAI膜3及
びレジスト膜4が除去され、これによフさらにその上の
5IO2膜6がす7トオフされ、結局同図(f)に示す
ように凹部に5i02膜6が埋ゆ込まれた形となる。次
に同図(g)に示すように、第2の絶縁膜として、例え
ばCVD 5to2膜8を例えば1.0μm均一に堆積
して7字形溝7を完全に埋め込み、その上にさらに流動
性物質膜として例えばレジスト膜9を塗布して表面を平
坦化する。そして全面を例えば反応性イオンエツチング
でエツチングしていく。ここで、反応性イオンエツチン
グの条件とレジスト膜9の熱処理時間を適当に選ぶこと
によシ、レジスト膜9と5to2膜8のエツチング速度
をほぼ同程度に選ぶ事ができる。このような条件で反応
性イオンエツチングを行い、レジスト膜9を完全にエツ
チングし、さらに素子形成領域上の半導体基板が露出す
るまで5IO2膜8をエツチングすると、同図(h)に
示すようにフィールド部に完全にSlO□M6.8が平
坦な構造で埋め込まれる。この後は図示しないが、通常
の素子形成工程により例えばMO8型半導体装置を形成
する。
Thereafter, when the wafer is treated with a mixture of sulfuric acid and hydrogen peroxide, the AI film 3 and resist film 4 used as an etching mask are removed, and the 5IO2 film 6 thereon is also removed. In the end, the 5i02 film 6 is embedded in the recess as shown in FIG. 2(f). Next, as shown in FIG. 7G, as a second insulating film, a CVD 5to2 film 8, for example, is deposited uniformly to a thickness of, for example, 1.0 μm to completely fill the figure 7 groove 7, and then a fluid material is further deposited on top of the CVD 5to2 film 8. For example, a resist film 9 is applied as a film to flatten the surface. Then, the entire surface is etched using, for example, reactive ion etching. By appropriately selecting the reactive ion etching conditions and the heat treatment time for the resist film 9, the etching rates of the resist film 9 and the 5to2 film 8 can be selected to be approximately the same. When reactive ion etching is performed under these conditions, the resist film 9 is completely etched, and the 5IO2 film 8 is further etched until the semiconductor substrate above the element formation region is exposed, resulting in a field pattern as shown in FIG. The area is completely filled with SlO□M6.8 in a flat structure. After this, although not shown, an MO8 type semiconductor device, for example, is formed by a normal element forming process.

しかしながら、このような従来の方法では、す7トオフ
加工を行うためにAl1膜及びレジスト膜を残したまま
第1の絶縁膜を堆積する必要が   □あり、従ってこ
の第1の絶縁膜を堆積する前にウ壬ハの前処理が出来な
い。通常、硫酸と過酸化水素水の混液、塩酸と過酸化水
素水と水の混液または希フ、酸等を用いて前処理を行う
が、このような前処理を行うとAl膜やレジスト膜が除
去されてしまうからである・。また、Al膜及びレジス
ト膜からのシリコン基板及び第1の絶縁膜への汚染を生
じ、素子特性を劣化させ製品の歩留りを著しく低下させ
るなど重大な問題があった。
However, in such a conventional method, it is necessary to deposit the first insulating film while leaving the Al1 film and the resist film in order to perform the step-off process. I can't do the pre-processing beforehand. Normally, pretreatment is performed using a mixture of sulfuric acid and hydrogen peroxide, a mixture of hydrochloric acid, hydrogen peroxide, and water, diluted fluoride, acid, etc., but such pretreatment may damage the Al film or resist film. This is because it will be removed. Further, there were serious problems such as contamination of the silicon substrate and first insulating film from the Al film and resist film, deteriorating device characteristics and significantly lowering product yield.

〔発明の目的〕[Purpose of the invention]

本発明は上記素子間分離法の欠点に鑑みなされたもので
、−回の写真食刻工程にょシ素子間分離を行ない、低温
プロセスでフィールド領域に平坦絶縁膜を埋め込む方法
であって、かつ素子特性を汚染などによシ劣化させるこ
となく、微細素子の高密度集積化を可能とした半導体装
置の製造方法を提供するものである。
The present invention was developed in view of the drawbacks of the above-mentioned device isolation method, and is a method of performing device isolation in two photolithography steps and embedding a flat insulating film in the field region in a low temperature process. The present invention provides a method for manufacturing a semiconductor device that enables high-density integration of fine elements without deteriorating the characteristics due to contamination or the like.

〔発明の概要〕[Summary of the invention]

本発明においてはまず、半導体基板のフィールド領域に
凹部を形成し、Al膜やレジスト膜を残すことなく第1
の絶縁膜を全面に堆積する。
In the present invention, first, a recess is formed in a field region of a semiconductor substrate, and a first recess is formed without leaving an Al film or a resist film.
Deposit an insulating film over the entire surface.

そしてこの第1の絶縁膜の段差部をエツチング除去し、
前記凹部の周辺に7字形の溝を形成する。その後表面全
面に溝を埋めて表面が平坦になるように流動性物質膜を
堆積し、この流動性物質膜及び前記第1の絶縁膜の少な
くとも一部をエツチングして素子形成領域上の第1の絶
縁膜を除去する。これにより、リフトオフ加工によらず
凹部にのみ第1の絶縁膜が埋め込まれた状態が得られる
。その後、前記流動性物質膜を除去した後、溝を埋める
ように表面全面に第2の絶縁膜を堆積して表面を平坦化
し、この第2の絶縁膜をエツチングして平坦構造でフィ
ールド絶縁膜が埋め込まれた状態で素子形成領域の基板
表面を露出させる。その後、通常良く用いられている方
法に従い素子形成領域上に所望の素子を形成するもので
ある。
Then, the step portion of this first insulating film is removed by etching,
A 7-shaped groove is formed around the recess. Thereafter, a fluid material film is deposited to fill the grooves over the entire surface so that the surface is flat, and at least a portion of the fluid material film and the first insulating film are etched to form the first insulating film on the element formation region. Remove the insulating film. As a result, a state in which the first insulating film is buried only in the recessed portions can be obtained without using lift-off processing. Thereafter, after removing the fluid material film, a second insulating film is deposited on the entire surface so as to fill the grooves to flatten the surface, and this second insulating film is etched to form a field insulating film with a flat structure. The surface of the substrate in the element formation region is exposed in a state where it is embedded. Thereafter, a desired element is formed on the element forming region according to a commonly used method.

〔発明の効果〕〔Effect of the invention〕

本発明の方法によれば、第1の絶縁膜を堆積する前に、
Al膜及びレジスト膜が残置されてい決され、第1の絶
縁膜を堆積する前に十分な前処理を行なうことが可能と
なシ、素子特性の劣化を防ぐことができた。また本発明
の方法によれば、凹部のみに第1の絶縁膜を埋め込むの
にAl膜及びレジスト膜を使用しないので、これらの材
料に起因する汚染がなくなシ、これによシ素子特性の低
下はほとんどみられなくな9製品の歩留シが著しく向上
した。
According to the method of the present invention, before depositing the first insulating film,
Since the Al film and the resist film were left behind, sufficient pretreatment could be performed before depositing the first insulating film, and deterioration of device characteristics could be prevented. Further, according to the method of the present invention, since an Al film and a resist film are not used to fill only the recessed portion with the first insulating film, there is no contamination caused by these materials, and this improves the device characteristics. There was almost no decrease, and the yield of 9 products was significantly improved.

〔発明の実施例〕 以下本発明をMO8型半導体装置に適用した実施例につ
き図面を参照して説明する。
[Embodiments of the Invention] Hereinafter, embodiments in which the present invention is applied to an MO8 type semiconductor device will be described with reference to the drawings.

実施例1 第2図(a)に示すように、面方位(100)、比抵抗
5〜500mのP型シリコン基板11を用意し、この表
面に300X程度の熱酸化膜12を形成する。次に同図
(b)に示すように、通常の写真蝕刻工程により素子形
成領域上をレジスト膜13でおおう。次に同図(e)に
示すように、レジスト膜13をマスクにして、フィール
)’領域上の熱酸化膜12を例えば反応性イオンエツチ
ング技術を用いてエツチングし、さらにレジスト膜13
及び熱酸化膜12をマスクにして、例えばcF’4ガス
を用いた反応性イオンエツチングによシフイールド部を
約0.8μmエツチングして凹部を形成する。次に同図
(d)に示すように、レジスト膜13及び熱酸化膜12
をマスクにしてフィールド部シリコン基板中にフィ、−
ルドイ:オン注入を行って反転防止層14を形成する。
Example 1 As shown in FIG. 2(a), a P-type silicon substrate 11 with a surface orientation (100) and a resistivity of 5 to 500 m is prepared, and a thermal oxide film 12 of about 300X is formed on its surface. Next, as shown in FIG. 4B, the element forming area is covered with a resist film 13 by a normal photolithography process. Next, as shown in FIG. 3(e), using the resist film 13 as a mask, the thermal oxide film 12 on the field area is etched using, for example, a reactive ion etching technique, and then the resist film 13 is etched using a reactive ion etching technique.
Then, using the thermal oxide film 12 as a mask, the shift field portion is etched by about 0.8 μm by reactive ion etching using, for example, cF'4 gas to form a recess. Next, as shown in FIG. 2(d), the resist film 13 and the thermal oxide film 12
Using the mask as a mask, fill the field part silicon substrate with -
The anti-inversion layer 14 is formed by performing LDID: ON implantation.

次にレジスト膜13を除去した後、同図(e)に示すよ
うに、表面全面に第1の絶縁膜として例えばプラズマC
VD法によシシリコン酸化膜(SIO2膜)15を約1
.2μm堆積する。この膜の堆積前には、シリコン基板
表面全面を十分に清浄する。5102膜15を堆積後、
例えば弗化アンモニウム等の緩衝弗酸液で5102膜1
5を全面エツチングすると、段差部側面の8102膜の
エツチング速度は平坦部での8102膜のエツチング速
度より約20倍太きいため、同図(f)に示すように5
102膜15がフィールド領域の凹部と素子形成領域と
に完全に分離され、凹部周辺にV字型の溝16が形成さ
れる。次に同図(glに示すように、溝を埋めて、表こ
で、レジスト膜17を塗布した場合、凸部の5to2膜
15上ではレジスト膜17は薄く、凹部の5tO2膜1
5上ではレジスト膜17は厚く塗布されており表面はほ
ぼ平坦となっている。次に同図(貝に示すように、全面
を例えば反応性イオンエツチングでエツチングしていく
。ここで、反応性イオンエツチングの条件と、レジスト
膜11の熱処理時間を適当に選ぶことによジ、レジスト
膜17と5IO2膜15のエツチング速度を鐙ぼ同程度
に選ぶことができる。このような条件で反応性イオンエ
ツチングを行い、レゾスト塗布膜厚のほぼ半分稈度工、
チングした所でエツチングを止める。このエツチングで
は、多少のオーバーエツチング、あるいはアンダーエツ
チングがあってもよい。要は、凸部のSlO□膜16が
露出しており、凹部の5I02膜15がレジ次に同図(
1)に示すように、例えば弗化アンモニウム液で全面エ
ツチングすると露出した凸部の5IO2膜15及び熱酸
化膜12が除去され、この後レジスト膜17を除去する
と、凹部にSio2膜15が埋め込まれた形となる。次
に同図(j)に示すように、第2の絶縁膜として、CV
D法またはスパッタ法による5IO2膜18を例えば1
.0μm均一に堆積してV字溝16を完全に埋め込み、
その上にさらに流動性物質膜として例えばレジスト膜1
9を塗布して表面を平坦化する。そして′、全面を例え
ば反応性イオンエツチングでエツチングしていく。ここ
でも、反応性イオンエツチングの条件と、レジスト膜1
9の熱処理時間を適当に選ぶ事によシ、レジスト膜19
とS tO2膜18のエツチング速度をはは同程度に選
ぶ事ができる。このような条件で反応性イオンエツチン
グを行い、レジストM19を完全にエツチングし、さら
に素子形成領域上の半導体基板が露出するまでSlO□
膜18全エツチング速度ト、同図(klに示すようにフ
ィールド部に完全に5102膜15 、18が平坦な構
造で埋め込まれる。
Next, after removing the resist film 13, as shown in FIG.
Silicon oxide film (SIO2 film) 15 is deposited by about 1 by VD method.
.. Deposit 2 μm. Before depositing this film, the entire surface of the silicon substrate is thoroughly cleaned. After depositing the 5102 film 15,
For example, 5102 membrane 1 with a buffered hydrofluoric acid solution such as ammonium fluoride.
When the entire surface of 5 is etched, the etching speed of the 8102 film on the side surface of the stepped portion is approximately 20 times greater than the etching speed of the 8102 film on the flat part, so that
The 102 film 15 is completely separated into a recess in the field region and an element forming region, and a V-shaped groove 16 is formed around the recess. Next, as shown in FIG.
5, the resist film 17 is thickly applied and the surface is almost flat. Next, as shown in FIG. The etching speed of the resist film 17 and the 5IO2 film 15 can be selected to be approximately the same. Under these conditions, reactive ion etching is performed to remove approximately half the thickness of the resist coating film.
Stop etching at the point where it is etched. This etching may include some overetching or underetching. The point is that the SlO□ film 16 in the convex part is exposed, and the 5I02 film 15 in the concave part is exposed as shown in the same figure (
As shown in 1), for example, when the entire surface is etched with an ammonium fluoride solution, the exposed convex portions of the 5IO2 film 15 and thermal oxide film 12 are removed, and when the resist film 17 is then removed, the Sio2 film 15 is buried in the concave portions. It becomes a shape. Next, as shown in (j) of the same figure, CV
For example, the 5IO2 film 18 formed by the D method or the sputtering method is
.. Completely fill the V-shaped groove 16 by depositing 0 μm uniformly,
On top of that, for example, a resist film 1 is formed as a fluid material film.
9 to flatten the surface. Then, the entire surface is etched using, for example, reactive ion etching. Here again, the conditions of reactive ion etching and the resist film 1
By appropriately selecting the heat treatment time in step 9, the resist film 19
The etching rate of the StO2 film 18 can be selected to be approximately the same. Reactive ion etching is performed under these conditions to completely etch the resist M19, and furthermore, the SlO□ is etched until the semiconductor substrate above the element formation region is exposed.
When the total etching rate of the film 18 is increased, the 5102 films 15 and 18 are completely embedded in the field portion in a flat structure as shown in the figure (kl).

この後は図示しないが、通常の素子形成工程によp M
O8型半導体装置を形成する。
After this, although not shown in the drawings, p M
An O8 type semiconductor device is formed.

この実施例によれば、第1の絶縁膜を堆積する前にウェ
ハ前処理を十分に行なうことが出来、素子特性の劣化を
防ぐことができた。しかもこの実施例によれば、凹部の
みに第1の絶縁膜を埋め込むのにAl膜及びレジスト膜
を使用しないので、それらによる汚染がなくなりこれに
より素子特性は安定し、製品の歩留シが著しく向上した
According to this example, the wafer could be sufficiently pretreated before depositing the first insulating film, and deterioration of device characteristics could be prevented. Moreover, according to this embodiment, since an Al film and a resist film are not used to fill the first insulating film only in the concave portion, there is no contamination caused by them, and as a result, the device characteristics are stabilized, and the yield rate of the product is significantly reduced. Improved.

実施例2 第3図(alに示すように比抵抗5〜50Ω口のP型シ
リコン基板21を用意し、その表面に例えば300X程
度の熱酸化膜22を介して1000芙程度のシリコン窒
化膜23を形成する。次に同図(b)に示すように通常
の写真蝕刻工程によ多素子形成領域上にニレジスト膜2
4を形成し、これをマスクにして、例えば反応性イオン
エツチング技術を用して、同図(c)に示すようにシリ
コン窒化膜23、熱酸化膜22、及び半導体基板21の
一部をエツチングして凹部を形成する。さらに同図(d
)に示すようにフィールド領域にフィールドイオン注入
を行い、反転防止層25を形成する。次にレノスト膜2
4を除去後、前処理(例えば硫酸と過酸化水素水の混液
によるウェハの処理及び塩酸と過酸化水素水と水の混液
によるウェハの処理及び希フッ酸によるウェハの処理)
を十分に行ない、ウェハを清浄化して、同図+e+に示
すように第1の絶縁膜として例えばプラズマCVD法に
よi) 5i02膜26を凹部段差より厚く半導体基板
表面全面に堆積する。その後例えば弗化アンモニウム液
でSiO2膜26全26チングする。このとき、前述の
ように段差部側面での5IO2膜26のエツチング速度
は平坦部でのエツチング速度より約20倍はやいため、
同図(f)に示すように5102膜がフィールド領域の
凹部と素子形成領域とに完全に分離され、凹部周辺にV
字溝27が形成される。その後、実施例1と同様、同図
(g)のようにレジスト膜28を堆積し素子形成領域上
に残置された5to2膜26が露出するまで例えば反応
性イオンエツチングでエツチングを行ない、同図(h)
のように5lo2膜26を露出させる。その後、例えば
弗化アンモニウム液で8102膜26をエツチングする
。このとき、凹部の5102膜26はレジスト膜28で
覆われているのでエツチング除去されない。この弗化ア
ンモニウム液での8102膜26のエツチングは、シリ
コン窒化膜23の表面で止まる。この後レジスト膜28
を除去すると、同図(1) K示すようになる。その後
、同図(jlに示すように、CVDによる5IO2膜2
9、更にレジスト膜30を堆積し、これらを均一にエツ
チングして同図(k)に示すように素子形成領域のシリ
コン窒化膜23の表面を露出させる。次に、例えばSt
O□膜26.29に対して、シリコン窒化膜23の工、
チング比が十分大きくとれる例えばCF4ガスを含むグ
ラズマエ、チング法によシエッチングすると、同図(4
)に示すようにシリコン窒化膜23のみを除去できる。
Embodiment 2 As shown in FIG. 3 (al), a P-type silicon substrate 21 with a specific resistance of 5 to 50 Ω is prepared, and a silicon nitride film 23 of about 1000× is formed on its surface via a thermal oxide film 22 of about 300×, for example. Next, as shown in FIG.
4, and using this as a mask, the silicon nitride film 23, thermal oxide film 22, and part of the semiconductor substrate 21 are etched using, for example, reactive ion etching technology, as shown in FIG. to form a recess. Furthermore, the same figure (d
), field ion implantation is performed in the field region to form an anti-inversion layer 25. Next, Lenost membrane 2
After removing 4, pre-treatment (for example, wafer treatment with a mixture of sulfuric acid and hydrogen peroxide, treatment of the wafer with a mixture of hydrochloric acid, hydrogen peroxide, and water, and treatment of the wafer with dilute hydrofluoric acid)
After thoroughly cleaning the wafer, as shown in +e+ in the same figure, a 5i02 film 26 is deposited as a first insulating film by, for example, plasma CVD, on the entire surface of the semiconductor substrate to be thicker than the steps of the recesses. Thereafter, the entire SiO2 film 26 is etched using, for example, an ammonium fluoride solution. At this time, as mentioned above, the etching speed of the 5IO2 film 26 on the side surface of the stepped portion is approximately 20 times faster than the etching speed on the flat portion.
As shown in (f) of the same figure, the 5102 film is completely separated into the recess in the field region and the element formation region, and the V
A groove 27 is formed. Thereafter, in the same manner as in Example 1, a resist film 28 is deposited as shown in FIG. 2(g), and etched by, for example, reactive ion etching until the 5to2 film 26 left on the element formation region is exposed. h)
The 5lo2 film 26 is exposed as shown in FIG. Thereafter, the 8102 film 26 is etched using, for example, an ammonium fluoride solution. At this time, the 5102 film 26 in the recessed portion is covered with the resist film 28 and is therefore not removed by etching. Etching of the 8102 film 26 with this ammonium fluoride solution stops at the surface of the silicon nitride film 23. After this, the resist film 28
If you remove , it becomes as shown in (1) K in the same figure. After that, as shown in the same figure (jl), the 5IO2 film 2 was formed by CVD.
9. A resist film 30 is further deposited and etched uniformly to expose the surface of the silicon nitride film 23 in the element formation region, as shown in FIG. 9(k). Next, for example, St
For the O□ film 26 and 29, the silicon nitride film 23 is processed,
For example, when etching is performed using the ching method for glasmae containing CF4 gas, where the etch ratio is sufficiently large, the same figure (4) is obtained.
), only the silicon nitride film 23 can be removed.

次に同図(−に示すように例えば弗化アンモニウム液に
よりS i02膜26゜29及び熱酸化膜22を均一エ
ツチングして素子形成領域の基板表面を露出させる。
Next, as shown in FIG.

本実施例2の方法によれば、実施例1と同様の効果が得
られる他、さらに、シリコン窒化膜23を設けたことに
より素子形成領域よりもフィールド領域の5i02膜を
厚く形成出来、素子形成領域のシリコン基板のニップが
露出することによる素子特性の劣化を防ぐことが出来、
製品の歩留りが著しく向上した。
According to the method of Example 2, the same effects as in Example 1 can be obtained, and in addition, by providing the silicon nitride film 23, the 5i02 film in the field region can be formed thicker than in the element formation region. It is possible to prevent deterioration of device characteristics due to exposure of the nip of the silicon substrate in the area.
Product yield has significantly improved.

なお以上の実施例において、最初に凹部に埋め込む第1
の絶縁膜としてCVD法による5i02膜を用いたのは
、5102膜をエツチングする場合、段差部でのエツチ
ング速度が平坦部でのエツチング速度に比べて十分大き
い事を利用するためで、このような性質はプラズマ51
02に限らずスパッタ法によって形成した5i02膜更
に同様の方法による81.N4 M −? PSG膜に
おいてもみられ、このような膜が本発明方法において第
1の絶縁膜として使用できる事は当然でおる。またこの
発明はMO8型半導体装置に限らず、バイポーラ型半導
体装置での素子間分離にも適用できる事はもちろんであ
る。
Note that in the above embodiments, the first
The reason why we used the 5i02 film produced by the CVD method as the insulating film is to take advantage of the fact that when etching the 5102 film, the etching speed at the step part is sufficiently higher than that at the flat part. The property is plasma 51
02, 5i02 film formed by sputtering method, and 81.02 film formed by a similar method. N4 M-? This is also seen in PSG films, and it is natural that such a film can be used as the first insulating film in the method of the present invention. Further, the present invention is of course applicable not only to MO8 type semiconductor devices but also to isolation between elements in bipolar type semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(hlは、従来の半導体装置の製造工程
を説明するための断面図、第2図(a)〜(k)及び第
3図(a)〜(→は、それぞれこの発明の実施例の製造
工程を示す断面図である。 11 * 21・・・シリコン基板、12.22・・・
熱酸化膜、13.24・・・レジスト膜、14.25・
・・反転防止層、15.26・・・プラズマCvDSI
O2膜(第1の絶縁膜)、16.27・・・7字溝、1
7.28・ レジスト膜、11#y 29・・・CVD
5 i O2膜(第2の絶縁膜)、19.30・・・レ
ジスト膜(第2の絶縁膜)、23・・・シリコン窒化膜
。 第1図 第1図 を 第2図 第2図 第2図 83図 第3図 第3図 =20− 第3J!1
Figures 1(a) to (hl) are cross-sectional views for explaining the manufacturing process of conventional semiconductor devices, Figures 2(a) to (k), and Figures 3(a) to (→, respectively) It is a sectional view showing a manufacturing process of an example of the invention. 11*21...Silicon substrate, 12.22...
Thermal oxide film, 13.24... Resist film, 14.25.
・・Inversion prevention layer, 15.26 ・・Plasma CvDSI
O2 film (first insulating film), 16.27...7-shaped groove, 1
7.28・Resist film, 11#y 29...CVD
5 i O2 film (second insulating film), 19.30... resist film (second insulating film), 23... silicon nitride film. Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 83 Figure 3 Figure 3 = 20- 3J! 1

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板のフィールド領域に凹部を形成する工
程と、この凹部が形成された基板全面に段差部でのエツ
チング速度が平坦部でのそれよシ大きい第1の絶縁膜を
堆積する工程と、仁の第1の絶縁膜の段差部をエツチン
グ除去することにより前記凹部の周辺に溝を形成する工
程と、この溝を埋めて表面が平坦になるように全面に流
動性物質膜を堆積する工程と、この流動性膜及び前記第
1’Q絶縁膜の少なくとも一部をエツチングして素子形
成領域上の第1の絶縁膜表面を露出する工程と、前記流
動性物質膜をマスクとして素子形成領域上の前記第1の
絶縁膜をエツチング除去する工程と、前記流動性物質膜
を除去し、前記、溝を埋めるように全面に第2の絶縁膜
を堆積する工程と、この第2の絶縁膜を表面が平坦にな
るようにエツチングして素子形成領域の基板表面を露出
させる工程と、露出した基板に所望の素子を形成する工
程とを備えたことを特徴とする半導体装置の製造方法。
(1) A step of forming a recess in the field region of a semiconductor substrate, and a step of depositing a first insulating film on the entire surface of the substrate in which the recess is formed, the etching rate of which is higher in the stepped portion than in the flat portion. , forming a groove around the recess by etching away the stepped portion of the first insulating film, and depositing a fluid material film over the entire surface to fill the groove and make the surface flat. a step of etching at least a portion of the fluid film and the first Q insulating film to expose the surface of the first insulating film on the element forming region; and forming an element using the fluid material film as a mask. a step of etching away the first insulating film on the region; a step of removing the fluid material film and depositing a second insulating film over the entire surface so as to fill the groove; A method for manufacturing a semiconductor device, comprising the steps of: exposing a substrate surface in an element formation region by etching a film so that the surface is flat; and forming a desired element on the exposed substrate.
(2)前記第1の絶縁膜はプラズマCVD法またはスパ
ッタ法による5IO2膜、SI3N4膜またはPSG膜
であシ、その段差部をエツチングする方法は緩衝弗酸液
によるエツチング法である特許請求の範囲第1項記載の
半導体装置の製造方法。
(2) The first insulating film is a 5IO2 film, a SI3N4 film, or a PSG film formed by a plasma CVD method or a sputtering method, and the method for etching the stepped portion is an etching method using a buffered hydrofluoric acid solution. 2. A method for manufacturing a semiconductor device according to item 1.
(3)前記第2の絶縁膜は、CVD法またはスフ4ツタ
法による5IO2膜とその上に表面が平坦になるように
形成された流動性物質膜からなシ、この第2の絶縁膜を
エツチングする方法は、上記8102膜と流動性物質膜
に対してエツチング速度が等しい反応性イオンエツチン
グ法である特許請求の範囲第1項記載の半導体装置の製
造方法。
(3) The second insulating film is composed of a 5IO2 film formed by the CVD method or the Sufu 4 Tsuta method and a fluid material film formed thereon so that the surface is flat. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching method is a reactive ion etching method in which the etching rate is equal for the 8102 film and the fluid material film.
JP13868482A 1982-08-10 1982-08-10 Manufacture of semiconductor device Granted JPS5928358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13868482A JPS5928358A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13868482A JPS5928358A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5928358A true JPS5928358A (en) 1984-02-15
JPH0427703B2 JPH0427703B2 (en) 1992-05-12

Family

ID=15227684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13868482A Granted JPS5928358A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5928358A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984548A (en) * 1982-11-08 1984-05-16 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture
JPS61104626A (en) * 1984-10-29 1986-05-22 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS6224627A (en) * 1985-07-25 1987-02-02 Sony Corp Dry etching method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363871A (en) * 1976-11-18 1978-06-07 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5791537A (en) * 1980-11-29 1982-06-07 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363871A (en) * 1976-11-18 1978-06-07 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5791537A (en) * 1980-11-29 1982-06-07 Toshiba Corp Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984548A (en) * 1982-11-08 1984-05-16 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture
JPH0586655B2 (en) * 1982-11-08 1993-12-13 Nippon Telegraph & Telephone
JPS61104626A (en) * 1984-10-29 1986-05-22 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS6224627A (en) * 1985-07-25 1987-02-02 Sony Corp Dry etching method

Also Published As

Publication number Publication date
JPH0427703B2 (en) 1992-05-12

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