JPH0427703B2 - - Google Patents
Info
- Publication number
- JPH0427703B2 JPH0427703B2 JP57138684A JP13868482A JPH0427703B2 JP H0427703 B2 JPH0427703 B2 JP H0427703B2 JP 57138684 A JP57138684 A JP 57138684A JP 13868482 A JP13868482 A JP 13868482A JP H0427703 B2 JPH0427703 B2 JP H0427703B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- insulating film
- sio
- fluid material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 238000001020 plasma etching Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 239000012530 fluid Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 238000002294 plasma sputter deposition Methods 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 6
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に係り、特にフ
イールド領域に比較的厚い絶縁膜を埋め込んで平
坦構造を得る方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of embedding a relatively thick insulating film in a field region to obtain a flat structure.
従来、半導体としてシリコンを用いた半導体装
置、特にMOS型半導体集積回路装置では寄生チ
ヤンネルによる絶縁不良をなくし、かつ寄生容量
を小さくするために素子間のいわゆるフイールド
領域に厚い絶縁膜を形成する方法として、選択酸
化法が知られている。しかしながら、この選択酸
化法をますます微細化、高密度化が進む集積回路
の素子間分離法として用いるには、次のような問
題があるため高集積化の妨げとなる。第１にフイ
ールド酸化膜が鳥のくちばし（バースビーク）状
に食い込むことにより素子領域の寸法誤差が生じ
る。第２に、フイールド酸化時に高温、長時間の
熱処理（例えば1000℃５時間）を必要とするため
既にドープされているフイールド領域の不純物が
再拡散してしまい、素子形成領域にまでしみ出す
ことにより素子特性が劣化する。第３に、フイー
ルド酸化膜の膜厚の約半分を半導体基板に埋没す
る事が出来るが基板表面にはフイールド酸化膜厚
の約半分の段差が出来ることにより金属配線のこ
の段差部での信頼性が著しく低下する。
Conventionally, in semiconductor devices using silicon as a semiconductor, especially MOS type semiconductor integrated circuit devices, a method has been used to form a thick insulating film in the so-called field region between elements in order to eliminate insulation defects due to parasitic channels and reduce parasitic capacitance. , selective oxidation methods are known. However, when this selective oxidation method is used as a method for isolating elements in integrated circuits that are becoming increasingly finer and denser, the following problems arise, which impede higher integration. First, the field oxide film digs into the shape of a bird's beak, causing dimensional errors in the element region. Second, since field oxidation requires high-temperature and long-term heat treatment (for example, 1000°C for 5 hours), impurities in the field region that have already been doped are re-diffused and seep into the element formation region. Element characteristics deteriorate. Thirdly, although approximately half the thickness of the field oxide film can be buried in the semiconductor substrate, a step approximately half the thickness of the field oxide film is formed on the substrate surface, which reduces the reliability of the metal wiring at this step. decreases significantly.
以上のような問題を解決するために、従来半導
体装置の製造において半導体基板のフイールド領
域に凹部を形成し、この凹部に比較的厚い絶縁膜
を低温プロセスにより埋め込んで、平坦構造を得
る方法が用いられている。その一例を第１図ａ〜
ｈをもつて以下に説明する。 To solve the above-mentioned problems, a conventional method has been used in manufacturing semiconductor devices to form a recess in the field region of a semiconductor substrate, and then fill the recess with a relatively thick insulating film using a low-temperature process to obtain a flat structure. It is being An example of this is shown in Figure 1 a~
This will be explained below using h.
第１図ａに示すように、面方位（100）、比抵抗
５〜50ΩcmのＰ型シリコン基板１を用意し、この
表面に300Å程度の熱酸化膜２及び0.5μm程度の
Al膜３を順次形成する。次に同図ｂに示すよう
に、通常の写真蝕刻工程により素子形成領域上を
レジスト膜４でおおう。同図ｃに示すように、レ
ジスト膜４をマスクにしてフイールド領域上の
Al膜３及び熱酸化膜２を順次例えば反応性イオ
ンエツチング技術を用いてエツチングし、さらに
レジスト膜４及びAl膜３をマスクにして、例え
ばDF4ガスを用いた反応性イオンエツチングによ
りフイールド領域を約0.8μmエツチングして凹部
を形成し、さらにレジスト膜４、及びAl膜３を
マスクにしてフイールド領域のシリコン基板中に
イオン注入を行つて反転防止層５を形成する。次
に同図ｄに示すように、表面全面に第１の絶縁膜
として例えばプラズマCVD法によりシリコン酸
化膜（SiO2膜）６を約1.2μm堆積する。その後、
例えば弗化アンモニウム液でSiO2膜６を全面エ
ツチングすると、段差部側面のSiO2膜のエツチ
ング速度は平坦部でのSiO2膜のエツチング速度
より約20倍大きいため、同図ｅに示すように、
SiO2膜６がフイールド領域の凹部と素子形成領
域とに完全に分離され、凹部周辺部にＶ字形の溝
７が形成される。その後例えば硫酸と過酸化水素
水の混液によりウエハを処理すると、エツチング
マスクとして用いたAl膜３及びレジスト膜４が
除去され、これによりさらにその上のSiO2膜６
がリフトオフされ、結局同図ｆに示すように凹部
にSiO2膜６が埋ゆ込まれた形となる。次に同図
ｇに示すように、第２の絶縁膜として、例えば
CVDSiO2膜８を例えば1.0μm均一に堆積してＶ
字形溝７を完全に埋め込み、その上にさらに流動
性物質膜として例えばレジスト膜９を塗布して表
面を平坦化する。そして全面を例えば反応性イオ
ンエツチングでエツチングしていく。ここで、反
応性イオンエツチングの条件とレジスト膜９の熱
処理時間を適当に選ぶことにより、レジスト膜９
とSiO2膜８のエツチング速度をほぼ同程度に選
ぶ事ができる。このような条件で反応性イオンエ
ツチングを行い、レジスト膜９を完全にエツチン
グし、さらに素子形成領域上の半導体基板が露出
するまでSiO2膜８をエツチングすると、同図ｈ
に示すようにフイールド部に完全にSiO2膜６，
８が平坦な構造で埋め込まれる。この後は図示し
ないが、通常の素子形成工程により例えばMOS
型半導体装置を形成する。 As shown in FIG. 1a, a P-type silicon substrate 1 with a surface orientation (100) and a specific resistance of 5 to 50 Ωcm is prepared, and a thermal oxide film 2 of about 300 Å and a thermal oxide film 2 of about 0.5 μm are coated on its surface.
Al films 3 are formed one after another. Next, as shown in FIG. 4B, the element forming area is covered with a resist film 4 by a normal photolithography process. As shown in figure c, the resist film 4 is used as a mask to form a
The Al film 3 and the thermal oxide film 2 are sequentially etched using, for example, a reactive ion etching technique, and the field region is further etched by reactive ion etching using, for example, DF 4 gas, using the resist film 4 and the Al film 3 as a mask. Etching is performed by approximately 0.8 μm to form a recess, and further, using the resist film 4 and Al film 3 as a mask, ions are implanted into the silicon substrate in the field region to form an anti-inversion layer 5. Next, as shown in FIG. 4D, a silicon oxide film (SiO 2 film) 6 of about 1.2 μm is deposited as a first insulating film over the entire surface by, for example, plasma CVD. after that,
For example, when the entire surface of the SiO 2 film 6 is etched with an ammonium fluoride solution, the etching rate of the SiO 2 film on the side surface of the stepped portion is about 20 times higher than the etching rate of the SiO 2 film on the flat portion, so as shown in Figure e. ,
The SiO 2 film 6 is completely separated into the recess in the field region and the element formation region, and a V-shaped groove 7 is formed around the recess. Thereafter, when the wafer is treated with a mixture of sulfuric acid and hydrogen peroxide, the Al film 3 and resist film 4 used as an etching mask are removed, and the SiO 2 film 6 thereon is removed.
is lifted off, and as a result, the SiO 2 film 6 is buried in the recessed portion as shown in FIG. Next, as shown in figure g, a second insulating film, for example,
CVDSiO 2 film 8 is deposited uniformly, for example, 1.0 μm, and V
The groove 7 is completely buried, and a fluid material film such as a resist film 9 is further applied thereon to flatten the surface. Then, the entire surface is etched using, for example, reactive ion etching. Here, by appropriately selecting the reactive ion etching conditions and the heat treatment time for the resist film 9, the resist film 9 can be etched.
The etching rates of the SiO 2 film 8 and the SiO 2 film 8 can be selected to be approximately the same. When reactive ion etching is performed under these conditions, the resist film 9 is completely etched, and the SiO 2 film 8 is further etched until the semiconductor substrate over the element formation region is exposed, as shown in h of the same figure.
As shown in the figure, the field part is completely covered with SiO 2 film 6,
8 is embedded in a flat structure. After this, although not shown in the figure, for example, MOS
type semiconductor device is formed.
しかしながら、このような従来の方法では、リ
フトオフ加工を行うためにAl膜及びレジスト膜
を残したまま第１の絶縁膜を堆積する必要があ
り、従つてこの第１の絶縁膜を堆積する前にウエ
ハの前処理が出来ない。通常、硫酸と過酸化水素
水の混液、塩酸と過酸化水素水と水の混液または
希フツ酸等を用いて前処理を行うが、このような
前処理を行うとAl膜やレジスト膜が除去されて
しまうからである。また、Al膜及びレジスト膜
からのシリコン基板及び第１の絶縁膜への汚染を
生じ、素子特性を劣化させ製品の歩留りを著しく
低下させるなど重大な問題があつた。 However, in such conventional methods, in order to perform lift-off processing, it is necessary to deposit the first insulating film while leaving the Al film and resist film, and therefore, before depositing this first insulating film, Wafer preprocessing is not possible. Normally, pretreatment is performed using a mixture of sulfuric acid and hydrogen peroxide, a mixture of hydrochloric acid, hydrogen peroxide, and water, or dilute hydrofluoric acid, but when such pretreatment is performed, the Al film and resist film are removed. This is because it will be done. In addition, there were serious problems such as contamination of the silicon substrate and first insulating film from the Al film and resist film, deteriorating device characteristics and significantly lowering product yield.
本発明は上記素子間分離法の欠点に鑑みなされ
たもので、一回の写真食刻工程により素子間分離
を行ない、低温プロセスでフイールド領域に平坦
絶縁膜を埋め込む方法であつて、かつ素子特性を
汚染などにより劣化させることなく、微細素子の
高密度集積化を可能とした半導体装置の製造方法
を提供するものである。
The present invention was developed in view of the drawbacks of the above-mentioned device isolation method, and is a method of performing device isolation using a single photolithography process and embedding a flat insulating film in the field region using a low-temperature process. The present invention provides a method for manufacturing a semiconductor device that enables high-density integration of fine elements without deteriorating the semiconductor device due to contamination or the like.
本発明においてはまず、半導体基板の素子形成
領域がエツチング・ストツパ膜により覆われた状
態でフイールド領域に凹部を形成し、Al膜やレ
ジスト膜を残すことなく第１の絶縁膜を全面に堆
積する。そしてこの第１の絶縁膜の段差部をエツ
チング除去し、前記凹部の周辺にＶ字形の溝を形
成する。その後表面全面に溝を埋めて表面が平坦
になるように流動性物質膜を堆積し、この流動性
物質膜及び前記第１の絶縁膜の少なくとも一部を
エツチングして素子形成領域上の第１の絶縁膜を
除去する。これにより、リフトオフ加工によらず
凹部にのみ第１の絶縁膜が埋め込まれた状態が得
られる。その、前記後流動性物質膜を除去した
後、溝を埋めるように表面全面に第２の絶縁膜を
堆積して表面を平坦化し、この第２の絶縁膜をエ
ツチングして平坦構造でフイールド絶縁膜が埋め
込まれた状態で素子形成領域のエツチング・スト
ツパ膜を露出させ、このエツチング・ストツパ膜
を除去して基板表面を露出させる。その後、通常
良く用いられている方法に従い素子形成領域上に
所望の素子を形成するものである。
In the present invention, first, a recess is formed in the field region while the element formation region of the semiconductor substrate is covered with an etching stopper film, and a first insulating film is deposited on the entire surface without leaving any Al film or resist film. . Then, the stepped portion of the first insulating film is removed by etching, and a V-shaped groove is formed around the recessed portion. Thereafter, a fluid material film is deposited to fill the grooves over the entire surface so that the surface is flat, and at least a portion of the fluid material film and the first insulating film are etched to form the first insulating film on the element formation region. Remove the insulating film. As a result, a state in which the first insulating film is buried only in the recessed portions can be obtained without using lift-off processing. After removing the flowable material film, a second insulating film is deposited on the entire surface so as to fill the grooves to flatten the surface, and this second insulating film is etched to create a flat structure for field insulation. The etching stopper film in the element forming region is exposed while the film is buried, and the etching stopper film is removed to expose the substrate surface. Thereafter, a desired element is formed on the element forming region according to a commonly used method.
本発明の方法によれば、第１の絶縁膜を堆積す
る前に、Al膜及びレジスト膜が残置されている
ため十分な前処理が出来ないという問題が解決さ
れ、第１の絶縁膜を堆積する前に十分な前処理を
行なうことが可能となり、素子特性の劣化を防ぐ
ことができた。また本発明の方法によれば、凹部
のみに第１の絶縁膜を埋め込むのにAl膜及びレ
ジスト膜を使用しないので、これらの材料に起因
する汚染がなくなり、これにより素子特性の低下
はほとんどみられなくなり製品の歩留りが著しく
向上した。また素子形成領域が絶縁膜埋込みが終
了するまでエツチング・ストツパ膜によつて覆わ
れていて、埋込み終了後にエツチング・ストツパ
膜が除去される。したがつてこのエツチング・ス
トツパ膜の膜厚によつて、フイールド絶縁膜表面
位置より確実に素子形成領域の基板面が低い状態
が得られる。換言すれば、素子形成領域のエツジ
部側面が露出するという事態が確実に防止され、
エツジ部が露出することによる電界集中等による
素子特性低下が防止される。
According to the method of the present invention, the problem that sufficient pretreatment cannot be performed before depositing the first insulating film because the Al film and resist film remain is solved, and the first insulating film is deposited. It became possible to carry out sufficient pretreatment before deterioration, and it was possible to prevent deterioration of device characteristics. Furthermore, according to the method of the present invention, since an Al film and a resist film are not used to fill only the recessed portions with the first insulating film, contamination caused by these materials is eliminated, and as a result, there is almost no deterioration in device characteristics. The product yield has improved significantly. Further, the element formation region is covered with an etching stopper film until the filling of the insulating film is completed, and the etching stopper film is removed after the filling is completed. Therefore, the thickness of this etching stopper film ensures that the substrate surface in the element formation region is lower than the surface position of the field insulating film. In other words, the situation where the side surface of the edge part of the element formation region is exposed is reliably prevented.
Degradation of device characteristics due to electric field concentration and the like due to exposure of the edge portions is prevented.
以下本発明をMOS型半導体装置に適用した実
施例につき図面を参照して説明する。具体的な実
施例の説明に先立つて、第２図を参照して本発明
の基本プロセスを説明する。
Embodiments in which the present invention is applied to a MOS type semiconductor device will be described below with reference to the drawings. Before explaining specific embodiments, the basic process of the present invention will be explained with reference to FIG.
第２図ａに示すように、面方位（100）、比抵抗
５〜50ΩcmのＰ型シリコン基板１１を用意し、こ
の表面に300Å程度の熱酸化膜１２を形成する。
次に同図ｂに示すように、通常の写真蝕刻工程に
より素子形成領域上をレジスト膜１３でおおう。
次に同図ｃに示すように、レジスト膜１３をマス
クにして、フイールド領域上の熱酸化膜１２を例
えば反応性イオンエツチング技術を用いてエツチ
ングし、さらにレジスト膜１３及び熱酸化膜１２
をマスクにして、例えばCF4ガスを用いた反応性
イオンエツチングによりフイールド部を約0.8μm
エツチングして凹部を形成する。次に同図ｄに示
すように、レジスト膜１３及び熱酸化膜１２をマ
スクにしてフイールド部シリコン基板中にフイー
ルドイオン注入を行つて反転防止層１４を形成す
る。次にレジスト膜１３を除去した後、同図ｅに
示すように、表面全面に第１の絶縁膜として例え
ばプラズマCVD法によりシリコン酸化膜（SiO2
膜）１５を約1.2μm堆積する。この膜の堆積前に
は、シリコン基板表面全面を十分に清浄する。
SiO2膜１５を堆積後、例えば弗化アンモニウム
等の緩衝弗酸液でSiO2膜１５を全面エツチング
すると、段差部側面のSiO2膜のエツチング速度
は平坦部でのSiO2膜のエツチング速度より約20
倍大きいため、同図ｆに示すようにSiO2膜１５
がフイールド領域の凹部と素子形成領域とに完全
に分離され、凹部周辺にＶ字型の溝１６が形成さ
れる。次に同図ｇに示すように、溝を埋めて、表
面がほぼ平坦になるように全面に流動性物質膜と
して、例えばレジスト膜１７を塗布する。ここ
で、レジスト膜１７を塗布した場合、凸部の
SiO2膜１５上ではレジスト膜１７は薄く、凹部
のSiO2膜１５上ではレジスト膜１７は厚く塗布
されており表面はほぼ平坦となつている。次に同
図ｈに示すように、全面を例えば反応性イオンエ
ツチングでエツチングしていく。ここで、反応性
イオンエツチングの条件と、レジスト膜１７の熱
処理時間を適当に選ぶことにより、レジスト膜１
７とSiO2膜１５のエツチング速度をほぼ同程度
に選ぶことができる。このような条件で反応性イ
オンエツチングを行い、レジスト塗布膜厚のほぼ
半分程度エツチングした所でエツチングを止め
る。このエツチングでは、多少のオーバーエツチ
ング、あるいはアンダーエツチングがあつてもよ
い。要は、凸部のSiO2膜１５が露出しており、
凹部のSiO2膜１５がレジスト膜１７で覆われて
いる状態であれば良い。次に同図ｉに示すよう
に、例えば弗化アンモニウム液で全面エツチング
すると露出した凸部のSiO2膜１５及び熱酸化膜
１２が除去され、この後レジスト膜１７を除去す
ると、凹部にSiO2膜１５が埋め込まれた形とな
る。次に同図ｊに示すように、第２の絶縁膜とし
て、CVD法またはスパツタ法によるSiO2膜１８
を例えば1.0μm均一に堆積してＶ字溝１６を完全
に埋め込み、その上にさらに流動性物質膜として
例えばレジスト膜１９を塗布して表面を平坦化す
る。そして、全面を例えば反応性イオンエツチン
グでエツチングしていく。ここでも、反応性イオ
ンエツチングの条件と、レジスト膜１９の熱処理
時間を適当に選ぶ事により、レジスト膜１９と
SiO2膜１８のエツチング速度をほぼ同程度に選
ぶ事ができる。このような条件で反応性イオンエ
ツチングを行い、レジスト膜１９を完全にエツチ
ングし、さらに素子形成領域上の半導体基板が露
出するまでSiO2膜１８をエツチングすると、同
図ｋに示すようにフイールド部に完全にSiO2膜
１５，１８が平坦な構造で埋め込まれる。この後
は図示しないが、通常の素子形成工程により
MOS型半導体装置を形成する。 As shown in FIG. 2a, a P-type silicon substrate 11 with a (100) plane orientation and a resistivity of 5 to 50 Ωcm is prepared, and a thermal oxide film 12 of about 300 Å thick is formed on its surface.
Next, as shown in FIG. 5B, the element forming area is covered with a resist film 13 by a normal photolithography process.
Next, as shown in FIG. 3C, using the resist film 13 as a mask, the thermal oxide film 12 on the field area is etched using, for example, a reactive ion etching technique, and then the resist film 13 and the thermal oxide film 12 are etched.
Using the mask as a mask, the field area is etched by about 0.8 μm by reactive ion etching using, for example, CF 4 gas.
Etch to form a recess. Next, as shown in FIG. 4D, field ion implantation is performed into the silicon substrate in the field portion using the resist film 13 and the thermal oxide film 12 as a mask to form the anti-inversion layer 14. Next, after removing the resist film 13, as shown in Figure e, a silicon oxide film (SiO 2
Deposit film) 15 to a thickness of approximately 1.2 μm. Before depositing this film, the entire surface of the silicon substrate is thoroughly cleaned.
After depositing the SiO 2 film 15, if the entire surface of the SiO 2 film 15 is etched using a buffered hydrofluoric acid solution such as ammonium fluoride, the etching rate of the SiO 2 film on the side surface of the stepped portion will be higher than the etching rate of the SiO 2 film on the flat portion. about 20
Since it is twice as large, the SiO 2 film 15 is
is completely separated into a recess in the field region and an element formation region, and a V-shaped groove 16 is formed around the recess. Next, as shown in FIG. 3G, a resist film 17, for example, is applied as a fluid material film over the entire surface to fill the groove and make the surface substantially flat. Here, when the resist film 17 is applied, the convex portions are
The resist film 17 is thin on the SiO 2 film 15, and the resist film 17 is thick on the SiO 2 film 15 in the recessed portion, so that the surface is almost flat. Next, as shown in FIG. 6H, the entire surface is etched using, for example, reactive ion etching. Here, by appropriately selecting the reactive ion etching conditions and the heat treatment time for the resist film 17, the resist film 1
The etching rates of the SiO 2 film 7 and the SiO 2 film 15 can be selected to be approximately the same. Reactive ion etching is performed under these conditions, and the etching is stopped when approximately half the thickness of the resist coating film has been etched. This etching may include some overetching or underetching. In short, the SiO 2 film 15 on the convex portion is exposed,
It is sufficient that the SiO 2 film 15 in the recessed portion is covered with the resist film 17. Next, as shown in FIG . The film 15 is embedded. Next, as shown in FIG .
The V-groove 16 is completely buried by depositing it uniformly to a thickness of, for example, 1.0 μm, and a resist film 19, for example, is further applied thereon as a fluid material film to flatten the surface. Then, the entire surface is etched using, for example, reactive ion etching. Here too, by appropriately selecting the conditions for reactive ion etching and the heat treatment time for the resist film 19, the resist film 19 and
The etching rate of the SiO 2 film 18 can be selected to be approximately the same. When reactive ion etching is performed under these conditions, the resist film 19 is completely etched, and the SiO 2 film 18 is further etched until the semiconductor substrate over the element formation region is exposed, the field portion is etched as shown in FIG. The SiO 2 films 15 and 18 are completely buried in a flat structure. After this, although not shown, the normal element forming process is performed.
Form a MOS type semiconductor device.
この基本プロセスによれば、第１の絶縁膜を堆
積する前にウエハ前処理を十分に行なうことが出
来、素子特性の劣化を防ぐことができた。しかも
この実施例によれば、凹部のみに第１の絶縁膜を
埋め込むのにAl膜及びレジスト膜を使用しない
ので、それらによる汚染がなくなりこれにより素
子特性は安定し、製品の歩留りが著しく向上し
た。 According to this basic process, it was possible to perform sufficient wafer pretreatment before depositing the first insulating film, and it was possible to prevent deterioration of device characteristics. Moreover, according to this embodiment, since the Al film and the resist film are not used to fill the first insulating film only in the recessed portions, there is no contamination caused by them, which stabilizes the device characteristics and significantly improves the product yield. .
ただし以上の基本プロセスのみでは、絶縁膜埋
込みの際のエツチング停止制御が容易ではなく、
オーバーエツチングによつて素子形成領域のエツ
ジ側面が露出する事態が生じる可能性がある。こ
れは、電界集中等による素子特性低下の原因にな
る。 However, with only the above basic process, it is not easy to control the etching stop when embedding the insulating film.
There is a possibility that the edge side of the element forming region may be exposed due to overetching. This causes deterioration of device characteristics due to electric field concentration and the like.
この点を解決したのが、次の第３図に示す実施
例である。 The embodiment shown in FIG. 3 below solves this problem.
第３図ａに示すように比抵抗５〜50ΩcmのＰ型
シリコン基板２１を用意し、その表面に例えば
300Å程度の熱酸化膜２２を介して1000Å程度の
エツチング・ストツパ膜としてのシリコン窒化膜
２３を形成する。次に同図ｂに示すように通常の
写真蝕刻工程により素子形成領域上にレジスト膜
２４を形成し、これをマスクにして、例えば反応
性イオンエツチング技術を用して、同図ｃに示す
ようにシリコン窒化膜２３、熱酸化膜２２、及び
半導体基板２１の一部をエツチングして凹部を形
成する。さらに同図ｄに示すようにフイールド領
域にフイールドイオン注入を行い、反転防止層２
５を形成する。次にレジスト膜２４を除去後、前
処理（例えば硫酸と過酸化水素水の混液によるウ
エハの処理及び塩酸と過酸化水素水と水の混液に
よるウエハの処理及び希フツ酸によるウエハの処
理）を十分に行ない、ウエハを清浄化して、同図
ｅに示すように第１の絶縁膜として例えばプラズ
マCVD法によりSiO2膜２６を凹部段差より厚く
半導体基板表面全面に堆積する。その後例えば弗
化アンモニウム液でSiO2膜２６をエツチングす
る。このとき、前述のように段差部側面での
SiO2膜２６のエツチング速度は平坦部でのエツ
チング速度より約20倍はやいため、同図ｆに示す
ようにSiO2膜がフイールド領域の凹部と素子形
成領域とに完全に分離され、凹部周辺にＶ字溝２
７が形成される。その後、実施例１と同様、同図
ｇのようにレジスト膜２８を堆積し素子形成領域
上に残置されたSiO2膜２６が露出するまで例え
ば反応性イオンエツチングでエツチングを行な
い、同図ｈのようにSiO2膜２６を露出させる。
その後、例えば弗化アンモニウム液でSiO2膜２
６をエツチングする。このとき、凹部のSiO2膜
２６はレジスト膜２８で覆われているのでエツチ
ング除去されない。この弗化アンモニウム液での
SiO2膜２６のエツチングは、シリコン窒化膜２
３の表面で止まる。この後レジスト膜２８を除去
すると、同図ｉに示すようになる。その後、同図
ｊに示すように、CVDによるSiO2膜２９、更に
レジスト膜３０を堆積し、これらを均一にエツチ
ングして同図ｋに示すように素子形成領域のシリ
コン窒化膜２３の表面を露出させる。次に、例え
ばSiO2膜２６，２９に対して、シリコン窒化膜
２３のエツチング比が十分大きくとれる例えば
CF4ガスを含むプラズマエツチング法によりエツ
チングすると、同図ｌに示すようにシリコン窒化
膜２３のみを除去できる。次に同図ｍに示すよう
に例えば弗化アンモニウム液によりSiO2膜２６，
２９及び熱酸化膜２２を均一エツチングして素子
形成領域の基板表面を露出させる。 As shown in FIG. 3a, a P-type silicon substrate 21 with a specific resistance of 5 to 50 Ωcm is prepared, and its surface is coated with, for example,
A silicon nitride film 23 of about 1000 Å as an etching stopper film is formed through a thermal oxide film 22 of about 300 Å. Next, as shown in FIG. 2B, a resist film 24 is formed on the element forming area by a normal photolithography process, and using this as a mask, for example, reactive ion etching technology is used to form a resist film 24 as shown in FIG. Then, the silicon nitride film 23, the thermal oxide film 22, and a portion of the semiconductor substrate 21 are etched to form a recessed portion. Furthermore, as shown in Figure d, field ion implantation is performed in the field region to form the anti-inversion layer
form 5. Next, after removing the resist film 24, pretreatment (for example, wafer treatment with a mixture of sulfuric acid and hydrogen peroxide, treatment of the wafer with a mixture of hydrochloric acid, hydrogen peroxide, and water, and treatment of the wafer with dilute hydrofluoric acid) is performed. After thoroughly cleaning the wafer, a SiO 2 film 26 is deposited as a first insulating film on the entire surface of the semiconductor substrate by, for example, plasma CVD to be thicker than the steps of the recesses, as shown in FIG. Thereafter, the SiO 2 film 26 is etched using, for example, an ammonium fluoride solution. At this time, as mentioned above, the
Since the etching rate of the SiO 2 film 26 is about 20 times faster than the etching rate on the flat area, the SiO 2 film is completely separated into the recessed part of the field region and the element formation area, and the etching is carried out around the recessed part, as shown in FIG. V-shaped groove 2
7 is formed. Thereafter, in the same manner as in Example 1, a resist film 28 is deposited as shown in FIG. The SiO 2 film 26 is exposed in this manner.
After that, the SiO 2 film 2 is removed using, for example, ammonium fluoride solution.
Etch 6. At this time, the SiO 2 film 26 in the recessed portion is covered with the resist film 28 and is therefore not removed by etching. With this ammonium fluoride solution
The etching of the SiO 2 film 26 is performed by etching the silicon nitride film 2.
It stops on the surface of 3. After the resist film 28 is removed, the result is as shown in FIG. Thereafter, as shown in Figure J, a SiO 2 film 29 and a resist film 30 are deposited by CVD, and these are uniformly etched to cover the surface of the silicon nitride film 23 in the element formation region, as shown in Figure K. expose. Next, the etching ratio of the silicon nitride film 23 to, for example, the SiO 2 films 26 and 29 is sufficiently large.
When etching is performed using a plasma etching method containing CF 4 gas, only the silicon nitride film 23 can be removed as shown in FIG. Next, as shown in figure m, the SiO 2 film 26,
29 and the thermal oxide film 22 are uniformly etched to expose the substrate surface in the element formation region.
本実施例によれば、シリコン窒化膜２３を設け
たことにより素子形成領域よりもフイールド領域
のSiO2膜を厚く形成出来、素子形成領域のシリ
コン基板のエツヂが露出することによる素子特性
の劣化を防ぐことが出来、製品の歩留りが著しく
向上した。 According to this embodiment, by providing the silicon nitride film 23, the SiO 2 film in the field region can be formed thicker than in the element formation region, and deterioration of element characteristics due to exposure of the edge of the silicon substrate in the element formation region can be prevented. This resulted in a significant improvement in product yield.
なお以上の実施例において、最初に凹部に埋め
込む第１の絶縁膜としてCVD法によるSiO2膜を
用いたのは、SiO2膜をエツチングする場合、段
差部でのエツチング速度が平坦部でのエツチング
速度に比べて十分大きい事を利用するためで、こ
のような性質はプラズマSiO2に限らずスパツタ
法によつて形成したSiO2膜更に同様の方法によ
るSi3N4膜やPSG膜においてもみられ、このよう
な膜が本発明方法において第１の絶縁膜として使
用できる事は当然である。またこの発明はMOS
型半導体装置に限らず、バイポーラ型半導体装置
での素子間分離にも適用できる事はもちろんであ
る。 In the above embodiments, the SiO 2 film formed by the CVD method was used as the first insulating film to be buried in the recesses because the etching rate at the stepped portion is lower than that at the flat portion. This is to take advantage of the fact that the speed is sufficiently large compared to the speed, and this property is observed not only in plasma SiO 2 but also in SiO 2 films formed by sputtering, as well as Si 3 N 4 films and PSG films formed by similar methods. , it is natural that such a film can be used as the first insulating film in the method of the present invention. This invention also applies to MOS
It goes without saying that the present invention can be applied not only to type semiconductor devices but also to isolation between elements in bipolar type semiconductor devices.
第１図ａ〜ｈは、従来の半導体装置の製造工程
を説明するための断面図、第２図ａ〜ｋ及び第３
図ａ〜ｍは、それぞれこの発明の実施例の製造工
程を示す断面図である。
１１，２１……シリコン基板、１２，２２……
熱酸化膜、１３，２４……レジスト膜、１４，２
５……反転防止層、１５，２６……プラズマ
CVDSiO2膜（第１の絶縁膜）、１６，２７……Ｖ
字溝、１７，２８……レジスト膜、１８，２９…
…CVDSiO2膜（第２の絶縁膜）、１９，３０……
レジスト膜（第２の絶縁膜）、２３……シリコン
窒化膜。
1A to 1H are cross-sectional views for explaining the manufacturing process of a conventional semiconductor device, and FIGS.
Figures a to m are cross-sectional views showing manufacturing steps of embodiments of the present invention, respectively. 11, 21... Silicon substrate, 12, 22...
Thermal oxide film, 13, 24...Resist film, 14, 2
5... Inversion prevention layer, 15, 26... Plasma
CVDSiO 2 film (first insulating film), 16, 27...V
Groove, 17, 28...Resist film, 18, 29...
...CVDSiO 2 film (second insulating film), 19, 30...
Resist film (second insulating film), 23...Silicon nitride film.
Claims (1)
トツパ膜で覆われた状態でフイールド領域に凹部
を形成する工程と、この凹部が形成された基板全
面に段差部でのエツチング速度が平坦部でのそれ
より大きい第１の絶縁膜を堆積する工程と、この
第１の絶縁膜の段差部をエツチング除去すること
により前記凹部の周辺に溝を形成する工程と、こ
の溝を埋めて表面が平坦になるように全面に流動
性物質膜を堆積する工程と、この流動性物質膜及
び前記第１の絶縁膜の少なくとも一部をエツチン
グして素子形成領域上の第１の絶縁膜を露出させ
る工程と、前記流動性物質膜をマスクとして素子
形成領域上の前記第１の絶縁膜をエツチング除去
する工程と、前記流動性物質膜を除去し、前記溝
を埋めるように全面に第２の絶縁膜を堆積する工
程と、この第２の絶縁膜を表面が平坦になるよう
にエツチングして素子形成領域の前記エツチン
グ・ストツパ膜を露出させる工程と、露出したエ
ツチング・ストツパ膜を除去して、露出した基板
面に所望の素子を形成する工程とを備えたことを
特徴とする半導体装置の製造方法。 ２ 前記第１の絶縁膜はプラズマCVD法または
スパツタ法によるSiO2膜、Si3N4膜またはPSG膜
であり、その段差部をエツチングする方法は緩衝
弗酸液によるエツチング法である特許請求の範囲
第１項記載の半導体装置の製造方法。 ３ 前記第２の絶縁膜は、CVD法またはスパツ
タ法によるSiO2膜とその上に表面が平坦になる
ように形成された流動性物質膜からなり、この第
２の絶縁膜をエツチングする方法は、上記SiO2
膜と流動性物質膜に対してエツチング速度が等し
い反応性イオンエツチング法である特許請求の範
囲第１項記載の半導体装置の製造方法。[Claims] 1. A step of forming a recess in a field region with the element formation region of the semiconductor substrate covered with an etching stopper film, and a step of increasing the etching rate at the stepped portion over the entire surface of the substrate where the recess is formed. a step of depositing a first insulating film larger than that on the flat portion; a step of etching away the stepped portion of the first insulating film to form a groove around the recess; and a step of filling the groove. Depositing a fluid material film over the entire surface so that the surface is flat, and etching at least a portion of the fluid material film and the first insulating film to form the first insulating film on the element forming region. an exposing step, a step of etching away the first insulating film on the element formation region using the fluid material film as a mask, and a step of removing the fluid material film and etching a second insulating film over the entire surface so as to fill the groove. a step of depositing an insulating film, a step of etching this second insulating film so that its surface becomes flat to expose the etching stopper film in the element formation region, and removing the exposed etching stopper film. and forming a desired element on the exposed surface of the substrate. 2. The first insulating film is an SiO 2 film, a Si 3 N 4 film, or a PSG film formed by plasma CVD or sputtering, and the step portion thereof is etched by an etching method using a buffered hydrofluoric acid solution. A method for manufacturing a semiconductor device according to scope 1. 3. The second insulating film consists of a SiO 2 film formed by CVD or sputtering and a fluid material film formed thereon so that the surface is flat, and the method for etching this second insulating film is as follows: , above SiO2
2. The method of manufacturing a semiconductor device according to claim 1, wherein a reactive ion etching method is used in which the etching rate is equal for the film and the fluid material film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13868482A JPS5928358A (en) | 1982-08-10 | 1982-08-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13868482A JPS5928358A (en) | 1982-08-10 | 1982-08-10 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5928358A JPS5928358A (en) | 1984-02-15 |
| JPH0427703B2 true JPH0427703B2 (en) | 1992-05-12 |
Family
ID=15227684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13868482A Granted JPS5928358A (en) | 1982-08-10 | 1982-08-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5928358A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5984548A (en) * | 1982-11-08 | 1984-05-16 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| JPH0738383B2 (en) * | 1984-10-29 | 1995-04-26 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
| JPS6224627A (en) * | 1985-07-25 | 1987-02-02 | Sony Corp | Dry etching method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363871A (en) * | 1976-11-18 | 1978-06-07 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5791537A (en) * | 1980-11-29 | 1982-06-07 | Toshiba Corp | Manufacture of semiconductor device |
-
1982
- 1982-08-10 JP JP13868482A patent/JPS5928358A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363871A (en) * | 1976-11-18 | 1978-06-07 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5791537A (en) * | 1980-11-29 | 1982-06-07 | Toshiba Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5928358A (en) | 1984-02-15 |
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