JPS6387741A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6387741A
JPS6387741A JP23362586A JP23362586A JPS6387741A JP S6387741 A JPS6387741 A JP S6387741A JP 23362586 A JP23362586 A JP 23362586A JP 23362586 A JP23362586 A JP 23362586A JP S6387741 A JPS6387741 A JP S6387741A
Authority
JP
Japan
Prior art keywords
film
oxidation
oxide film
silicon nitride
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23362586A
Other languages
Japanese (ja)
Inventor
Fumihiro Okabe
岡部 文洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23362586A priority Critical patent/JPS6387741A/en
Publication of JPS6387741A publication Critical patent/JPS6387741A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable integration to be upgraded, by forming the second thick oxidation-proof film on the first thin oxidation-proof film through the second oxidizing film and thereafter patterning these films to form a mask and forming a field oxidizing film on the surface of a semiconductor substrate. CONSTITUTION:The second thick silicon nitride film 4 is formed on the first thin silicon nitride film 2 through the second silicon oxide film 3. The second thick silicon nitride film 4 is etched irrespective of a selection ratio of reactive ion etching. Even if irregularity of etching occurs when this first silicon nitride film 2 is etched, the etching stays in the first silicon oxide film 1 and it does not advance to the surface of a semiconductor substrate 5 because the first silicon nitride film 2 is formed thin. Therefore, this etching does not have effects on elements formed in the later process and so integration can be upgraded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に選択酸化法
におけるマスクとなる耐酸化性膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an oxidation-resistant film that serves as a mask in a selective oxidation method.

〔従来の技術〕[Conventional technology]

半導体装置のフィールド領域を形成する従来の方法につ
いて第2図(a)〜・(c)を用いて説明する。
A conventional method for forming a field region of a semiconductor device will be described with reference to FIGS. 2(a) to 2(c).

まず、第2図(a)に示すように半導体基板5上に熱酸
化により薄い酸化シリコン膜3Aを形成し、その後窒化
シリコン等の耐酸化性被膜4Aを気相成長などを用いて
形成する。
First, as shown in FIG. 2(a), a thin silicon oxide film 3A is formed on the semiconductor substrate 5 by thermal oxidation, and then an oxidation-resistant film 4A of silicon nitride or the like is formed by vapor phase growth or the like.

次に第2図(b)に示すように、ホトレジストからなる
マスク6を形成したのち、写真蝕刻技術を用いて耐酸化
性被膜4Aをパターニングする。
Next, as shown in FIG. 2(b), after forming a mask 6 made of photoresist, the oxidation-resistant film 4A is patterned using photolithography.

次に第2図(c)に示すようにマスク6を除き、チャネ
ルストッパ層形成の為のイオン注入を行なった後に熱酸
化しフィールド酸化膜7を形成する。
Next, as shown in FIG. 2(c), the mask 6 is removed, ions are implanted to form a channel stopper layer, and then a field oxide film 7 is formed by thermal oxidation.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のフィールド酸化膜7を形成するための選
択酸化技術では、熱酸化時、酸化が横方向に進み、耐酸
化性被膜4Aの下に酸化シリコンがくいこんでしまう、
しかし素子の微細化に伴ない、上記の酸化シリコンのく
い込みがデバイス設計に大きな問題を与える。
In the conventional selective oxidation technique for forming the field oxide film 7 described above, oxidation progresses laterally during thermal oxidation, and silicon oxide sinks under the oxidation-resistant film 4A.
However, with the miniaturization of elements, the penetration of the silicon oxide described above poses a major problem in device design.

この酸化シリコンのくい込みをおさえるためには、下地
の半導体基板の酸化シリコン膜3Aの厚さをうすくおさ
え、またその上の耐酸化性被膜4Aの膜厚を厚くする必
要がある。
In order to suppress this penetration of silicon oxide, it is necessary to keep the thickness of the silicon oxide film 3A of the underlying semiconductor substrate small and to increase the thickness of the oxidation-resistant film 4A thereon.

しかしこの耐酸化性被膜4Aを厚くした場合、この耐酸
化性被膜4Aをエツチングする為の反応性イオンエツチ
ングの選択比が大きくとれないため、パターニングの時
に半導体基板5までエツチングしてしまい、素子を形成
した場合リーク電流の増大となり、半導体装置の製造歩
留り及び信頼性を低下させるという問題点がある。
However, when this oxidation-resistant film 4A is made thicker, the selective ratio of reactive ion etching for etching this oxidation-resistant film 4A cannot be made large, so that the semiconductor substrate 5 is etched during patterning, resulting in the device being damaged. If formed, there is a problem in that leakage current increases and the manufacturing yield and reliability of semiconductor devices are reduced.

本発明の目的は、上記問題点を除去し、集積度が高く、
かつ製造歩留り及び信頼性の向上した半導体装置を提供
することにある。
The purpose of the present invention is to eliminate the above problems, achieve a high degree of integration,
Another object of the present invention is to provide a semiconductor device with improved manufacturing yield and reliability.

〔問題点を解決するための手段〕 本発明の半導体装置の製造方法は、半導体基板表面に第
1の酸化膜を形成したのち第1の酸化膜上に薄い第1の
耐酸化性膜を形成する工程と、前記第1の耐酸化性膜上
に第2の酸化膜を介して厚い第2の耐酸化性膜を形成す
る工程と、前記第2の耐酸化性膜上にホトレジスト層を
形成したのちパターニングし、素子形成予定領域上にマ
スクを形成する工程と、前記マスクを用い前記第2の耐
酸化性膜と第2の酸化膜及び第1の耐酸化性膜とを順次
エツチングし除去する工程と、前記マスクを除去したの
ち第1及び第2の耐酸化性膜をマスクとして前記半導体
基板表面を酸化しフィールド酸化膜を形成する工程とを
含んで構成される。
[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes forming a first oxide film on the surface of a semiconductor substrate, and then forming a thin first oxidation-resistant film on the first oxide film. forming a thick second oxidation resistant film on the first oxidation resistant film via a second oxide film; and forming a photoresist layer on the second oxidation resistant film. After that, patterning is performed, and a step of forming a mask on the area where the element is to be formed, and using the mask, the second oxidation resistant film, the second oxide film, and the first oxidation resistant film are sequentially etched and removed. and a step of removing the mask and then oxidizing the surface of the semiconductor substrate using the first and second oxidation-resistant films as masks to form a field oxide film.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。
FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

まず第1図(a)に示すように、半導体基板5上に熱酸
化法により厚さ約100人の第1の酸化シリコン膜1を
形成したのち、この第1の酸化シリコン膜1状にCVD
法により厚さ約200人の第1の窒化シリコン膜2を形
成する。続いて全面にCV D法により厚さ500〜1
000人の第2の酸化シリコン膜2と厚さ1000〜2
000人の第2の窒化シリコン[4を順次形成する。
First, as shown in FIG. 1(a), a first silicon oxide film 1 with a thickness of approximately 100 layers is formed on a semiconductor substrate 5 by thermal oxidation, and then CVD is applied to the first silicon oxide film 1.
A first silicon nitride film 2 having a thickness of about 200 wafers is formed by the method. Subsequently, the entire surface is coated with a thickness of 500~1 by CVD method.
000 second silicon oxide film 2 and thickness 1000~2
000 second silicon nitride [4] is sequentially formed.

次に第1図(b)に示すように全面にホトレジスト層を
形成したのち、パターニングして素子形成予定領域上に
ホトレジストからなるマスク6を形成する。続いてこの
マスク6を用い反応性イオンエツチング法により第2の
窒化シリコン膜4をエツチングし除去する。この時エツ
チング速度にばらつきを生じ第2の酸化シリコン膜3が
エツチングされてもよい。
Next, as shown in FIG. 1(b), a photoresist layer is formed on the entire surface and then patterned to form a mask 6 made of photoresist on the area where the element is to be formed. Subsequently, using this mask 6, the second silicon nitride film 4 is etched and removed by a reactive ion etching method. At this time, the second silicon oxide film 3 may be etched with variations in the etching rate.

次に第1図(c)に示すように緩衝性フッ酸溶液で第2
の酸化シリコン膜3を、反応性イオンエツチングで第1
の窒化シリコン膜2を順次エツチングしたのちマスク6
を除去する。
Next, as shown in Figure 1(c), a second solution was prepared using buffered hydrofluoric acid solution.
The first silicon oxide film 3 is etched by reactive ion etching.
After sequentially etching the silicon nitride film 2 of
remove.

次に第1図(d)に示すように、第1及び第2の窒化シ
リコン膜2,4をマスクとして熱酸化を行ない、半導体
基板表面にフィールド酸化膜7を形成する。
Next, as shown in FIG. 1(d), thermal oxidation is performed using the first and second silicon nitride films 2 and 4 as masks to form a field oxide film 7 on the surface of the semiconductor substrate.

このように本実施例においては、第2の酸化シリコン膜
3を介して、薄い第1の窒化シリコン膜2上に厚い第2
の窒化シリコン膜4を設けることにより、反応性イオン
エツチングの選択比にとられれることなく、厚い第2の
窒化シリコン膜4をエツチングできる。そして第1の窒
化シリコン膜2は薄く形成されているために、この第1
の窒化シリコン膜2をエツチングする場合、エツチング
にばらつきを生じてもエツチングは第1の酸化シリコン
膜1の部分で止り、半導体基板5の表面までエツチング
されることはない。従ってこのエツチングは後工程で形
成される素子に影響を与えることはない。
As described above, in this embodiment, a thick second silicon oxide film is formed on a thin first silicon nitride film 2 via a second silicon oxide film 3.
By providing the silicon nitride film 4, the thick second silicon nitride film 4 can be etched without being affected by the selectivity of reactive ion etching. Since the first silicon nitride film 2 is formed thinly, this first silicon nitride film 2
When etching the silicon nitride film 2, even if there are variations in etching, the etching stops at the first silicon oxide film 1 and does not reach the surface of the semiconductor substrate 5. Therefore, this etching does not affect elements formed in subsequent steps.

〔発明の効果〕 以上説明したように本発明は第1の酸化膜が形成された
半導体基板上の薄い第1の耐酸化性膜上に、第2の酸化
膜を介して厚い第2の耐酸化性膜を形成したのち、これ
ら第2の耐酸化性膜と第2の酸化膜及び第1の耐酸化性
膜とをパターニングしてマスクを形成して半導体基板表
面にフィールド酸化膜を形成することにより、マスク下
部にくい込みの少ないフィールド酸化膜が形成できる。
[Effects of the Invention] As explained above, the present invention provides a method for forming a thick second oxidation-resistant film on a thin first oxidation-resistant film on a semiconductor substrate on which a first oxide film is formed, via a second oxide film. After forming the oxidation-resistant film, the second oxidation-resistant film, the second oxide film, and the first oxidation-resistant film are patterned to form a mask to form a field oxide film on the surface of the semiconductor substrate. As a result, a field oxide film can be formed with less digging into the lower part of the mask.

従って集積度が高くかつ製造歩留り及び信頼性の向上し
た半導体装置が得られる。
Therefore, a semiconductor device with a high degree of integration and improved manufacturing yield and reliability can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図(a
)〜(c)は従来の半導体装置の製造方法を説明する為
の工程順に示した半導体チップの断面図である。 1・・・第1の酸化・シリコン膜、2・・・第1の窒化
シリコン膜、3・・・第2の酸化シリコン膜、3A・・
・酸化シリコン膜、4・・・第2の窒化シリコン膜、4
A・・・耐酸化性被膜、5・・・半導体基板、6・・・
マスク、7・・・フィールド酸化膜。 1.−7 代理人 弁理士 内 原  音にl。 く、・〜 S第1 図
1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... First oxide/silicon film, 2... First silicon nitride film, 3... Second silicon oxide film, 3A...
-Silicon oxide film, 4...Second silicon nitride film, 4
A... Oxidation-resistant film, 5... Semiconductor substrate, 6...
Mask, 7...Field oxide film. 1. -7 Agent Patent Attorney Uchihara Otoni l. ku・・〜SFigure 1

Claims (1)

【特許請求の範囲】[Claims]  半導体基板表面に第1の酸化膜を形成したのち該第1
の酸化膜上に薄い第1の耐酸化性膜を形成する工程と、
前記第1の耐酸化性膜上に第2の酸化膜を介して厚い第
2の耐酸化性膜を形成する工程と、前記第2の耐酸化性
膜上にホトレジスト層を形成したのちパターニングし、
素子形成予定領域上にマスクを形成する工程と、前記マ
スクを用い前記第2の耐酸化性膜と第2の酸化膜及び第
1の耐酸化性膜とを順次エッチングし除去する工程と、
前記マスクを除去したのち第1及び第2の耐酸化性膜を
マスクとして前記半導体基板表面を酸化しフィールド酸
化膜を形成する工程とを含むことを特徴とする半導体装
置の製造方法。
After forming a first oxide film on the surface of the semiconductor substrate, the first oxide film is formed on the surface of the semiconductor substrate.
forming a thin first oxidation-resistant film on the oxide film;
forming a thick second oxidation resistant film on the first oxidation resistant film via a second oxide film; forming a photoresist layer on the second oxidation resistant film and then patterning it; ,
a step of forming a mask on a region where an element is to be formed; a step of sequentially etching and removing the second oxidation-resistant film, the second oxide film, and the first oxidation-resistant film using the mask;
A method of manufacturing a semiconductor device, comprising the step of removing the mask and then oxidizing the surface of the semiconductor substrate using first and second oxidation-resistant films as masks to form a field oxide film.
JP23362586A 1986-09-30 1986-09-30 Manufacture of semiconductor device Pending JPS6387741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23362586A JPS6387741A (en) 1986-09-30 1986-09-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23362586A JPS6387741A (en) 1986-09-30 1986-09-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6387741A true JPS6387741A (en) 1988-04-19

Family

ID=16957978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23362586A Pending JPS6387741A (en) 1986-09-30 1986-09-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6387741A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358892A (en) * 1993-02-11 1994-10-25 Micron Semiconductor, Inc. Etch stop useful in avoiding substrate pitting with poly buffered locos
US5472904A (en) * 1994-03-02 1995-12-05 Micron Technology, Inc. Thermal trench isolation
US5753962A (en) * 1996-09-16 1998-05-19 Micron Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US5837596A (en) * 1994-03-02 1998-11-17 Micron Technology, Inc. Field oxide formation by oxidation of polysilicon layer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358892A (en) * 1993-02-11 1994-10-25 Micron Semiconductor, Inc. Etch stop useful in avoiding substrate pitting with poly buffered locos
US5472904A (en) * 1994-03-02 1995-12-05 Micron Technology, Inc. Thermal trench isolation
US5837596A (en) * 1994-03-02 1998-11-17 Micron Technology, Inc. Field oxide formation by oxidation of polysilicon layer
US5888881A (en) * 1994-03-02 1999-03-30 Micron Technology, Inc. Method of trench isolation during the formation of a semiconductor device
US5753962A (en) * 1996-09-16 1998-05-19 Micron Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US6114218A (en) * 1996-09-16 2000-09-05 Microm Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation

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