JPS63257244A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPS63257244A
JPS63257244A JP9271087A JP9271087A JPS63257244A JP S63257244 A JPS63257244 A JP S63257244A JP 9271087 A JP9271087 A JP 9271087A JP 9271087 A JP9271087 A JP 9271087A JP S63257244 A JPS63257244 A JP S63257244A
Authority
JP
Japan
Prior art keywords
insulator
oxide film
silicon substrate
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9271087A
Other languages
Japanese (ja)
Inventor
Muraji Kawai
河合 邑司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9271087A priority Critical patent/JPS63257244A/en
Publication of JPS63257244A publication Critical patent/JPS63257244A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent an insulator from sinking below the surface of a semiconductor substrate by forming a device isolation region in such a way that the insulator filled in a groove is projected from the surface of the semiconductor substrate. CONSTITUTION:An insulator 5 is filled in a groove 2 and is formed by a CVD oxide film. The insulator 5 is projected from the surface of a silicon substrate 1 by, e.g., about 1000-5000 Angstrom . The height of this protrusion of the insulator 5 is set appropriately in such a way that the insulator 5 does not sink below the surface of the silicon substrate 1 after an operation to be executed during a subsequent device formation process. By this setup, even when the insulator 5 is etched to some extent by a subsequent etching operation, the insulator 5 does not sink below the surface of the silicon substrate 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、絶縁物によって素子分離を行っている半導
体装置およびその製造方法に係り、特に半導体基板に形
成された溝部に絶縁物を埋め込んだ素子分離領域を備え
た半導体装置およびその製造方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device in which elements are separated by an insulator and a method for manufacturing the same, and particularly relates to a semiconductor device in which elements are isolated by an insulator and a method for manufacturing the same. The present invention relates to a semiconductor device including an element isolation region and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

第3図fatは、このような従来の半導体装置の構成を
示した断面図である。
FIG. 3 fat is a sectional view showing the structure of such a conventional semiconductor device.

図において、1はシリコン基板、2は素子領域A、Bを
分離するためにシリコン基Fi、l上に形成された溝部
、3はシリコン基板1の表面とほぼ同一面になるように
溝部2に埋め込まれた絶縁物である。絶縁物3としては
、例えばCV D (Chemical Vapor 
Deposition)酸化膜が用いられる。
In the figure, 1 is a silicon substrate, 2 is a groove formed on a silicon base Fi,l to separate the element regions A and B, and 3 is a groove 2 formed so as to be almost flush with the surface of the silicon substrate 1. It is an embedded insulator. As the insulator 3, for example, CVD (Chemical Vapor
Deposition) An oxide film is used.

次に、上述した従来の半導体装置の製造方法を第4図に
従って説明する。
Next, a method of manufacturing the above-mentioned conventional semiconductor device will be explained with reference to FIG.

シリコン基板1上に素子領域A、Bを分離するように溝
部2を形成する(第4図fa)参照)。溝部2が形成さ
れたシリコン基板1上にCVD酸化膜3. (このCV
D酸化1123 、は最終的には第3図に示した絶縁物
3になる)を堆積し、このCVD酸化膜3.で溝部2を
埋め込む(第4図山)参照)。
Groove portions 2 are formed on silicon substrate 1 to separate element regions A and B (see FIG. 4 fa). A CVD oxide film 3. is formed on the silicon substrate 1 in which the groove portion 2 is formed. (This CV
D oxide 1123 (which will eventually become the insulator 3 shown in FIG. 3) is deposited, and this CVD oxide film 3. Fill the groove 2 with (see Fig. 4 mountain)).

CVD酸化膜3.が堆積されたシリコン基板1上にフォ
トレジスト4を厚く塗布しく第4図(C)参照)、シリ
コン基板10表面が露出するまでフォトレジスト4およ
びCVD酸化膜3.を平坦にエツチングする。このよう
にして第3図に示したような溝部2に絶縁物3が埋め込
まれた素子分離領域が形成される。なお、上述した製造
方法の説明では省略したが、CVD酸化膜31を埋め込
む前に、溝部2内ヘチヤネルカソト用のボロンを注入し
たり、熱酸化膜を形成したりする処理等が適宜に行われ
ている。
CVD oxide film 3. The photoresist 4 is coated thickly on the silicon substrate 1 on which the CVD oxide film 3. is deposited (see FIG. 4(C)), and the photoresist 4 and the CVD oxide film 3. Etch it flat. In this way, an element isolation region in which the insulator 3 is embedded in the trench 2 as shown in FIG. 3 is formed. Although omitted in the explanation of the manufacturing method described above, before embedding the CVD oxide film 31, treatments such as implanting boron for channel oxidation into the trench 2 and forming a thermal oxide film are performed as appropriate. There is.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、従来の半導体装置は、溝部2に埋め込ま
れた絶縁物3がシリコン基板1の表面と略同−面上にあ
るから、素子骨i%I tiI域が形成された後に行わ
れる素子形成過程において次のような問題点を生しる。
However, in the conventional semiconductor device, since the insulator 3 embedded in the groove 2 is substantially on the same plane as the surface of the silicon substrate 1, the element formation process is performed after the element bone i%I tiI region is formed. This causes the following problems.

例えば、ゲートを形成する工程や酸化膜エツチング残程
などにおいて、希釈したフッ化水素やフン化アンモニウ
ムによるエツチング処理が行われるが、溝部2に埋め込
まれたCVD酸化膜3.は、素子形成過程でシリコン基
板1に形成される熱酸化膜(図示せず)よりも前記エツ
チング処理液に対してエツチング速度が速いために、第
3図fb)に示したように、CVD酸化膜3Iがシリコ
ン基板1の表面よりも下に落ち込んでしまう、しかも、
このようにして生じた溝部2の段差は急峻なために、後
にゲート電極や配線を形成する際に、前記段差部に沿っ
てゲート電極材料や配線材料の残渣(エツチング残渣)
が生し易く、隣接配線間で短絡現象を引き起こすなどの
問題を生じる。
For example, in the step of forming a gate or the remaining oxide film etching process, etching treatment using diluted hydrogen fluoride or ammonium fluoride is performed. Since the etching rate of the etching solution is faster than that of the thermal oxide film (not shown) formed on the silicon substrate 1 during the device formation process, the CVD oxidation process is faster as shown in FIG. The film 3I falls below the surface of the silicon substrate 1, and
Since the step of the groove 2 created in this way is steep, when forming gate electrodes and wiring later, residues of gate electrode material and wiring material (etching residue) are left along the step.
This tends to cause problems such as short circuits between adjacent wirings.

この発明は、このような問題点を解決するためになされ
たものであって、ゲート電極や配線を形成する際に、絶
縁物が埋め込まれる溝部とシリコシ基板表面との境目に
エツチング残渣が生じにく゛い半導体装置と、その製造
方法を提供することを目的としている。
This invention has been made to solve these problems, and is aimed at preventing etching residue from being generated at the boundary between the trench where the insulator is buried and the surface of the silicon substrate when forming gate electrodes and wiring. The purpose is to provide a highly sophisticated semiconductor device and its manufacturing method.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、半導体基板に形成された
素子分離用の溝部に埋め込んで素子分離領域を形成する
絶縁物を、前記半導体基板の表面よりも突出させたもの
である。
In the semiconductor device according to the present invention, an insulator that is buried in a groove for element isolation formed in a semiconductor substrate to form an element isolation region protrudes from the surface of the semiconductor substrate.

また、この発明に係る半導体装置の製造方法は、半導体
基板に第1の絶縁膜を堆積させて、前記第1の絶縁膜を
通して半導体基板に素子分離用の溝部を形成し、前記溝
部に前記第1の絶縁膜とは異種の第2の絶縁膜を埋め込
むように堆積させた後、第2の絶縁膜が堆積された半導
体基板表面が平坦になるように前記第2の絶縁膜をその
表面から次第に除去し、下層の第1の絶縁膜に達したと
ころで前記除去処理を停止した後、前記第1の絶縁膜を
除去して半導体基板表面を露出させるものである。
Further, in the method for manufacturing a semiconductor device according to the present invention, a first insulating film is deposited on a semiconductor substrate, a trench for element isolation is formed in the semiconductor substrate through the first insulating film, and the first insulating film is formed in the trench. After depositing a second insulating film of a different type from the first insulating film so as to embed it, the second insulating film is deposited from the surface of the semiconductor substrate on which the second insulating film is deposited, so that the surface of the semiconductor substrate on which the second insulating film is deposited is flat. After gradually removing the semiconductor substrate and stopping the removal process when the lower first insulating film is reached, the first insulating film is removed to expose the surface of the semiconductor substrate.

〔作用〕[Effect]

この発明においては、溝部に埋め込まれた絶縁物を半導
体基板の表面よりも突出させて素子分離領域を形成して
いるから、後のエツチング処理によって絶縁物が多少エ
ツチングされても絶縁物が基板表面よりも落ち込むこと
がない。しかも、基板表面から突出した絶縁物の縁は前
記エツチング処理によって滑らかになり、ゲート電極や
配線形成工程においてエツチング残渣が生じにくくなる
In this invention, the insulating material embedded in the groove is made to protrude beyond the surface of the semiconductor substrate to form the element isolation region, so even if the insulating material is etched to some extent by the later etching process, the insulating material remains on the surface of the substrate. I'm never more depressed than I am. Moreover, the edges of the insulator protruding from the substrate surface are smoothed by the etching process, making it difficult for etching residues to form during the process of forming gate electrodes and wiring.

〔実施例〕〔Example〕

以下、この発明の実施例を図に基づいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は、この発明の一実施例の構成を示した半導体装
置の構成の概略を示した断面図である。
FIG. 1 is a sectional view schematically showing the structure of a semiconductor device showing the structure of an embodiment of the present invention.

同図において、第3図に示した従来例と同一符号は、同
一部分を示しているから、ここでの説明は省略する。
In this figure, the same reference numerals as those in the conventional example shown in FIG. 3 indicate the same parts, so the explanation here will be omitted.

第1図において、5は溝部2に埋め込まれた絶縁物であ
る。この絶縁物5は、前述した従来例の場合と同様に例
えば、CVD酸化膜によって形成されている。この絶縁
物5はシリコン基板1の表面よりも、例えば1000〜
5000人程度突出してい程度絶縁物5の突出高さは、
後の素子形成工程において施されるエツチング処理によ
って、絶縁物5がシリコン基板1の表面よりも下に落ち
込まない程度の高さに適宜に設定されるもであるから、
上記範囲内に限定されるものではない。
In FIG. 1, 5 is an insulator embedded in the groove 2. As shown in FIG. This insulator 5 is formed of, for example, a CVD oxide film, as in the case of the conventional example described above. This insulator 5 is, for example, 1000 to
The protruding height of the insulator 5 is about 5,000 people.
The etching process performed in the subsequent element forming step will appropriately set the height of the insulator 5 to such an extent that it will not fall below the surface of the silicon substrate 1.
It is not limited to the above range.

このように絶縁物5をシリコン基板1の表面よりも突出
させたから、後のエツチング処理によって絶縁物5が多
少エツチングされても、絶縁物5がシリコン基板1の表
面よりも落ち込むことはない。しかも、前記エツチング
処理によって絶縁物5の縁が滑らかになるから、ゲート
?it極や配線形成工程におけるエツチング処理の際に
エツチング残渣が生じにくくなる。
Since the insulator 5 is made to protrude above the surface of the silicon substrate 1 in this way, even if the insulator 5 is etched to some extent in the subsequent etching process, the insulator 5 will not fall below the surface of the silicon substrate 1. Moreover, since the edges of the insulator 5 are smoothed by the etching process, the edges of the insulator 5 are smoothed. Etching residues are less likely to be generated during etching in the IT electrode and wiring formation process.

次に上述した半導体装置の製造方法を第2図に従って説
明する。
Next, a method for manufacturing the above-mentioned semiconductor device will be explained with reference to FIG.

Calシリコン基板1上に、例えば数100人程0の薄
い熱酸化膜6と、第1の絶縁膜としての例えば数100
0人程度0比較的に厚い窒化膜7と、シリコン基板1を
エツチングする際のマスクとなる膜、例えばCVD酸化
膜8とをその順に形成する(第2図(al参照)。熱酸
化膜6は、後に窒化膜7を除去する際にシリコン基vi
、1の表面を保護するために設けられている。したがっ
て、窒化膜7を除去する際にシリコン基板1に与える損
傷が問題とならない場合には、熱酸化膜6を形成する必
要はない。
On the Cal silicon substrate 1, there is a thin thermal oxide film 6 with a thickness of, for example, several hundred layers, and a thin thermal oxide film 6 with a thickness of, for example, several hundred layers as a first insulating film.
A relatively thick nitride film 7 and a film to be used as a mask when etching the silicon substrate 1, for example, a CVD oxide film 8, are formed in that order (see FIG. 2 (al)).Thermal oxide film 6 When the nitride film 7 is removed later, the silicon base vi
, 1 is provided to protect the surfaces of the parts. Therefore, if damage to the silicon substrate 1 when removing the nitride film 7 is not a problem, there is no need to form the thermal oxide film 6.

(blフォトリソグラフィーによって前記熱酸化膜6、
窒化膜?、CVD酸化膜8をエツチングして、溝部を形
成する箇所に窓開けを行う(第2図(b)参照)。
(The thermal oxide film 6 is formed by BL photolithography,
Nitride film? , the CVD oxide film 8 is etched to form a window at the location where the groove will be formed (see FIG. 2(b)).

(c)窓開けされたCVD酸化膜8をマスクとして、異
方性イオンエツチング(RI E)によってシリコン基
板1に溝部2を形成する(第2図(C)参照)。
(c) Using the opened CVD oxide film 8 as a mask, a groove 2 is formed in the silicon substrate 1 by anisotropic ion etching (RIE) (see FIG. 2(C)).

fdl CV D酸化[8を除去した後、第2の絶縁膜
としての例えばCVD酸化膜5. (このCVD酸化膜
51は最終的に第1図に示した絶縁物5になる)を堆積
して、このCVD酸化膜51によって溝部2を埋め込む
(第2図[dl参照)。
fdl CVD oxidation [8] After removing the CVD oxide film 5.fdl, for example, a CVD oxide film 5. (This CVD oxide film 51 will eventually become the insulator 5 shown in FIG. 1) is deposited, and the trench 2 is filled with this CVD oxide film 51 (see FIG. 2 [dl]).

tel溝部2の窪みが表面にできるだけ現れないよう゛
にするために、CVD酸化膜5.の上にフォトレジスト
9を厚く塗布する(第2図(81参照)。
In order to prevent the depression of the tel groove 2 from appearing on the surface as much as possible, a CVD oxide film 5. A thick layer of photoresist 9 is applied over the photoresist (see FIG. 2 (81)).

fflこのフォトレジスト9とCVD酸化膜51 とが
ほぼ同じ速度でエツチングされるように、フォトレジス
ト9とCVD酸化膜51とを平坦にプラズマエツチング
して行き、窒化膜7に達したところでエツチング処理を
停止する(第2図(fl参照)。
fflThe photoresist 9 and the CVD oxide film 51 are plasma etched flatly so that the photoresist 9 and the CVD oxide film 51 are etched at approximately the same speed, and when the nitride film 7 is reached, the etching process is performed. Stop (see Figure 2 (fl)).

ここで、CVD酸化膜5.をエツチングするためのガス
に混合されるフォトレジストエツチング用の酸素ガスの
混合比を適宜に設定することによって、フォトレジスト
9とCVD酸化膜5.とのエツチング速度をほぼ同じに
することができる。また、エツチングが窒化膜7に達し
た場合に、窒化膜7が多少エツチングされて窒素ガスが
放出されるから、この窒素ガスを検出することによって
、前記エツチングが窒化膜7にまで達したことを知るこ
とができる。
Here, CVD oxide film 5. By appropriately setting the mixing ratio of the oxygen gas for photoresist etching, which is mixed with the gas for etching the photoresist 9 and the CVD oxide film 5. It is possible to make the etching speed almost the same. Furthermore, when the etching reaches the nitride film 7, the nitride film 7 is slightly etched and nitrogen gas is released, so by detecting this nitrogen gas, it can be confirmed that the etching has reached the nitride film 7. You can know.

[+窒化膜7を熱燐酸あるいはフラズマエッチングなど
によって除去する(第2図(a参照)。
[+The nitride film 7 is removed by hot phosphoric acid or plasma etching (see FIG. 2(a)).

[hlさらに、熱酸化膜6をエツチングしてシリコン基
板lの表面を露出させる(第2図(hl参照)。
[hl] Furthermore, the thermal oxide film 6 is etched to expose the surface of the silicon substrate 1 (see FIG. 2 (hl)).

これにより、同図に示したようにシリコン基板1の表面
から突出した絶縁物5を得ることができる。
Thereby, the insulator 5 protruding from the surface of the silicon substrate 1 can be obtained as shown in the figure.

ただし、窒化IPJ7の除去によって、絶縁物5をシリ
コン基板1の表面から突出させることができるから、こ
の熱酸化膜6の除去は必ずしも必要ではない。
However, since the insulator 5 can be made to protrude from the surface of the silicon substrate 1 by removing the nitrided IPJ 7, the removal of the thermal oxide film 6 is not necessarily necessary.

以上のようにして素子分離領域を形成した後に、各素子
領域に素子を形成して行く。
After forming the element isolation regions as described above, elements are formed in each element region.

なお、上述の実施例では、溝部2に埋め込まれたCVD
酸化膜5.のエッチバックを途中で止めるために窒化膜
7を用いたが、これはノンドープの多結晶シリコン膜な
どを用いてもよい。
In addition, in the above-mentioned embodiment, the CVD buried in the groove part 2
Oxide film 5. Although the nitride film 7 is used to stop the etch-back in the middle, a non-doped polycrystalline silicon film or the like may also be used.

また、上述の実施例では、フォトレジスト9とCVD酸
化膜5.とを同じ速度で平坦にエツチングする手段とし
てプラズマエツチングを用いたが、これは例えば研摩な
どによってフォトレジスト9とCVD酸化膜5.とを平
坦に除去するものであってもよい。
Further, in the above embodiment, the photoresist 9 and the CVD oxide film 5. Plasma etching was used as a means to flatten the photoresist 9 and the CVD oxide film 5. by polishing, for example. It may also be a method that flatly removes the .

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る半導体装置よれば、素子
分離用の溝部に埋め込まれる絶縁物を半導体基板表面よ
りも突出させたから、素子分’f=HeM域が形成され
た後の素子形成過程において施されるエツチング処理に
おいて、前記絶縁物が多少エツチングされても、この絶
縁物が半導体基板表面よりも下に落ち込むことがない。
As described above, according to the semiconductor device according to the present invention, since the insulator buried in the trench for element isolation is made to protrude from the surface of the semiconductor substrate, the element formation process after the element part 'f=HeM region is formed. Even if the insulating material is etched to some extent in the etching process performed in the etching process, the insulating material does not fall below the surface of the semiconductor substrate.

しかも、前記エンチング処理によって絶縁物の縁は滑ら
かになるから、ゲート電極や配線を形成するエツチング
の際に、前記ゲート電極材料や配線材料が絶縁物と半導
体基板表面との界面に残りにくくなり、これより半導体
装置の製造歩留りや信転性の向上を図ることができる。
Moreover, since the edges of the insulator are smoothed by the etching process, the gate electrode material and wiring material are less likely to remain at the interface between the insulator and the semiconductor substrate surface during etching to form gate electrodes and wiring. This makes it possible to improve the manufacturing yield and reliability of semiconductor devices.

また、この発明に係る半導体4A置の製造方法によれば
、前述した半導体装置を容易に実現することができる。
Further, according to the method for manufacturing a semiconductor 4A device according to the present invention, the above-described semiconductor device can be easily realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第10はこの発明に係る半導体装置の一実施例の構成の
概略を示した断面図、第2図はこの発明に係る半導体装
置の製造方法の一実施例の説明図、第3図は従来例の半
導体装置の構成の概略を示した断面図、第4図は従来例
の半導体装置の製造方法の説明図である。 図において、1はシリコン基七反、2番よ18合b、5
は絶縁物、51はCVD酸化膜、7むよ窒イヒlI豪で
ある。 なお、図中同一符号は同一または相当05分を示す。
10 is a sectional view schematically showing the configuration of an embodiment of a semiconductor device according to the present invention, FIG. 2 is an explanatory diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 3 is a conventional example. FIG. 4 is a cross-sectional view schematically showing the structure of a semiconductor device, and FIG. 4 is an explanatory diagram of a conventional method of manufacturing a semiconductor device. In the figure, number 1 is silicon base seven, number 2 is number 18, number 5 is
51 is an insulator, 51 is a CVD oxide film, and 7 is a nitride film. Note that the same reference numerals in the figure indicate the same or equivalent 05 minutes.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板に形成された素子分離用の溝部に絶縁
物を埋め込んだ素子分離領域を備えた半導体装置におい
て、前記絶縁物を前記半導体基板の表面よりも突出させ
たことを特徴とする半導体装置。
(1) A semiconductor device including an element isolation region in which an insulator is embedded in an element isolation groove formed in a semiconductor substrate, wherein the insulator is made to protrude beyond the surface of the semiconductor substrate. Device.
(2)半導体基板に第1の絶縁膜を堆積させる工程と、 前記第1の絶縁膜を通して半導体基板に素子分離用の溝
部を形成させる工程と、 前記溝部に前記第1の絶縁膜とは異種の第2の絶縁膜を
埋め込むように堆積させる工程と、前記第2の絶縁膜が
堆積された半導体基板表面が平坦になるように前記第2
の絶縁膜をその表面から次第に除去し、下層の第1の絶
縁膜に達したところで前記除去処理を停止する工程と、 前記第1の絶縁膜を除去する工程とを備えたことを特徴
とする半導体装置の製造方法。
(2) a step of depositing a first insulating film on a semiconductor substrate; a step of forming a trench for element isolation in the semiconductor substrate through the first insulating film; and a step of depositing a first insulating film on the semiconductor substrate; a step of depositing a second insulating film so as to embed the second insulating film;
The method is characterized by comprising the steps of: gradually removing the insulating film from the surface thereof and stopping the removal process when reaching the underlying first insulating film; and removing the first insulating film. A method for manufacturing a semiconductor device.
JP9271087A 1987-04-14 1987-04-14 Semiconductor device and manufacture thereof Pending JPS63257244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9271087A JPS63257244A (en) 1987-04-14 1987-04-14 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9271087A JPS63257244A (en) 1987-04-14 1987-04-14 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS63257244A true JPS63257244A (en) 1988-10-25

Family

ID=14062021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9271087A Pending JPS63257244A (en) 1987-04-14 1987-04-14 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS63257244A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
JP2007081358A (en) * 2005-09-14 2007-03-29 Magnachip Semiconductor Ltd Cmos image sensor and its manufacture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229316A (en) * 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
DE4310954A1 (en) * 1992-04-16 1993-10-21 Micron Technology Inc Semiconductor processing method for producing an isolation trench in a substrate
DE4310954C2 (en) * 1992-04-16 1998-07-16 Micron Technology Inc Semiconductor processing method for producing an isolation trench in a substrate
JP2007081358A (en) * 2005-09-14 2007-03-29 Magnachip Semiconductor Ltd Cmos image sensor and its manufacture
US8120062B2 (en) 2005-09-14 2012-02-21 Intellectual Ventures Ii Llc Complementary metal oxide semiconductor image sensor and method for fabricating the same
US8815628B2 (en) 2005-09-14 2014-08-26 Intellectual Ventures Ii Llc Complementary metal oxide semiconductor image sensor and method for fabricating the same

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