JPH0923001A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0923001A JPH0923001A JP7169125A JP16912595A JPH0923001A JP H0923001 A JPH0923001 A JP H0923001A JP 7169125 A JP7169125 A JP 7169125A JP 16912595 A JP16912595 A JP 16912595A JP H0923001 A JPH0923001 A JP H0923001A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- forming
- base layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 77
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000007772 electrode material Substances 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 18
- 238000002161 passivation Methods 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000992 sputter etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- -1 Phospho Chemical class 0.000 description 1
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に縦型ＭＯＳ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｉ
ｌｉｃｏｎ）の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a vertical MOS (Metal Oxide Si).
licon).
【０００２】[0002]
【従来の技術】従来、この種の製造方法としては、図４
及び図５に示すように、ｎ／ｎ+ エピ（１００）、比抵
抗０．６〜２．０（Ω・ｃｍ）、エピ厚１０μｍを使用
し、ベース領域３にはボロン（Ｂｏｒｏｎ：ホウ素）を
ドーズ量７×１０13ｃｍ-2、加速電圧１００ｋｅＶの条
件でイオン注入し、拡散長２μｍとなるように拡散して
いる。2. Description of the Related Art Conventionally, as a manufacturing method of this kind, FIG.
And, as shown in FIG. 5, n / n + epi (100), specific resistance 0.6 to 2.0 (Ω · cm), epi thickness 10 μm are used, and boron (Boron) is used for the base region 3. Is ion-implanted under the conditions of a dose amount of 7 × 10 13 cm −2 and an acceleration voltage of 100 keV, and diffused so that the diffusion length becomes 2 μm.
【０００３】また、ｎ+ ソース領域４にはヒ素をドーズ
量２×１０15ｃｍ-2、加速電圧４０ｋｅＶで、ソースの
コンタクト部をマスクした状態で注入し、拡散長０．４
μｍとなるように拡散している。Further, arsenic is implanted into the n + source region 4 at a dose amount of 2 × 10 15 cm -2 and an acceleration voltage of 40 keV while the source contact portion is masked, and the diffusion length is 0.4.
It is diffused so that it becomes μm.
【０００４】垂直溝１４はＲＩＥ（Ｒｅａｃｔｉｖｅ
Ｉｏｎ Ｅｔｃｈｉｎｇ）、ＳＦ6＋ＣＣｌ4 混合ガス
を使用し、圧力１００ｍＴｏｒｒの条件で深さ４μｍに
達するまでエッチングする。また、ゲート部の汚染層や
ダメージ領域を除去するための軽いウェットエッチング
を追加する［図４（ａ）参照］。The vertical groove 14 is formed by RIE (Reactive).
Ion Etching) and SF6 + CCl4 mixed gas are used, and etching is performed at a pressure of 100 mTorr until a depth of 4 .mu.m is reached. In addition, light wet etching is added to remove the contaminated layer and the damaged region of the gate portion [see FIG. 4 (a)].
【０００５】この上に、ゲート酸化膜１３を６５０Å成
長させた後に、ポリシリコン６を減圧ＣＶＤ（Ｃｈｅｍ
ｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）によっ
て５０００Å成長させ、リンドープした後にポリシリコ
ン６表面に酸化膜１３を薄く成長させる［図４（ｂ）参
照］。After the gate oxide film 13 is grown on this by 650Å, the polysilicon 6 is decompressed by CVD (Chem).
Then, the oxide film 13 is grown thinly on the surface of the polysilicon 6 after the growth of 5000Å by the chemical vapor deposition) and phosphorus doping [see FIG. 4 (b)].
【０００６】続いて、垂直溝１４の充填用の第２ポリシ
リコン１５を２．０μｍ成長させて垂直溝１４を完全に
埋め込んだ後に［図４（ｃ）参照］、全面ポリシリコン
エッチバックで垂直溝１４の部分以外の領域のポリシリ
コン１５を除去する［図５（ａ）参照］。ここで、第１
ポリシリコン６上の薄い酸化膜１３は第１ポリシリコン
６へのオーバエッチングのストッパの役割を持ってい
る。Subsequently, a second polysilicon 15 for filling the vertical groove 14 is grown to 2.0 μm to completely fill the vertical groove 14 [see FIG. 4 (c)], and then the entire surface is etched back by a polysilicon etch. The polysilicon 15 in the region other than the groove 14 is removed [see FIG. 5 (a)]. Here, the first
The thin oxide film 13 on the polysilicon 6 serves as a stopper for over-etching the first polysilicon 6.
【０００７】ゲート電極６のパターニングの後、層間絶
縁膜７としてリン濃度８％のＰＳＧ（Ｐｈｏｓｐｈｏ
Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）膜を５０００Å成長さ
せ、１００℃、Ｈ2 ＋Ｏ2 雰囲気中でリフローし、ステ
ップ被覆性の向上を図る［図５（ｂ）参照］。After patterning the gate electrode 6, PSG (Phospho) having a phosphorus concentration of 8% is formed as an interlayer insulating film 7.
A Silicate Glass) film is grown at 5000Å and reflowed at 100 ° C. in an H 2 + O 2 atmosphere to improve the step coverage (see FIG. 5B).
【０００８】また、コンタクトホール形成後、ＤＣマグ
ネトロンスパッタ（ＤｉｒｅｃｔＣｕｒｒｅｎｔ Ｍａ
ｇｎｅｔｒｏｎ Ｓｐｕｔｔｅｒｉｎｇ）によって２μ
ｍのＡｌ−Ｓｉ−Ｃｕ８をデポし、ソース及びゲート電
極を形成する［図５（ｃ）参照］。表面のパッシベーシ
ョン膜（図示せず）にはプラズマＳｉＮ膜を使用してい
る。After the contact hole is formed, DC magnetron sputtering (Direct Current Ma) is performed.
2μ by gnetron Sputtering)
m Al-Si-Cu8 is deposited to form the source and gate electrodes [see FIG. 5 (c)]. A plasma SiN film is used for the passivation film (not shown) on the surface.
【０００９】尚、上記の半導体装置の製造方法について
は、「超低イオン抵抗ＲＭＯＳＦＥＴ」（上田大助他
著、Ｎａｔｉｏｎａｌ Ｔｅｃｈｎｉｃａｌ Ｒｅｐｏ
ｒｔＶｏｌ．３２、Ｎｏ．２、Ａｐｒ．１９８６）に詳
述されている。Regarding the method of manufacturing the above semiconductor device, "Ultra-low ion resistance RMOSFET" (Dasuke Ueda et al., National Technical Report).
rtVol. 32, no. 2, Apr. 1986).
【００１０】[0010]
【発明が解決しようとする課題】近年、半導体全般にコ
ストダウンが求められており、同じ構造の半導体であれ
ばいかに少ない工程でその半導体を実現するかが重要に
なっている。In recent years, cost reduction has been demanded for semiconductors in general, and it is important to realize the semiconductor with the same structure in a small number of steps.
【００１１】上述した従来の半導体装置の製造方法で
は、ソース領域形成時にベース層とコンタクトをとる部
分をマスクしているためにパターニングの工程が必要と
なり、この場合にはパターニングの工程をなくすことは
できない。In the above-described conventional method for manufacturing a semiconductor device, a patterning step is required because the portion that makes contact with the base layer when forming the source region is masked. In this case, the patterning step can be eliminated. Can not.
【００１２】これを解決するために、ソース領域を基板
全面に形成し、コンタクト形成時にベース層までシリコ
ンをエッチングする方法も考えられる。しかしながら、
ベース層までシリコンをエッチングしようとするとゲー
ト電極のポリシリコンも一緒にエッチングされるため、
ベース層までのコンタクトをゲート電極のコンタクトと
は別に形成するか、あるいはゲート電極の大きさや深さ
をエッチングされても支障のないサイズにしなければな
らない。In order to solve this, a method of forming a source region on the entire surface of the substrate and etching silicon up to the base layer at the time of forming a contact can be considered. However,
When attempting to etch silicon up to the base layer, the polysilicon of the gate electrode is also etched, so
The contact to the base layer must be formed separately from the contact of the gate electrode, or the size and depth of the gate electrode must be sized so as not to interfere with etching.
【００１３】そこで、本発明の目的は上記の問題点を解
消し、同一構造の半導体装置の製造において工程数を削
減することができ、コストダウンを図ることができる半
導体装置の製造方法を提供することにある。Therefore, an object of the present invention is to solve the above problems and to provide a method of manufacturing a semiconductor device which can reduce the number of steps in manufacturing a semiconductor device having the same structure and can reduce the cost. Especially.
【００１４】[0014]
【課題を解決するための手段】本発明による半導体装置
の製造方法は、基板上全面にベース層を形成する工程
と、前記ベース層上全面に前記ベース層よりも薄くソー
ス層を形成する工程と、前記ベース層及び前記ソース層
を貫通する溝を形成して前記ソース層の表面と前記溝の
表面及び側壁面に夫々ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極材料を積層して前記溝
を埋め込む工程と、前記ゲート電極材料をパターニング
してゲート電極を形成する工程と、前記ゲート絶縁膜及
び前記ゲート電極上に層間絶縁膜を積層する工程と、前
記層間絶縁膜及び前記ゲート絶縁膜をエッチングして前
記ベース層及び前記ゲート電極へのコンタクトホールを
形成する工程とを備えている。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a base layer on the entire surface of a substrate, and a step of forming a source layer thinner than the base layer on the entire surface of the base layer. Forming a groove penetrating the base layer and the source layer and forming a gate insulating film on the surface of the source layer, the surface of the groove, and the side wall surface, respectively.
Stacking a gate electrode material on the gate insulating film to fill the groove; patterning the gate electrode material to form a gate electrode; forming an interlayer insulating film on the gate insulating film and the gate electrode; And a step of forming a contact hole to the base layer and the gate electrode by etching the interlayer insulating film and the gate insulating film.
【００１５】本発明による他の半導体装置の製造方法
は、上記の構成のほかに、前記コンタクトホールを形成
した後に全面にボロンを注入する工程を具備している。Another method of manufacturing a semiconductor device according to the present invention comprises, in addition to the above structure, a step of implanting boron over the entire surface after forming the contact hole.
【００１６】本発明による別の半導体装置の製造方法
は、上記の構成のほかに、基板上全面にベース層を形成
する工程と、前記ベース層上全面に前記ベース層よりも
薄くソース層を形成する工程と、前記ベース層及び前記
ソース層を貫通する溝を形成して前記ソース層の表面と
前記溝の表面及び側壁面に夫々ゲート絶縁膜を形成する
工程と、前記ゲート絶縁膜上にゲート電極材料を積層し
て前記溝を埋め込む工程と、前記ゲート絶縁膜上に積層
した前記ゲート電極材料を熱処理で溶融して前記溝に集
中的に流し込むことでゲート電極を自己形成する工程
と、前記ゲート絶縁膜及び前記ゲート電極上に層間絶縁
膜を積層する工程と、前記層間絶縁膜及び前記ゲート絶
縁膜をエッチングして前記ベース層及び前記ゲート電極
へのコンタクトホールを形成する工程とを具備してい
る。In addition to the above structure, another method of manufacturing a semiconductor device according to the present invention is a step of forming a base layer on the entire surface of the substrate, and forming a source layer thinner than the base layer on the entire surface of the base layer. A step of forming a groove penetrating the base layer and the source layer to form a gate insulating film on the surface of the source layer, the surface of the groove and the sidewall surface, respectively, and a gate on the gate insulating film. Stacking an electrode material to fill the groove; forming the gate electrode by melting the gate electrode material stacked on the gate insulating film by heat treatment and pouring the material into the groove in a concentrated manner; Stacking an interlayer insulating film on the gate insulating film and the gate electrode, and contact holes to the base layer and the gate electrode by etching the interlayer insulating film and the gate insulating film Is a step of forming.
【００１７】本発明によるさらに別の半導体装置の製造
方法は、上記の構成のほかに、前記コンタクトホールを
形成した後に全面にボロンを注入する工程を具備してい
る。Still another semiconductor device manufacturing method according to the present invention comprises, in addition to the above structure, a step of implanting boron over the entire surface after forming the contact hole.
【００１８】[0018]
【作用】基板上全面にベース層を形成し、その上にソー
ス層を形成した後にベース層及びソース層を貫通する垂
直溝を形成してソース層の表面と垂直溝の表面及び側壁
面に夫々ゲート絶縁膜を形成する。A base layer is formed on the entire surface of a substrate, a source layer is formed on the base layer, and then vertical grooves penetrating the base layer and the source layer are formed to form a surface of the source layer, a surface of the vertical groove, and a side wall surface, respectively. A gate insulating film is formed.
【００１９】そのゲート絶縁膜上にゲート電極の材料を
積層して垂直溝を埋め込んでゲート電極を形成するとと
もに、ゲート絶縁膜及びゲート電極上に層間絶縁膜を積
層してからエッチングでベース層及びゲート電極へのコ
ンタクトホールを形成する。The gate electrode material is laminated on the gate insulating film to fill the vertical groove to form the gate electrode, and the gate insulating film and the interlayer insulating film are laminated on the gate electrode, and then the base layer and the base layer are formed by etching. A contact hole to the gate electrode is formed.
【００２０】これによって、ソース領域形成時にベース
層とコンタクトをとる部分をマスクしてパターニングす
るという工程が不要となるので、フォトマスクを用いた
パターニング工程を４工程に減らすことができる。As a result, the step of patterning by masking the portion that comes into contact with the base layer when forming the source region is not required, and the patterning step using the photomask can be reduced to four steps.
【００２１】よって、同一構造の半導体装置の製造にお
いて工程数の削減が可能となる。同時に、パターニング
工程で用いるガラスマスクも減らすことができるので、
コストダウンを図ることが可能となる。Therefore, it is possible to reduce the number of steps in manufacturing semiconductor devices having the same structure. At the same time, the number of glass masks used in the patterning process can be reduced,
Costs can be reduced.
【００２２】この場合、ゲート電極にはシリコンとの選
択比が大きいアルミニウム等を用いているので、ベース
層までシリコンをエッチングする場合にもシリコンと一
緒にエッチングされることはない。よって、ベース層ま
でのコンタクトホールをゲート電極のコンタクトホール
とは別に形成する必要はなく、ゲート電極の大きさや深
さをエッチングされても支障のないサイズにする必要も
ない。In this case, since the gate electrode is made of aluminum or the like having a large selection ratio with respect to silicon, it is not etched together with silicon even when the silicon is etched up to the base layer. Therefore, it is not necessary to form the contact hole up to the base layer separately from the contact hole for the gate electrode, and it is not necessary to make the size and depth of the gate electrode a size that does not hinder the etching.
【００２３】[0023]
【実施例】次に、本発明の一実施例について図面を参照
して説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【００２４】図１及び図２は本発明の一実施例による半
導体装置の製造工程を示す各工程の断面図である。これ
ら図１及び図２を用いて本発明の一実施例による半導体
装置の製造工程について説明する。1 and 2 are cross-sectional views showing the steps of manufacturing a semiconductor device according to an embodiment of the present invention. The manufacturing process of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
【００２５】Ｎ+ 基板１（１００）［比抵抗０．００２
〜０．００６（Ω・ｃｍ）］にＮ-エピ２［比抵抗０．
６〜１．０（Ω・ｃｍ）、厚さ８μｍ］を成長させたウ
ェハを使用し、全面にボロンを注入して拡散深さ１．５
〜２．０μｍとなるような熱処理を行い、ベース層３を
形成する。その後に、全面にヒ素を注入して拡散深さ
０．４〜０．６μｍとなるような熱処理を行い、ソース
層４を形成する［図１（ａ）参照］。N + substrate 1 (100) [specific resistance 0.002
~0.006 (Ω · cm)] in N - epi 2 [specific resistance 0.
6-1.0 (Ω · cm), thickness of 8 μm] is used, and boron is implanted over the entire surface to obtain a diffusion depth of 1.5.
The base layer 3 is formed by performing heat treatment such that the thickness is about 2.0 μm. After that, arsenic is implanted into the entire surface and heat treatment is performed so that the diffusion depth is 0.4 to 0.6 μm, and the source layer 4 is formed [see FIG. 1 (a)].
【００２６】ソース層４を形成した後に、垂直溝をイオ
ンエッチングにてＮ+ ソース４及びＰベース３を貫いて
Ｎ- エピ２に到達する深さとなるように形成する。その
上にゲート酸化膜５を成長させ、さらにその上にアルミ
ニウムを積層する。積層したアルミニウムを熱処理によ
って垂直溝に埋め込み、ゲート電極６を形成する［図１
（ｂ）及び図１（ｃ）参照］。After forming the source layer 4, a vertical groove is formed by ion etching so as to reach the N - epi 2 through the N + source 4 and the P base 3. A gate oxide film 5 is grown on it, and aluminum is further stacked thereon. The laminated aluminum is buried in the vertical groove by heat treatment to form the gate electrode 6 [FIG.
(B) and FIG. 1 (c)].
【００２７】これらゲート酸化膜５及びゲート電極６の
上に層間絶縁膜７を積層した後に、イオンエッチングに
てベース層３及びゲート電極６まで届くコンタクトホー
ルを形成する［図２（ａ）参照］。この場合、ゲート電
極６にはシリコンとの選択比が大きい、つまりシリコン
のエッチングレートとの差が大きいエッチングレートの
アルミニウムを用いているので、シリコンをエッチング
してコンタクトホールを形成する場合でもゲート電極６
がエッチングされることはない。After laminating the interlayer insulating film 7 on the gate oxide film 5 and the gate electrode 6, a contact hole reaching the base layer 3 and the gate electrode 6 is formed by ion etching [see FIG. 2 (a)]. . In this case, since the gate electrode 6 is made of aluminum having a large selection ratio with respect to silicon, that is, an etching rate having a large difference from the etching rate of silicon, even when the silicon is etched to form the contact hole, the gate electrode 6 is formed. 6
Is not etched.
【００２８】これらコンタクトホールを埋め込むよう
に、アルミリフロースパッタにて配線アルミ８を積層
し、この配線アルミ８をパターニングした後にＳｉＮ膜
をパッシベーション膜９として積層する［図２（ｂ）参
照］。Wiring aluminum 8 is laminated by aluminum reflow sputtering so as to fill these contact holes, and after patterning the wiring aluminum 8, a SiN film is laminated as a passivation film 9 [see FIG. 2 (b)].
【００２９】上記の製造方法によれば、フォトリソグラ
フィ技術を用いたパターニングが４回のみとなり、半導
体装置の製造工程の短縮及びパターニングに用いるマス
クを削減することができる。According to the above manufacturing method, the patterning using the photolithography technique is performed only four times, so that the manufacturing process of the semiconductor device can be shortened and the mask used for the patterning can be reduced.
【００３０】層間絶縁膜７を形成する前の状態は表面に
ほとんど段差がないので、層間絶縁膜７の形成後に熱処
理によるリフローを行う必要がない。また、ゲート電極
６の形成後に不純物の活性化や層間絶縁膜７のリフロー
等の高温の熱処理が不要となるので、ゲート電極６の材
料としてアルミニウム等の低融点金属を用いることがで
き、ゲート電極６にアルミニウムを用いることでポリシ
リコンに比べて大幅にゲート抵抗を低減することが可能
となる。尚、ゲート電極６の材料としてはアルミニウム
の他にＷ、Ｔｉ、Ａｎ等を用いることができる。Since there is almost no step on the surface before the interlayer insulating film 7 is formed, it is not necessary to perform reflow by heat treatment after forming the interlayer insulating film 7. Further, since high temperature heat treatment such as activation of impurities and reflow of the interlayer insulating film 7 is not required after the formation of the gate electrode 6, a low melting point metal such as aluminum can be used as the material of the gate electrode 6, By using aluminum for 6, it becomes possible to significantly reduce the gate resistance as compared with polysilicon. As the material of the gate electrode 6, W, Ti, An or the like can be used in addition to aluminum.
【００３１】図３は本発明の他の実施例による半導体装
置の製造工程を示す各工程の断面図である。この図３を
用いて本発明の他の実施例による半導体装置の製造工程
について説明する。3A to 3D are sectional views showing the steps of manufacturing a semiconductor device according to another embodiment of the present invention. A manufacturing process of a semiconductor device according to another embodiment of the present invention will be described with reference to FIG.
【００３２】本発明の他の実施例では上記のゲート酸化
膜５の成長後にポリシリコン１０を積層し、リン拡散を
行った後にＷＳｉを積層して垂直溝を埋め込み、エッチ
バックによってゲート電極（ポリシリコン）１０，及び
ゲート電極（ＷＳｉ）１１を形成する［図３（ａ）参
照］。In another embodiment of the present invention, polysilicon 10 is laminated after the gate oxide film 5 is grown, phosphorus is diffused and then WSi is laminated to fill a vertical groove, and a gate electrode (polysilicon) is formed by etching back. Silicon) 10 and gate electrode (WSi) 11 are formed [see FIG. 3 (a)].
【００３３】これらゲート酸化膜５及びゲート電極１
０，１１の上に層間絶縁膜７を積層した後に、イオンエ
ッチングにてベース層３及びゲート電極１１まで届くコ
ンタクトホールを形成する。その後に、全面にボロンを
注入することで、ベース層３にＰ+ 拡散領域１２が形成
されるのでベース層３とのコンタクト抵抗を低減するこ
とができる［図３（ｂ）参照］。このとき、ゲート電極
１１に届くコンタクトホールのコンタクト部分にもボロ
ンが注入されるが、ゲート電極１１の表面はＷＳｉであ
るため、ボロンによる影響を受けることはない。These gate oxide film 5 and gate electrode 1
After laminating the interlayer insulating film 7 on the layers 0 and 11, a contact hole reaching the base layer 3 and the gate electrode 11 is formed by ion etching. After that, by implanting boron over the entire surface, the P + diffusion region 12 is formed in the base layer 3, so that the contact resistance with the base layer 3 can be reduced [see FIG. 3 (b)]. At this time, boron is also injected into the contact portion of the contact hole reaching the gate electrode 11, but since the surface of the gate electrode 11 is WSi, it is not affected by boron.
【００３４】これらコンタクトホールを埋め込むように
配線アルミ８を積層し、この配線アルミ８をパターニン
グした後にＳｉＮ膜をパッシベーション膜９として積層
する［図３（ｃ）参照］。これによって、上記の製造方
法でも、フォトリソグラフィ技術を用いたパターニング
の回数が減るので、半導体装置の製造工程の短縮及びパ
ターニングに用いるマスクを削減することができる。A wiring aluminum 8 is laminated so as to fill these contact holes, the wiring aluminum 8 is patterned, and then a SiN film is laminated as a passivation film 9 [see FIG. 3 (c)]. As a result, even in the above manufacturing method, the number of times of patterning using the photolithography technique is reduced, so that it is possible to shorten the manufacturing process of the semiconductor device and reduce the mask used for patterning.
【００３５】このように、基板上全面にベース層３及び
ソース層４を形成した後にベース層３及びソース層４を
貫通する垂直溝を形成してソース層４の表面と垂直溝の
表面及び側壁面に夫々ゲート絶縁膜５を形成し、そのゲ
ート絶縁膜５上にゲート電極６，１０，１１の材料を積
層して垂直溝を埋め込んでゲート電極６，１０，１１を
形成するとともに、ゲート絶縁膜５及びゲート電極６，
１０，１１上に層間絶縁膜７を積層してからエッチング
でベース層３及びゲート電極６，１１へのコンタクトホ
ールを形成することによって、ソース領域形成時にベー
ス層３とコンタクトをとる部分をマスクしてパターニン
グするという工程が不要となるので、フォトマスクを用
いたパターニング工程を４工程に減らすことができる。In this way, after the base layer 3 and the source layer 4 are formed on the entire surface of the substrate, vertical grooves penetrating the base layer 3 and the source layer 4 are formed to form the surface of the source layer 4 and the surface and side of the vertical groove. Gate insulating films 5 are formed on the wall surfaces, and the materials for the gate electrodes 6, 10 and 11 are stacked on the gate insulating films 5 to fill the vertical grooves to form the gate electrodes 6, 10 and 11, and the gate insulating film 5 is formed. Film 5 and gate electrode 6,
By forming the interlayer insulating film 7 on the layers 10 and 11 and then forming contact holes to the base layer 3 and the gate electrodes 6 and 11 by etching, the portions that make contact with the base layer 3 when the source region is formed are masked. Since the step of patterning is not necessary, the patterning step using the photomask can be reduced to four steps.
【００３６】よって、同一構造の半導体装置の製造にお
いて工程数を削減することができる。同時に、パターニ
ング工程で用いるガラスマスクも減らすことができるの
で、コストダウンを図ることができる。Therefore, it is possible to reduce the number of steps in manufacturing semiconductor devices having the same structure. At the same time, the number of glass masks used in the patterning process can be reduced, so that the cost can be reduced.
【００３７】この場合、ゲート電極６，１１にはシリコ
ンとの選択比が大きいアルミニウム等を用いているの
で、ベース層３までシリコンをエッチングする場合にも
シリコンと一緒にエッチングされることはない。よっ
て、ベース層３までのコンタクトホールをゲート電極
６，１１のコンタクトホールとは別に形成する必要はな
く、ゲート電極６，１１の大きさや深さをエッチングさ
れても支障のないサイズにする必要もない。In this case, since the gate electrodes 6 and 11 are made of aluminum or the like having a large selection ratio with respect to silicon, even when the silicon is etched up to the base layer 3, it is not etched together with the silicon. Therefore, it is not necessary to form the contact hole up to the base layer 3 separately from the contact holes of the gate electrodes 6 and 11, and it is also necessary to make the size and depth of the gate electrodes 6 and 11 such that etching does not cause any trouble. Absent.
【００３８】[0038]
【発明の効果】以上説明したように本発明によれば、基
板上全面に形成したベース層及びソース層を貫通する溝
を形成し、ソース層の表面と溝の表面及び側壁面に夫々
ゲート絶縁膜を形成してからゲート絶縁膜上にゲート電
極材料を積層して溝を埋め込んでゲート電極を形成する
とともに、ゲート絶縁膜及びゲート電極上に層間絶縁膜
を積層した後に層間絶縁膜及びゲート絶縁膜をエッチン
グしてベース層及びゲート電極へのコンタクトホールを
形成することによって、同一構造の半導体装置の製造に
おいて工程数を削減することができ、コストダウンを図
ることができるという効果がある。As described above, according to the present invention, a groove penetrating the base layer and the source layer formed on the entire surface of the substrate is formed, and the gate insulation is formed on the surface of the source layer, the surface of the groove, and the side wall surface, respectively. After forming the film, the gate electrode material is laminated on the gate insulating film to fill the groove to form the gate electrode, and the gate insulating film and the interlayer insulating film are laminated on the gate electrode and then the interlayer insulating film and the gate insulating film. By etching the film to form the contact holes to the base layer and the gate electrode, it is possible to reduce the number of steps in manufacturing a semiconductor device having the same structure, and it is possible to achieve cost reduction.
【図１】本発明の一実施例による半導体装置の製造工程
を示す各工程の断面図である。FIG. 1 is a cross-sectional view of each process showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例による半導体装置の製造工程
を示す各工程の断面図である。FIG. 2 is a sectional view of each step showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図３】本発明の他の実施例による半導体装置の製造工
程を示す各工程の断面図である。FIG. 3 is a cross-sectional view of each process showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.
【図４】従来例による半導体装置の製造工程を示す各工
程の断面図である。FIG. 4 is a sectional view of each step showing the manufacturing process of the semiconductor device according to the conventional example.
【図５】従来例による半導体装置の製造工程を示す各工
程の断面図である。FIG. 5 is a sectional view of each step showing the manufacturing process of the semiconductor device according to the conventional example.
３ ベース層 ４ ソース層 ５ ゲート酸化膜 ６ ゲート電極 ７ 層間絶縁膜 ８ 配線アルミ ９ パッシベーション膜 １０ ゲート電極（ポリシリコン） １１ ゲート電極（ＷＳｉ） １２ Ｐ+ 拡散領域3 Base Layer 4 Source Layer 5 Gate Oxide Film 6 Gate Electrode 7 Interlayer Insulation Film 8 Wiring Aluminum 9 Passivation Film 10 Gate Electrode (Polysilicon) 11 Gate Electrode (WSi) 12 P + Diffusion Region
Claims (8)
と、前記ベース層上全面に前記ベース層よりも薄くソー
ス層を形成する工程と、前記ベース層及び前記ソース層
を貫通する溝を形成して前記ソース層の表面と前記溝の
表面及び側壁面に夫々ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極材料を積層して前記溝
を埋め込む工程と、前記ゲート電極材料をパターニング
してゲート電極を形成する工程と、前記ゲート絶縁膜及
び前記ゲート電極上に層間絶縁膜を積層する工程と、前
記層間絶縁膜及び前記ゲート絶縁膜をエッチングして前
記ベース層及び前記ゲート電極へのコンタクトホールを
形成する工程とを有することを特徴とする半導体装置の
製造方法。1. A step of forming a base layer on the entire surface of a substrate, a step of forming a source layer thinner than the base layer on the entire surface of the base layer, and forming a groove penetrating the base layer and the source layer. And forming a gate insulating film on the surface of the source layer, the surface of the groove, and the sidewall surface, respectively,
Stacking a gate electrode material on the gate insulating film to fill the groove; patterning the gate electrode material to form a gate electrode; forming an interlayer insulating film on the gate insulating film and the gate electrode; A method of manufacturing a semiconductor device, comprising: a step of stacking; and a step of etching the interlayer insulating film and the gate insulating film to form contact holes to the base layer and the gate electrode.
面にボロンを注入する工程を含むことを特徴とする請求
項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of implanting boron over the entire surface after forming the contact hole.
ホールの形成時にシリコンとの選択比が大きくかつエッ
チングされない材料からなることを特徴とする請求項１
または請求項２記載の半導体装置の製造方法。3. The gate electrode material is made of a material that has a large selection ratio with silicon and is not etched when the contact hole is formed.
A method for manufacturing a semiconductor device according to claim 2.
点の金属材料からなることを特徴とする請求項１から請
求項３のいずれか記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode material is a metal material having a low resistance and a low melting point.
と、前記ベース層上全面に前記ベース層よりも薄くソー
ス層を形成する工程と、前記ベース層及び前記ソース層
を貫通する溝を形成して前記ソース層の表面と前記溝の
表面及び側壁面に夫々ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極材料を積層して前記溝
を埋め込む工程と、前記ゲート絶縁膜上に積層した前記
ゲート電極材料を熱処理で溶融して前記溝に集中的に流
し込むことでゲート電極を自己形成する工程と、前記ゲ
ート絶縁膜及び前記ゲート電極上に層間絶縁膜を積層す
る工程と、前記層間絶縁膜及び前記ゲート絶縁膜をエッ
チングして前記ベース層及び前記ゲート電極へのコンタ
クトホールを形成する工程とを有することを特徴とする
半導体装置の製造方法。5. A step of forming a base layer on the entire surface of a substrate, a step of forming a source layer thinner than the base layer on the entire surface of the base layer, and forming a groove penetrating the base layer and the source layer. And forming a gate insulating film on the surface of the source layer, the surface of the groove, and the sidewall surface, respectively,
A step of stacking a gate electrode material on the gate insulating film to fill the groove, and a step of melting the gate electrode material stacked on the gate insulating film by heat treatment and pouring the material into the groove in a concentrated manner. A step of self-forming, a step of stacking an interlayer insulating film on the gate insulating film and the gate electrode, and a step of etching the interlayer insulating film and the gate insulating film to form contact holes to the base layer and the gate electrode. And a step of forming the semiconductor device.
面にボロンを注入する工程を含むことを特徴とする請求
項５記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of implanting boron on the entire surface after forming the contact hole.
ホールの形成時にシリコンとの選択比が大きくかつエッ
チングされない材料からなることを特徴とする請求項５
または請求項６記載の半導体装置の製造方法。7. The gate electrode material is made of a material that has a large selection ratio with respect to silicon and is not etched when the contact hole is formed.
7. A method for manufacturing a semiconductor device according to claim 6.
点の金属材料からなることを特徴とする請求項５から請
求項７のいずれか記載の半導体装置の製造方法。8. The method of manufacturing a semiconductor device according to claim 5, wherein the gate electrode material is made of a metal material having a low resistance and a low melting point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16912595A JP3201221B2 (en) | 1995-07-05 | 1995-07-05 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16912595A JP3201221B2 (en) | 1995-07-05 | 1995-07-05 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0923001A true JPH0923001A (en) | 1997-01-21 |
| JP3201221B2 JP3201221B2 (en) | 2001-08-20 |
Family
ID=15880751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16912595A Expired - Fee Related JP3201221B2 (en) | 1995-07-05 | 1995-07-05 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3201221B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1167787A (en) * | 1997-08-26 | 1999-03-09 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH11103052A (en) * | 1997-09-26 | 1999-04-13 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JP2001044435A (en) * | 1999-06-30 | 2001-02-16 | Fairchild Semiconductor Corp | Highly conductive trench structure |
| JP2002110983A (en) * | 2000-09-28 | 2002-04-12 | Shindengen Electric Mfg Co Ltd | Mos transistor |
| JP2002368220A (en) * | 2001-06-04 | 2002-12-20 | Hitachi Ltd | Semiconductor device and power system using the same |
| JP2002368221A (en) * | 2001-06-08 | 2002-12-20 | Nec Corp | Semiconductor device equipped with longitudinal mosfet and manufacturing method therefor |
| JP2004504711A (en) * | 2000-02-29 | 2004-02-12 | ゼネラル セミコンダクター，インク． | High-speed trench double diffusion metal oxide semiconductor |
| JP2006135038A (en) * | 2004-11-04 | 2006-05-25 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| JP2006140263A (en) * | 2004-11-11 | 2006-06-01 | Sanken Electric Co Ltd | Semiconductor element and manufacturing method thereof |
| JP2007049204A (en) * | 2006-11-15 | 2007-02-22 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device having trench structure |
| WO2008099843A1 (en) * | 2007-02-14 | 2008-08-21 | Rohm Co., Ltd. | Nitride semiconductor element and method for manufacturing nitride semiconductor element |
| JP2010147298A (en) * | 2008-12-19 | 2010-07-01 | Rohm Co Ltd | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS598374A (en) * | 1982-07-05 | 1984-01-17 | Matsushita Electronics Corp | Insulated gate field-effect transistor |
| JPS618941A (en) * | 1984-06-23 | 1986-01-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH03109775A (en) * | 1989-09-25 | 1991-05-09 | Hitachi Ltd | Insulation-gate-type semiconductor device |
| JPH05304297A (en) * | 1992-01-29 | 1993-11-16 | Nec Corp | Semiconductor power device and manufacture thereof |
-
1995
- 1995-07-05 JP JP16912595A patent/JP3201221B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS598374A (en) * | 1982-07-05 | 1984-01-17 | Matsushita Electronics Corp | Insulated gate field-effect transistor |
| JPS618941A (en) * | 1984-06-23 | 1986-01-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH03109775A (en) * | 1989-09-25 | 1991-05-09 | Hitachi Ltd | Insulation-gate-type semiconductor device |
| JPH05304297A (en) * | 1992-01-29 | 1993-11-16 | Nec Corp | Semiconductor power device and manufacture thereof |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1167787A (en) * | 1997-08-26 | 1999-03-09 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH11103052A (en) * | 1997-09-26 | 1999-04-13 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JP2001044435A (en) * | 1999-06-30 | 2001-02-16 | Fairchild Semiconductor Corp | Highly conductive trench structure |
| JP2004504711A (en) * | 2000-02-29 | 2004-02-12 | ゼネラル セミコンダクター，インク． | High-speed trench double diffusion metal oxide semiconductor |
| JP2002110983A (en) * | 2000-09-28 | 2002-04-12 | Shindengen Electric Mfg Co Ltd | Mos transistor |
| JP2002368220A (en) * | 2001-06-04 | 2002-12-20 | Hitachi Ltd | Semiconductor device and power system using the same |
| JP2002368221A (en) * | 2001-06-08 | 2002-12-20 | Nec Corp | Semiconductor device equipped with longitudinal mosfet and manufacturing method therefor |
| JP2006135038A (en) * | 2004-11-04 | 2006-05-25 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| JP2006140263A (en) * | 2004-11-11 | 2006-06-01 | Sanken Electric Co Ltd | Semiconductor element and manufacturing method thereof |
| JP2007049204A (en) * | 2006-11-15 | 2007-02-22 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device having trench structure |
| WO2008099843A1 (en) * | 2007-02-14 | 2008-08-21 | Rohm Co., Ltd. | Nitride semiconductor element and method for manufacturing nitride semiconductor element |
| JP2010147298A (en) * | 2008-12-19 | 2010-07-01 | Rohm Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3201221B2 (en) | 2001-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6294476B1 (en) | Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough | |
| JPS6072268A (en) | Method of producing bipolar transistor structure | |
| JPH01290236A (en) | Method of levelling wide trench | |
| JPH0923001A (en) | Manufacture of semiconductor device | |
| US6329251B1 (en) | Microelectronic fabrication method employing self-aligned selectively deposited silicon layer | |
| US5652172A (en) | Method for controlling the etch profile of an aperture formed through a multi-layer insulator layer | |
| JPH03248534A (en) | Manufacture of semiconductor element | |
| JPH04196122A (en) | Manufacture of semiconductor device | |
| JPS6230494B2 (en) | ||
| KR100256237B1 (en) | Method of forming contact hole | |
| JP2707536B2 (en) | Method for manufacturing semiconductor device | |
| KR100811449B1 (en) | Semiconductor device and the fabricating method thereof | |
| JPH0528501B2 (en) | ||
| JPS63257244A (en) | Semiconductor device and manufacture thereof | |
| JPH03163832A (en) | Semiconductor device | |
| KR970005704B1 (en) | Semiconductor device and manufacturing method for the same | |
| JPS60217645A (en) | Manufacture of semiconductor device | |
| JPS6320383B2 (en) | ||
| JP3298183B2 (en) | Method for manufacturing semiconductor device | |
| JPH0542817B2 (en) | ||
| JPS5968950A (en) | Manufacture of semiconductor device | |
| JPH10242275A (en) | Manufacture of semiconductor device | |
| JPS58175843A (en) | Manufacture of semiconductor integrated circuit | |
| JPH03181135A (en) | Manufacture of semiconductor device | |
| JPS62108576A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080622 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090622 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100622 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100622 Year of fee payment: 9 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100622 Year of fee payment: 9 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100622 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110622 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120622 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |