JPS618941A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS618941A JPS618941A JP12976484A JP12976484A JPS618941A JP S618941 A JPS618941 A JP S618941A JP 12976484 A JP12976484 A JP 12976484A JP 12976484 A JP12976484 A JP 12976484A JP S618941 A JPS618941 A JP S618941A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- filled
- semiconductor device
- substances
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体装置の製造工程において、半導体基
板部に形成された四部を所要の物質で埋める、半導体装
置の製造方法に関する0〔従来技術〕
半導体基板の表面に、例えば左右の素子間又は領域間を
分離するため、凹部を形成する。この凹部を絶縁物で埋
め空所部をなくする処理をし、素子特性が低下しないよ
うにしている。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, in which four parts formed in a semiconductor substrate portion are filled with a required substance in the manufacturing process of the semiconductor device. A recess is formed on the surface of a semiconductor substrate, for example, to isolate left and right elements or regions. These recesses are filled with an insulator to eliminate voids and prevent the device characteristics from deteriorating.
この種の従来の半導体装置の製造方法は、第1図(a)
〜(e)に工程順に示す基板の凹部の断面図のようにし
ていた。まず、第1図(a)のように、半導体基板(1
)表面に1写真調版とエツチングなどにより凹部(2)
を形成する0つづいて、この凹部(2)を埋めるため、
例えば、化学的気相反応による形成法で、第1図(b)
K示すように、全面に絶縁膜(3)を形成する。ついで
、例えば、反応性イオンの直進性を利用したドライエツ
チング法、いわゆる反応性イオンエツチング法により全
面をエツチングし、第1図(C)のように、凹部(2)
の外の絶縁膜(3)を除去すると、凹部(2)の側面に
残留絶縁膜(4)が残る。この後さらに、第1図(d)
に示すように、第2回目の絶縁膜(5)を形成した後、
再び全面をエツチングする。The conventional manufacturing method of this type of semiconductor device is shown in FIG. 1(a).
- (e) are cross-sectional views of the concave portion of the substrate shown in the order of steps. First, as shown in FIG. 1(a), a semiconductor substrate (1
) Concave part (2) on the surface by photolithography and etching etc.
Next, in order to fill this recess (2),
For example, in a formation method using a chemical gas phase reaction, as shown in Fig. 1(b).
As shown in K, an insulating film (3) is formed on the entire surface. Next, the entire surface is etched by, for example, a dry etching method that utilizes the linearity of reactive ions, so-called reactive ion etching method, and as shown in FIG. 1(C), a recess (2) is formed.
When the outer insulation film (3) is removed, a residual insulation film (4) remains on the side surface of the recess (2). After this, Fig. 1(d)
As shown in Figure 2, after forming the second insulating film (5),
Etch the entire surface again.
この絶縁膜形成とエツチングを繰返すことKよシ、第1
図(e)に示すように、埋込み層(6)で凹部(2)を
埋めることができる。By repeating this insulating film formation and etching, the first
As shown in Figure (e), the recess (2) can be filled with a buried layer (6).
しかしながら、このような従来の方法では、工程が複雑
で生産性が低く、また、第1図(e)に示すように、埋
込み層(6)内に空洞(7)を生じて素子特性を悪化す
るおそれがあった。ざらに、同一基板面内に幅が種々の
大きさの凹部が混在する場合、埋込み完了の時期に差が
できる。このため、幅の大きい凹部は幅の小さい凹部よ
り埋込みK<くなる。However, in such a conventional method, the process is complicated and productivity is low, and as shown in FIG. There was a risk that Roughly speaking, if recesses of various widths coexist within the same substrate surface, there will be differences in the timing of completion of filling. Therefore, a recess with a large width has a embedding K< more than a recess with a small width.
l そのうえ、四部の幅が極めて狭く、かつ、
深さが幅に比べてかなシ大きい場合は、凹部内に膜形成
を行うことが困難となり、埋めることができない場合も
できていた。l Moreover, the width of the four parts is extremely narrow, and
If the depth is much larger than the width, it becomes difficult to form a film within the recess, and in some cases it may not be possible to fill the recess.
この発明は、半導体基板又はこの上部層の表面に形成さ
れである凹部を埋めるのに、上記基板又は上部層の表面
に粒状物質を付着させ、この付着粒状物質を除去して凹
部内に充てんさせ、この充てんした粒状物質を加熱によ
り溶融して凹部を埋めるようにし、工程が簡単になり生
産性が向上され、同一平面にある各凹部の大きさや形状
が異なっても一様に確実に埋込むことができる、半導体
装置の製造方法を提供することを目的としている。In this invention, in order to fill a recess formed on the surface of a semiconductor substrate or an upper layer thereof, particulate matter is attached to the surface of the substrate or upper layer, and the adhered particulate material is removed to fill the recess. The filled granular material is melted by heating to fill the recesses, simplifying the process and improving productivity, and ensuring uniform filling even if the recesses on the same plane have different sizes and shapes. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.
以下、この発明の一実施例による半導体装置の製造方法
を、第2図(a)〜(θ)に工程順に示す基板の凹部の
断面′図により説明する。まず、第2図(a)に示すよ
うに、半導体基板(1)表面忙凹部(2)を形成する。Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be explained with reference to cross-sectional views of a recessed portion of a substrate shown in the order of steps in FIGS. First, as shown in FIG. 2(a), a concave portion (2) is formed on the surface of a semiconductor substrate (1).
つづいて、凹部(2)を絶縁材料で埋める場合は、JL
ij=@(l; y 9 :y y (D@*i゛b
l 7y*−4JJl#” j質(8)を全面に付着さ
せる。ついで、遠心分離法あるいは空気吹付は法などの
方法により、第1図(1))のように1粒状絶縁物質(
8)を凹部(2)のみに充てんする。つぎ忙、半導体基
板(1)を約900°C以上で粒状絶縁物質(8)が溶
融する程度の温度に加熱し、第2図(0)のように、粒
子間にすき間のない充てん絶縁膜(9)で底側を埋める
。再び、粒状絶縁物質(8)を全面に付着させ、凹部(
8)のみに充てんし、第2図(d)のようKして後、加
熱する。これを繰返すと、第20図(e)に示すように
、凹部(2)を絶縁埋込み1顛で充満して埋込むことが
できる。Next, when filling the recess (2) with insulating material, JL
ij=@(l; y 9 :y y (D@*i゛b
l 7y*-4JJl#"J material (8) is deposited on the entire surface. Then, by a method such as centrifugation or air blowing, one granular insulating material (8) is deposited as shown in Figure 1 (1)).
Fill only the recess (2) with 8). Next, the semiconductor substrate (1) is heated to about 900°C or higher to a temperature that melts the granular insulating material (8), and as shown in Figure 2 (0), a filled insulating film with no gaps between the particles is formed. Fill the bottom side with (9). Again, the granular insulating material (8) is deposited on the entire surface, and the recesses (
Fill only 8), heat as shown in Fig. 2(d), and then heat. By repeating this process, the recess (2) can be filled with one insulating filling as shown in FIG. 20(e).
なお、上記実施例では、粒状絶縁物質(8)の付着は、
1回目と2回目以降との付着工程で同一の粒径のものを
用いたが、2回目以降では粒径を次第に小さくしてもよ
い。In addition, in the above embodiment, the attachment of the granular insulating material (8) is as follows:
Although the same particle size was used in the first and second and subsequent adhesion steps, the particle size may be gradually made smaller in the second and subsequent steps.
また、上記実施例では粒状絶縁物質(8)が球状のもの
を示したが、これに限らず、立方体、八面体など多面体
であってもよい。Further, in the above embodiment, the granular insulating material (8) is spherical, but is not limited to this, and may be polyhedral such as a cube or an octahedron.
ざらに、上記実施例では半導体基板(1)の凹部(2)
に絶縁埋込み層(11で埋込んだ場合を示したが、半導
体基板自体に限らず、ざらに基板上部層に形成された多
結晶シリコン層などの層に形成した凹部を埋める場合に
も適用できる。この場合の粒状物質として二酸化シリコ
ン粉末又は窒化シリコン粉末などの絶縁物粉末を用いる
。Roughly speaking, in the above embodiment, the recess (2) of the semiconductor substrate (1)
An insulating buried layer (11 shows the case of embedding, but it can be applied not only to the semiconductor substrate itself but also to filling a recess formed in a layer such as a polycrystalline silicon layer roughly formed on the upper layer of the substrate. Insulating powder such as silicon dioxide powder or silicon nitride powder is used as the granular material in this case.
なおまた、半導体基板の絶縁膜の凹部を埋める場合に、
多結晶シリコンあるいはアルミ合金”などの粉末を溶融
して埋めることにより適用できるものである。Furthermore, when filling the recesses in the insulating film of the semiconductor substrate,
It can be applied by melting and filling powder such as polycrystalline silicon or aluminum alloy.
以上のように1この発明の方法によれば、半導体基板又
はこの上部層に形成された凹部を埋めるのに、上記基板
又は上部層の全表面に粒状物質を付着し、この付着粒状
物質を除去し上記凹部内に充てんし、この充てんされた
粒状物質を加熱によシ溶融し、凹部を埋めるようにした
ので、工程が簡単になり、生産性が向上され、同一平面
にあるー凹部の大きさや形状が異なっても、一様に確実
に埋めることができる。As described above, 1. According to the method of the present invention, in order to fill a recess formed in a semiconductor substrate or an upper layer thereof, particulate matter is attached to the entire surface of the substrate or upper layer, and the attached particulate matter is removed. The filled granular material is heated and melted to fill the recess, which simplifies the process and improves productivity. Even if the pods have different shapes, they can be filled uniformly and reliably.
第1図は従来の半導体装置の製造方法を工程順に示す基
板の凹部の断面図、第2図はこの発明の一実施例による
半導体装置の製造方法を工程順に示す基板の凹部の断面
図である。
1・・・半導体基板、2・・・凹部、8・・・粒状絶縁
物質、9・・・充てん絶縁膜、10・・・絶縁埋込み層
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view of a concave portion of a substrate showing a conventional method for manufacturing a semiconductor device in order of process, and FIG. 2 is a cross-sectional view of a concave portion of a substrate showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of process. . DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Concavity, 8... Granular insulating material, 9... Filled insulating film, 10... Insulating buried layer. Note that the same reference numerals in the drawings indicate the same or equivalent parts. .
Claims (7)
れてあり、上記基板又は上部層の全表面に埋込み用の粒
状物質を付着させ、上記表面に付着した粒状物質を除去
して上記凹部に充てんし、この充てんされた粒状物質を
加熱溶融し凹部を埋めることを特徴とする半導体装置の
製造方法。(1) A recess is formed on the surface of the semiconductor substrate or the upper layer, and a particulate material for embedding is attached to the entire surface of the substrate or the upper layer, and the particulate material adhering to the surface is removed to form the recess. A method for manufacturing a semiconductor device, characterized in that the filled granular material is heated and melted to fill the recess.
項記載の半導体装置の製造方法。(2) The particulate material is an insulating material.
A method for manufacturing a semiconductor device according to section 1.
の範囲第2項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 2, wherein the particulate material is made of silicon dioxide powder.
囲第1項ないし第3項のいづれかに記載の半導体装置の
製造方法。(4) A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the upper layer is a polycrystalline silicon layer.
載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 1, wherein the upper layer is an insulating film.
の範囲第5項記載の半導体装置の製造方法。(6) The method for manufacturing a semiconductor device according to claim 5, wherein the particulate material is polycrystalline silicon powder.
囲第5項記載の半導体装置の製造方法。(7) The method for manufacturing a semiconductor device according to claim 5, wherein the granular material is aluminum alloy powder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12976484A JPS618941A (en) | 1984-06-23 | 1984-06-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12976484A JPS618941A (en) | 1984-06-23 | 1984-06-23 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS618941A true JPS618941A (en) | 1986-01-16 |
Family
ID=15017621
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12976484A Pending JPS618941A (en) | 1984-06-23 | 1984-06-23 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS618941A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0923001A (en) * | 1995-07-05 | 1997-01-21 | Nec Corp | Manufacture of semiconductor device |
US5691237A (en) * | 1993-09-20 | 1997-11-25 | Fujitsu Limited | Method for fabricating semiconductor device |
CN103456634A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5818938A (en) * | 1981-07-27 | 1983-02-03 | インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン | Integrated circuit structure |
-
1984
- 1984-06-23 JP JP12976484A patent/JPS618941A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5818938A (en) * | 1981-07-27 | 1983-02-03 | インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン | Integrated circuit structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5691237A (en) * | 1993-09-20 | 1997-11-25 | Fujitsu Limited | Method for fabricating semiconductor device |
JPH0923001A (en) * | 1995-07-05 | 1997-01-21 | Nec Corp | Manufacture of semiconductor device |
CN103456634A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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