CN103456634A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN103456634A CN103456634A CN2012101814690A CN201210181469A CN103456634A CN 103456634 A CN103456634 A CN 103456634A CN 2012101814690 A CN2012101814690 A CN 2012101814690A CN 201210181469 A CN201210181469 A CN 201210181469A CN 103456634 A CN103456634 A CN 103456634A
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Abstract
The invention discloses a manufacturing method for a semiconductor device. The manufacturing method for the semiconductor device comprises the steps that a semiconductor substrate is provided, and a gate trench for forming a metal gate electrode structure is formed on the semiconductor substrate; first metal deposition is conducted on the gate trench; protrusions on the upper left corner and the upper right corner of the gate trench are removed so as to enlarge the size of an opening of the gate trench; secondary metal deposition is conducted on the gate trench. According to the manufacturing method for the semiconductor device, the steps of metal deposition-removing of the protrusions on the upper left corner and the upper right corner of the gate trench- metal deposition are conducted for one cycle or more cycles during the process that the gate electrode is formed when filling is conducted on the gate trench by metal aluminum, and the problems that cavities are generated in metal gap fillers, and then the yield of products is lowered are solved.
Description
Technical field
The present invention relates to a kind of semiconductor making method, in particular to a kind of manufacture method of the semiconductor device based on gate replacement technique.
Background technology
In gate metal alternative techniques in semiconductor fabrication process, usually select polysilicon as false grid, after prepared with drain electrode by the source electrode of device, utilize dry etching or wet etching technique that false grid are removed, insert afterwards the metal gate material of metal charge as device in gate groove.
But, along with the device feature size structural development even meticulousr to 45 nanometers, to the gate metal alternative techniques, the especially filling of metal medium, have higher requirement, one of them challenging difficult problem is exactly that metal is difficult to the filling of even atresia in each gate groove.In metal filled process, cavitation happens occasionally, and these cavities are arranged in the gate groove filler, and each gate groove may have cavity to produce.Figure 1A-1C shows the method for inserting metal gate material in prior art in gate groove.As shown in Figure 1A, after forming gate groove shape 101 on Semiconductor substrate 100, deposit a wet metal material layer 102 thereon, shown in metal material can be Ti or Co etc., then as shown in Figure 1B, by the physical vapor deposition (PVD) method, while using aluminum metal to be filled gate groove, there will be projection 103 and 104 in the gate groove upper left corner and the upper right corner, and along with the carrying out of filling, the projection 103 in the left upper right corner can connect together with 104, and the obstruction aluminum metal further is packed in gate groove 101, the final phenomenon occurred as Fig. 1 C, formed a cavity 105 in aluminum metal packed layer 106.
This cavity that is arranged in the metal charge of gate groove can cause performance of semiconductor device to reduce, and may in follow-up operation, produce defect, and then reduce the qualification rate of product, so the cavity in the metal charge of gate groove becomes one of problem that industry must solve.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, is formed with the gate groove that is used to form metal gate structure on described Semiconductor substrate; Described gate groove is carried out to the first metal deposition step; Remove the step of the projection in the described gate groove upper left corner and the upper right corner, to enlarge the opening size of described gate groove; Described gate groove is carried out to the second metal deposition step.
Further, this manufacture method also comprises step, second metal deposition step of the projection that repeatedly repeats described the first metal deposition step, the described removal described gate groove upper left corner and the upper right corner.
Further, the step of the projection in the described removal described gate groove upper left corner and the upper right corner comprises the physical sputtering step.
Further, use a kind of or its combination: Ar, He, the H in gas in the step of described physical sputtering
2.
The flow of the gas used in the step of described physical sputtering further, is 4 to 500sccm.。
Further, the bias power used in the step of described physical sputtering is 50W-1000W.
Further, the source power of using in the step of described physical sputtering is 50W-1000W.
Further, the reaction time of the step of described physical sputtering is 3-50 second.
Further, the step of the projection in the described removal described gate groove upper left corner and the upper right corner comprises the chloride ion etching step.
The flow of the gas used in described etching step further, is 150 to 2500sccm.
Further, the etching power used in described etching step is 100W-1500W.
Further, the temperature of using in described etching step is 15-200 degree centigrade.
Further, the pressure used in described etching step holds in the palm for 0.2-10.
Further, described the first metal deposition step and/or the second metal deposition step are used one of following methods: physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Further, before described gate groove is carried out to described the first metal deposition step, also be included in the step of deposition one wet metal material layer in described gate groove.
Further, described wet metal material is Ti or Co.
Further, the step metal of described deposition refluxed also be included in settling chamber or heating furnace in described the first metal deposition step and/or the second metal deposition step in.
Further, the temperature of using in described reflow step is 300-500 degree centigrade, and the duration of reflow step is 20 minutes-2 hours.
According to the present invention, in the process with the formation grid when using aluminum metal to be filled gate groove, carry out the metal deposition step of taking turns or taking turns more-the remove step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner " process; can avoid producing cavity in filling of metal gap, and then reduce the problem of the qualification rate of product.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-1C shows the method for inserting metal gate material in prior art in gate groove;
Fig. 2 A-2G shows the schematic cross sectional view of each step of the method for inserting metal gate material in gate groove that the present invention proposes;
The flow chart of the method for inserting metal gate material in gate groove that Fig. 3 the present invention proposes.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, detailed step will be proposed in following description, so that the manufacture method of the semiconductor device that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Below, with reference to Fig. 2 A-Fig. 2 G and Fig. 3, the method for inserting metal gate material in gate groove that the present invention proposes is described.
With reference to Fig. 2 A-Fig. 2 G, wherein show the schematic cross sectional view of each step of the method for inserting metal gate material in gate groove that the present invention proposes.
At first, as shown in Figure 2 A, provide Semiconductor substrate 200, the constituent material of described Semiconductor substrate 200 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.In one embodiment of the invention, Semiconductor substrate 200 selects single crystal silicon material to make.Although several examples of having described the material that can form substrate 200 at this, any material that can be used as Semiconductor substrate all falls into spiritual scope of the present invention.At described Semiconductor substrate 200 upper surface growth one deck grid oxic horizons 201, grid oxic horizon 201 is as gate dielectric layer, and its material can be SiO
2, SiON etc., can use ald, chemical vapor deposition (CVD) or other applicable method, above only as example, be not limited to this.In different situations, grid oxic horizon 201 can adopt different materials and different thickness.
Then, deposit spathic silicon layer 202 on the grid oxic horizon 201 of described Semiconductor substrate 200, as shown in Fig. 2 B.The material of polysilicon layer 202 can be the polysilicon of polysilicon or doping metals impurity, and described metal impurities at least comprise a kind of metal (for example titanium, tantalum, tungsten etc.) and metal silicide.The method that forms polysilicon layer 202 comprises that ald, chemical vapor deposition (CVD), plasma strengthen shape chemical meteorology deposition (PECVD) or other applicable method, then at polysilicon layer surface using plasma enhancing chemical vapour deposition (CVD) (PECVD) process deposits silicon nitride or silicon oxynitride, forms hard mask layer.
In ensuing processing step, at the above-mentioned mask layer surface-coated photoresist layer of answering, then utilize conventional photoetching process, art pattern CAD photoresist layers such as exposure, development, cleaning, to form false grid 205, as shown in Fig. 2 B.
Before carrying out the follow-up step that removes false grid, can carry out any other technique, other technique forms side wall layer, forms the common semiconductor fabrication process such as source/drain regions (as low-doped source/drain regions) in substrate including but not limited to the both sides at described false grid, is not repeated herein.
Then form dielectric layer as interlayer dielectric layer (ILD) on substrate, the formation method of interlayer dielectric layer 206 can be CVD, PECVD or other appropriate method.The composition of interlayer dielectric layer 206 contains silica, silicon oxynitride or other suitable material.In one embodiment, the dielectric layer that interlayer dielectric layer 206 forms for the PECVD method.Then by its planarization, use for example chemical and mechanical grinding method (CMP), remove the dielectric layer material of deposition on false grid 205, until expose false grid 205 upper surfaces, as shown in Figure 2 C.
Then remove false grid 205, to form gate groove 207, as shown in Figure 2 D.In one embodiment, can utilize false grid 205 etchings shown in general such as one of dry etching or wet etching technique etc. to remove, thereby form gate groove 207.In another embodiment, can utilize dry etching or wet etching technique further grid oxic horizon 201 to be removed, to form the groove 207 that exposes substrate, redeposited high k gate dielectric layer (not shown) then, this high k gate dielectric layer (for example adopts the high K medium material, with silica, compare, material with high-k), the example of high K medium material comprises metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, the nitrogen oxide of metal, the combination of metal aluminate or other suitable compositions.
Then in gate groove 207, insert metal gate material.In one embodiment, can be at first at wet metal material layer 208 of gate groove 207 surface deposition, described metal material can be Ti or Co etc.Then, in one embodiment, by the deposition process of methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), use aluminum metal to be filled gate groove.This deposition step can also be included in settling chamber or heating furnace the step that the metal to described deposition is refluxed, and in this reflow step, the temperature of use can be 300-500 degree centigrade, and the duration of reflow step is 20 minutes-2 hours.In the process of using aluminum metal to fill gate groove, can there will be projection 209 and 210 in gate groove 207 upper left corners and the upper right corner, the obstruction aluminum metal continues to fill gate groove by the upper shed of gate groove 207, as shown in Figure 2 E.
Therefore, next, need to be removed the projection 209 in gate groove 207 upper left corners and the upper right corner and 210 step, as shown in Figure 2 F.The projection 209 in these removal gate groove 207 upper left corners and the upper right corner and 210 step can be used the method for physical sputtering, in the process of this physical sputtering, can adopt Ar, He, H
2etc. one of various process gass or by the mist of two kinds or above gas composition wherein, gas flow can be between 4 to 500sccm, and adopt the bias power 50W-1000W of 2MHz, the source power 50W-1000W of 27MHz, and the reaction time is 3-50 second.For example, in one embodiment, process gas can adopt Ar, and the Ar gas flow is about 400sccm, and the power output of the bias power of the 2MHz adopted is 500W, and the power output of the source power of 27MHz is 500W, and the reaction time is 40 seconds.Under such reaction condition, can remove the projection 209 and 210 in gate groove 207 upper left corners and the upper right corner, and enlarge the opening size of gate groove, as shown in Figure 2 F.
In another embodiment of the present invention, the projection 209 in described removal gate groove 207 upper left corners and the upper right corner and 210 step can also be used the chloride ion etching method, in the use chloride ion carries out etched process, gas flow can be between 150 to 2500sccm, etching power is 100W-1500W, the temperature adopted is 15-200 degree centigrade, and the pressure of use holds in the palm for 0.2-10.Under such reaction condition, also can remove the projection 209 and 210 in gate groove 207 upper left corners and the upper right corner, and enlarge the opening size of gate groove, as shown in Figure 2 F.
Then, deposition process by methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), continuation is to the interior filling metal gate material 212 of gate groove 207, until complete the step that aluminum metal is filled, and avoid the cavity in the metal charge of gate groove shape fully, as shown in Figure 2 G.The step of this continuation deposition can also be included in settling chamber or heating furnace the step that the metal to described deposition is refluxed, and in this reflow step, the temperature of use can be 300-500 degree centigrade, and the duration of reflow step is 20 minutes-2 hours.In one embodiment of the invention, the process of " metal deposition step-remove the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner " that can carry out taking turns, can complete gate replacement technique, and avoid producing cavity in the gate groove filler.In other embodiment of the present invention, can repeatedly repeat " metal deposition step-remove the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner ", just can avoid producing cavity in the gate groove filler.
So far, whole processing steps that method is implemented have according to an exemplary embodiment of the present invention been completed.Next, can complete by subsequent technique the making of whole semiconductor device, described subsequent technique and traditional process for fabricating semiconductor device are identical.
With reference to Fig. 3, wherein show the flow chart of the method for inserting metal gate material in gate groove of the present invention's proposition, for schematically illustrating the flow process of whole manufacturing process.
In step 301, Semiconductor substrate is provided, be formed with the gate groove that is used to form metal gate structure on described Semiconductor substrate;
In step 302, described gate groove is carried out to the step of the first metal deposition;
In step 303, remove the projection in the described gate groove upper left corner and the upper right corner, to enlarge the opening size of described gate groove;
In step 304, described gate groove is carried out to the second metal deposition step.Can repeatedly repeat as required " metal deposition step-remove the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner ", until complete metal filled step, and avoid the cavity in filling of metal gap fully.
According to the present invention, in the process with the formation grid when using aluminum metal to be filled gate groove, " metal deposition step-remove the step-metal deposition step of the projection in the described gate groove upper left corner and the upper right corner " process of carrying out taking turns or taking turns more, can avoid producing cavity in filling of metal gap, and then reduce the problem of the qualification rate of product.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, is formed with the gate groove that is used to form metal gate structure on described Semiconductor substrate;
Described gate groove is carried out to the first metal deposition step;
Remove the step of the projection in the described gate groove upper left corner and the upper right corner, to enlarge the opening size of described gate groove;
Described gate groove is carried out to the second metal deposition step.
2. method according to claim 1, also comprise step, second metal deposition step of the projection that repeatedly repeats described the first metal deposition step, the described removal described gate groove upper left corner and the upper right corner.
3. method according to claim 1, is characterized in that, the step of the projection in the described removal described gate groove upper left corner and the upper right corner comprises the physical sputtering step.
4. method according to claim 3, is characterized in that, uses a kind of or its combination: Ar, He, H2 in following gas in described physical sputtering step.
5. method according to claim 3, is characterized in that, the flow of the gas used in described physical sputtering step is 4 to 500sccm.
6. method according to claim 3, is characterized in that, the bias power used in described physical sputtering step is 50W-1000W.
7. method according to claim 3, is characterized in that, the source power of using in described physical sputtering step is 50W-1000W.
8. method according to claim 3, is characterized in that, the reaction time of described physical sputtering step is 3-50 second.
9. method according to claim 1, is characterized in that, the step of the projection in the described removal described gate groove upper left corner and the upper right corner comprises the chloride ion etching step.
10. method according to claim 9, is characterized in that, the flow of the gas used in described etching step is 150 to 2500sccm.
11. method according to claim 9, is characterized in that, the etching power used in described etching step is 100W-1500W.
12. method according to claim 9, is characterized in that, the temperature of using in described etching step is 15-200 degree centigrade.
13. method according to claim 9, is characterized in that, the pressure used in described etching step holds in the palm for 0.2-10.
14. method according to claim 1, is characterized in that, described the first metal deposition step and/or the second metal deposition step are used one of following methods: physical vapour deposition (PVD) or chemical vapour deposition (CVD).
15. method according to claim 1, is characterized in that, before described gate groove is carried out to described the first metal deposition step, also is included in the step of deposition one wet metal material layer in described gate groove.
16. the method according to claim 15, is characterized in that, described wet metal material is Ti or Co.
17. method according to claim 1, is characterized in that, the step metal of described deposition refluxed also be included in settling chamber or heating furnace in described the first metal deposition step and/or the second metal deposition step in.
18. method according to claim 17, is characterized in that, the temperature of using in described reflow step is 300-500 degree centigrade, and the duration of reflow step is 20 minutes-2 hours.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633135A (en) * | 2014-11-06 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN109742026A (en) * | 2019-02-25 | 2019-05-10 | 哈尔滨工业大学 | The method that direct growth method prepares diamond auxiliary heat dissipation silicon carbide substrate GaN-HEMTs |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633135A (en) * | 2014-11-06 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN105633135B (en) * | 2014-11-06 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN109742026A (en) * | 2019-02-25 | 2019-05-10 | 哈尔滨工业大学 | The method that direct growth method prepares diamond auxiliary heat dissipation silicon carbide substrate GaN-HEMTs |
| CN109742026B (en) * | 2019-02-25 | 2024-03-29 | 哈尔滨工业大学 | Method for preparing diamond-assisted heat dissipation silicon carbide substrate GaN-HEMTs by direct growth method |
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Application publication date: 20131218 |