CN103811403B - The formation method of fleet plough groove isolation structure - Google Patents
The formation method of fleet plough groove isolation structure Download PDFInfo
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- CN103811403B CN103811403B CN201210454954.0A CN201210454954A CN103811403B CN 103811403 B CN103811403 B CN 103811403B CN 201210454954 A CN201210454954 A CN 201210454954A CN 103811403 B CN103811403 B CN 103811403B
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- mask layer
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- plough groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
A formation method for fleet plough groove isolation structure, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form cushion oxide layer; In described cushion oxide layer, form mask layer; Mask layer described in etching, forms the opening that runs through described mask layer thickness; The sidewall of described opening is carried out to oxidation processes, form oxide layer; Oxide layer, mask layer, pad oxide layer and Semiconductor substrate described in etching, to the mask layer of remainder thickness and be positioned at the oxide layer on its sidewall, form isolated groove; In described isolated groove, form fleet plough groove isolation structure. The formation method of fleet plough groove isolation structure of the present invention can be avoided occurring groove at fleet plough groove isolation structure and Semiconductor substrate seam crossing, improve the pattern of the fleet plough groove isolation structure that forms, and then improve the electric property of the semiconductor devices that comprises formed fleet plough groove isolation structure.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, 0.18 micron of following element (for example CMOS collectionBecome between the active area of circuit) mostly adopt fleet plough groove isolation structure (STI) to carry out lateral isolation.
Fleet plough groove isolation structure is as a kind of device separation, and its concrete technology comprises: with reference to figure 1, carryFor Semiconductor substrate 101, in described Semiconductor substrate 101, be formed with successively from the bottom to top pad oxide layer103, hard mask layer 105 and mask layer 109, is formed with and exposes hard mask layer 105 in described mask layer 109Opening 111, described opening 111 has the shape corresponding with the isolation structure that defines active area; ReferenceFig. 2, taking the mask layer 109 that comprises opening 111 in Fig. 1 as mask, successively hard mask layer 105 described in etching,Pad oxide layer 103 and Semiconductor substrate 101, form isolated groove 113; With reference to figure 3, remove institute in Fig. 2State mask layer 109, and in isolated groove 113 described in Fig. 2 and the mask layer of isolated groove 113 both sidesCvd silicon oxide material 115a on 109; With reference to figure 4, silica material 115a described in planarization Fig. 3, extremelyExpose hard mask layer 105, form fleet plough groove isolation structure 115b; With reference to figure 5, by wet etching workSkill is removed hard mask layer 105 described in Fig. 4.
But the fleet plough groove isolation structure 115b forming by above-mentioned technique is easily in itself and pad oxide layer103, the seam crossing of Semiconductor substrate 101 is prone to groove 117, causes formed semiconductor devices easily to be sent outRaw " narrow width effect " (narrowwidtheffect) and the PMOS transistor forming easily form electric leakage,Have a strong impact on the electric property of the semiconductor devices that comprises above-mentioned fleet plough groove isolation structure 115b.
In the United States Patent (USP) that is US7112513 in the patent No., can also find more about fleet plough groove isolation structureRelevant information.
Therefore, how to avoid formed fleet plough groove isolation structure to occur at itself and Semiconductor substrate seam crossingGroove, just becomes one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fleet plough groove isolation structure, can avoid instituteThere is groove at itself and the seam crossing of Semiconductor substrate in the fleet plough groove isolation structure forming, improve form partlyThe electric property of conductor device.
For addressing the above problem, the invention provides a kind of formation method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form cushion oxide layer;
In described cushion oxide layer, form mask layer;
Mask layer described in etching, forms the opening that runs through described mask layer thickness;
The sidewall of described opening is carried out to oxidation processes, form oxide layer;
Oxide layer, mask layer, pad oxide layer and Semiconductor substrate described in etching, to remainder thicknessMask layer and be positioned at the oxide layer on its sidewall, form isolated groove;
In described isolated groove, form fleet plough groove isolation structure.
Optionally, after formation runs through the opening of described mask layer thickness, also comprise: to described openingThe mask layer of both sides carries out dry etching, makes the edge of described opening be circular-arc.
Optionally, the gas of described oxidation processes is the mist of oxygen and Krypton, and the flow of oxygen is100sccm ~ 1000sccm, the flow of Krypton is 100sccm ~ 1000sccm, the temperature of oxidation processes is 0DEG C ~ 100 DEG C, pressure is 5mTorr ~ 5Torr, the time of oxidation processes is 10s ~ 300s.
Compared with prior art, technical solution of the present invention has the following advantages:
Before forming isolated groove, first the mask layer on opening sidewalls is carried out to oxidation processes, form oxygenChange layer, then oxide layer, mask layer, pad oxide layer and Semiconductor substrate are carried out to etching, to remainderThe mask layer of point thickness and be positioned at the oxide layer on its sidewall, forms isolated groove, then described everyIn groove, form fleet plough groove isolation structure. After forming fleet plough groove isolation structure, owing to being positioned at residueOxide layer on the mask layer sidewall of segment thickness can stop etching solution infiltrate fleet plough groove isolation structure withThe seam crossing of Semiconductor substrate, avoids the fleet plough groove isolation structure of seam crossing and etching solution to react,And then avoid occurring groove at fleet plough groove isolation structure and Semiconductor substrate seam crossing, improve the shallow ridges that formsThe pattern of recess isolating structure, and then improve the electricity of semiconductor devices that comprises formed fleet plough groove isolation structureLearn performance.
Further, before the sidewall of opening is carried out to oxidation processes, the mask layer of opening both sides is enteredRow dry etching, makes the edge of opening be circular-arc, to reduce to form isolated groove remaining oxidation afterwardsLayer, avoids when groove appears in fleet plough groove isolation structure and Semiconductor substrate seam crossing, avoids remainingOxide layer too much the performance of fleet plough groove isolation structure is impacted, further improved and comprised institute's shapeBecome the electric property of the semiconductor devices of fleet plough groove isolation structure.
Brief description of the drawings
Fig. 1 to Fig. 5 is the schematic diagram that prior art forms fleet plough groove isolation structure;
Fig. 6 to Figure 11 is the schematic diagram of formation method first embodiment of fleet plough groove isolation structure of the present invention;
Figure 12 to Figure 15 is the schematic diagram of formation method second embodiment of fleet plough groove isolation structure of the present invention;
Figure 16 to Figure 20 is the schematic diagram of formation method the 3rd embodiment of fleet plough groove isolation structure of the present invention.
Detailed description of the invention
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but thisBrightly can also adopt other to be different from alternate manner described here to implement, below therefore the present invention is not subject toThe restriction of disclosed specific embodiment.
Just as described in the background section, in existing technique in fleet plough groove isolation structure and Semiconductor substrateSeam crossing is prone to groove, has had a strong impact on the performance of the semiconductor devices that comprises fleet plough groove isolation structure.
Inventor finds through research: after isolated groove forms, in isolated groove and isolating trenchesOn the mask layer of groove both sides when cvd silicon oxide material, due to the material of silica material and Semiconductor substrateDifference, silica material is combined not tight with Semiconductor substrate, removed firmly and covered by wet-etching technologyWhen mould layer, etching solution easily infiltrates the seam crossing of silica material and Semiconductor substrate, causes partial oxidationSilicon materials are etched, and form groove at the seam crossing of silica material and Semiconductor substrate. When formedFleet plough groove isolation structure, as the isolation structure between MOS device, is carrying out implantation to Semiconductor substrateFashionable, the existence of groove can cause adulterating ion more easily to the Semiconductor substrate diffusion of grid structure below,And then cause the channel length of MOS device to shorten, its performance to the short MOS device of channel length (as:Threshold voltage) impact more obvious, occur " narrow width effect ", had a strong impact on and comprised formed shallow trench isolationFrom the electric property of the semiconductor devices of structure.
For above-mentioned defect, the invention provides a kind of formation method of fleet plough groove isolation structure, formingBefore isolated groove, first the mask layer on opening sidewalls is carried out to oxidation processes, form oxide layer, shapeBecome when isolated groove, retain the partial oxidation layer in isolated groove semiconductor substrates on two sides, with at shallow trenchAfter isolation structure forms, while removing the mask layer of remainder thickness, stop etching solution to infiltrate shallow trenchThe seam crossing of isolation structure and Semiconductor substrate, prevents that the fleet plough groove isolation structure of seam crossing is etched, and keeps awayExempt to form groove at the seam crossing of fleet plough groove isolation structure and Semiconductor substrate, improved comprise formed shallowThe electric property of the semiconductor devices of groove isolation construction.
Be elaborated below in conjunction with accompanying drawing.
The first embodiment
With reference to figure 6, provide Semiconductor substrate 201, shape successively from the bottom to top in described Semiconductor substrate 201Become to have cushion oxide layer 203 and mask layer 205a.
In the present embodiment, the material of described Semiconductor substrate 201 is monocrystalline silicon or single-crystal silicon Germanium, or singleBrilliant carbon doped silicon; Or the material that can also comprise other, the present invention does not limit this.
Described mask layer 205a is single layer structure, and the material of described mask layer 205a is silicon nitride or polycrystallineSilicon.
The material of described cushion oxide layer 203 is silica, can pass through thermal oxidation technology or chemical gaseous phaseDepositing operation forms. What described pad oxide layer 203 existed in order to repairing semiconductor substrate 201 surfaces lacksFall into, improve the conjugation of mask layer 205a and Semiconductor substrate 201, avoid mask layer 205a and semiconductorSubstrate 201 is in conjunction with bad and peel off from Semiconductor substrate 201.
In addition, because silicon nitride has stress, in the time that the material of described mask layer 205a is silicon nitride, instituteState pad oxide layer 203 to mask layer 205a and 201 buffer actions of Semiconductor substrate, avoid mask layerStress in 205a impacts Semiconductor substrate 201.
Continue with reference to figure 6, form the opening 211 that runs through described mask layer 205a thickness, described opening 211Corresponding with the shape of the fleet plough groove isolation structure of follow-up formation.
With reference to figure 7, to the 205a of mask layer described in Fig. 6 surface (comprise mask layer 205a upper surface andThe sidewall of opening 211) carry out oxidation processes, form oxide layer 207a.
The method of described oxidation processes is free-radical oxidation (radicaloxidation), described oxidation processesReacting gas is Krypton (Kr) and oxygen (O2) mist, the flow of oxygen is100sccm ~ 1000sccm, the flow of Krypton is 100sccm ~ 1000sccm, the temperature of oxidation processes is 0DEG C ~ 100 DEG C, pressure is 5mTorr ~ 5Torr, the time of oxidation processes is 10s ~ 300s.
In the present embodiment, in the time that the material of described mask layer 205a is silicon nitride, the oxide layer 207a that formsMaterial comprise the compound such as silica, silicon oxynitride; When the material of described mask layer 205a is polysiliconTime, the material of the oxide layer 207a that forms is silica.
In other embodiments, after described oxide layer 207a forms, also can be by hydrochloric acid and hydrofluoric acidMixed solution cleans described oxide layer 207a, is formed the thick of oxide layer 207a with further attenuateDegree.
With reference to figure 8, to the 207a of oxide layer described in Fig. 7, mask layer 205b, pad oxide layer 203 andSemiconductor substrate 201 is carried out etching, to the mask layer 205c of remainder thickness and be positioned on its sidewallOxide layer 207b, form isolated groove 213.
In the present embodiment, to oxide layer 207a, mask layer 205b, pad oxide layer 203 and semiconductor liningThe method that etching is carried out at the end 201 is anisotropic dry etch, the etching of described anisotropic dry etchGas is HBr, N2And NF3Mist, the flow of HBr is 100sccm ~ 500sccm, N2'sFlow is 5sccm ~ 200sccm, NF3Flow be 5sccm～100sccm, power is100W ~ 2000W, bias generator power are 100W ~ 500W, and etch period is 10s ~ 300s.
Due to the good directionality of described anisotropic dry etch, can be vertically simultaneously to oxide layer207a, mask layer 205b, pad oxide layer 203 and Semiconductor substrate 201 are carried out etching, form everyDuring from groove 213, also remove mask layer 205b and the oxide layer 207a of segment thickness, made pad oxidationThe thinner thickness of mask layer 205c and oxide layer 207b on layer 203.
With reference to figure 9, in the oxide layer of isolated groove 213 described in Fig. 8 and isolated groove 213 both sidesThe upper layer deposited isolating 215a of 207b and mask layer 205c.
In the present embodiment, the material of described separation layer 215a is silica, can be by thermal oxidation technology orChemical vapor deposition method deposition, but the invention is not restricted to this.
With reference to Figure 10, separation layer 215a described in planarization Fig. 9, to exposing described oxide layer 207bWith mask layer 205c, form fleet plough groove isolation structure 215b.
In the present embodiment, the method for separation layer 215a is chemical mechanical milling tech (CMP) described in planarization.In the time that the material of described mask layer 205c is silicon nitride, it also can be used as in planarization separation layer 215a processStop-layer, avoid chemical mechanical milling tech to make pad oxide layer 203 and Semiconductor substrate 201Become damage.
With reference to Figure 11, remove the 205c of mask layer described in Figure 10 by wet-etching technology.
In the present embodiment, in the time that the material of described mask layer 205c is silicon nitride, the quarter of described wet etchingErosion solution is phosphoric acid solution, and in described phosphoric acid solution, the volume ratio of phosphoric acid and water is 1:1 ~ 1:20, phosphoric acid solutionTemperature be 100 DEG C ~ 250 DEG C.
In the time that the material of described mask layer 205c is polysilicon, the etching solution of described wet etching isTMAH(tetramethyl aqua ammonia) solution.
In the time removing described mask layer 205c by wet-etching technology, described oxide layer 207b can haveEffect stops etching solution to infiltrate the seam crossing of Semiconductor substrate 201 and fleet plough groove isolation structure 215b, avoidsThe fleet plough groove isolation structure 215b of seam crossing is because reacting and be removed with etching solution, and then avoidsThere is groove in the seam crossing of fleet plough groove isolation structure 215b and Semiconductor substrate 201, makes shallow trench isolation junctionThe pattern of structure 215b better, isolation effect is better, improved and comprised formed fleet plough groove isolation structure 215bThe electric property of semiconductor devices.
It should be noted that, the present embodiment is forming after fleet plough groove isolation structure 215b, shallow trench isolation junctionThe oxide layer 207b of structure 215b and Semiconductor substrate 201 seam crossings does not remove, still, and due to oxidationLayer 207b is the material that comprises silica, and it is insulator, can be the same with fleet plough groove isolation structure 215bPlay buffer action, little to the performance impact of semiconductor devices.
The second embodiment
With reference to Figure 12, Semiconductor substrate 301 is provided, in described Semiconductor substrate 301 from the bottom to top successivelyBe formed with cushion oxide layer 303 and mask layer 305a, in described mask layer 305a, be formed with and expose padThe opening 311 of oxide layer 303.
With reference to Figure 13, the mask layer 305a of the both sides of opening 311 described in Figure 12 is carried out to etching, make instituteThe edge of stating opening 311 is circular-arc. , make the edge of the mask layer 305b after etching be circular-arc.
In the present embodiment, the method for the mask layer 305a of opening 311 both sides being carried out to etching is dry etching.Be CF as adopted etching gas4、CHF3, Ar, He and O2Mist, CF4Flow be50sccm~500sccm，CHF3Flow be 50sccm ~ 500sccm, the flow of Ar is100sccm ~ 500sccm, the flow of He is 50sccm ~ 500sccm, O2Flow be10sccm ~ 100sccm, power is that 100W ~ 1000W, bias generator power are 100W ~ 1000W,Etch period is 10s ~ 300s. But the invention is not restricted to this, it also can adopt as well known to those skilled in the artOther lithographic methods make the edge of described opening 311 be circular-arc.
With reference to Figure 14, the surface to the 305a of mask layer described in Figure 13 (comprises the upper table of mask layer 305aFace and edge are the sidewall of circular-arc opening 311) carry out oxidation processes, form oxide layer 307a.
In the present embodiment, the method and the first embodiment that the surface of mask layer 305a are carried out to oxidation processes are completeEntirely identical, do not repeat them here.
With reference to Figure 15, to the 307a of oxide layer described in Figure 14, mask layer 305b, pad oxide layer 303Carry out etching with Semiconductor substrate 301, to the mask layer 305d of remainder thickness and be positioned at its sidewallOn oxide layer 307b, form isolated groove (not shown); And in formed isolated groove, fill fullIsolated material, forms fleet plough groove isolation structure 315b.
In the present embodiment, form isolated groove and in isolated groove, form fleet plough groove isolation structure 315b'sMethod is identical with the first embodiment, does not repeat them here.
In the present embodiment, before the sidewall of opening 311 is carried out to oxidation processes, first to mask layer 305aCarry out etching, make the edge of mask layer 305b split shed 311 after etching be circular-arc; To mask layer 305bWhile carrying out oxidation processes, then by the upper oxide layer of mask layer 305c after control oxidation processes control oxidation processesThe thickness of 307a; In the time forming isolated groove, can reduce the volume of isolated groove both sides oxide layer 307b,Utilizing oxide layer 307b to stop etching solution to infiltrate fleet plough groove isolation structure 315b and Semiconductor substrate 301Seam crossing, avoids when seam crossing forms groove, reduces oxide layer 307b to formed shallow trench isolationFrom the impact of structure 315b performance, further improve and comprised formed fleet plough groove isolation structure 315b'sThe electric property of semiconductor devices.
The 3rd embodiment
With reference to Figure 16, Semiconductor substrate 401 is provided, in described Semiconductor substrate 401 from the bottom to top successivelyBe formed with cushion oxide layer 403 and mask layer.
In the present embodiment, described mask layer is double-decker, and described mask layer comprises and is positioned at pad oxide layerThe first mask layer 405a on 403 and be positioned at the second mask layer 409a on the first mask layer 405a.
In the present embodiment, the material of described the second mask layer 409a is silica, described the second mask layer 409aFormation method be thermal oxidation technology or chemical vapor deposition method, but the invention is not restricted to this.
Continue with reference to Figure 16, form and run through opening of described the first mask layer 405a and the second mask layer 409aMouth 411, described opening 411 is corresponding with the shape of the fleet plough groove isolation structure of follow-up formation.
The technique that forms described opening 411 is conventionally known to one of skill in the art, does not repeat at this.
With reference to Figure 17, the sidewall of Figure 16 split shed 411 is carried out to oxidation processes, form oxide layer 407.
In the present embodiment, in the time that the sidewall of Figure 16 split shed 411 is carried out to oxidation processes, simultaneously to secondThe first shielding rete 405a and the second mask layer on upper surface, opening 411 sidewalls of mask layer 409a409a carries out oxidation processes. But, because the material of the second mask layer 409a is silica, oxidation processesAfterwards, the material of the second mask layer 409 does not change; And the material of the first mask layer 405a is polycrystallineSilicon or silicon nitride, after oxidation processes, the second mask layer 409a surface shape on opening 411 sidewallsBecome oxide layer 407. The thickness of oxide layer 407 can accurately be controlled by described oxidation processes, and its height canThickness by mask layer 405b is accurately controlled.
In the present embodiment, the method for the sidewall of opening 411 being carried out to oxidation processes is identical with the first embodiment,Do not repeat at this.
Continue with reference to Figure 17, to described the second mask layer 409a, pad oxide layer 403 and Semiconductor substrate401 carry out etching, to the mask layer of remainder thickness, form isolated groove 413.
In the present embodiment, form after isolated groove 413, the mask layer of remainder thickness comprises that first coversThe second mask layer 409b of rete 405b and segment thickness.
In other embodiments, the mask layer of remainder thickness can be only also the first mask layer 405b.
In the present embodiment, to described the second mask layer 409a, pad oxide layer 403 and Semiconductor substrate 401The method of carrying out etching is anisotropic dry etch. The gas of described anisotropic dry etch be HBr,N2And NF3Mist, the flow of HBr is 100sccm ~ 500sccm, N2Flow be 5sccm~200sccm，NF3Flow be 5sccm ~ 100sccm, power be 100W ~ 2000W,Bias generator power is 100W ~ 500W, and etch period is 10s ~ 300s.
Due to the good directionality of described anisotropic dry etch, can vertically cover second simultaneouslyRete 409a, pad oxide layer 403 and Semiconductor substrate 401 carry out etching, without forming maskIn situation, form isolated groove 413.
With reference to Figure 18, in isolated groove 413 described in Figure 17 and isolated groove 413 both sides secondThe upper deposition of mask layer 409b isolated material 415a.
The material of the 415a of isolated material described in the present embodiment and formation method respectively with the first embodiment in everyMaterial from material 215a is identical with formation method, does not repeat them here.
With reference to Figure 19, isolated material 415a described in planarization Figure 18, to exposing described oxide layer 407With mask layer 405b, form fleet plough groove isolation structure 415b.
In the present embodiment, the method for isolated material 415a is chemical mechanical milling tech described in planarization.
With reference to Figure 20, remove the 405b of mask layer described in Figure 19 by wet-etching technology.
In the present embodiment, remove mask layer 205c in the method for described mask layer 405b and the first embodimentRemoval method identical, do not repeat them here.
In the present embodiment, because the upper surface of mask layer 405a is covered by the second mask layer 409a, described oxygenChange mask layer 405b surface on the sidewall that 407, layer is formed at opening 411, its thickness can be by oxidation placeReason is controlled, and the height of oxide layer 407 can enter by the thickness of controlling the mask layer 405a that formsRow is controlled, and therefore, the present embodiment can accurately be controlled follow-up Semiconductor substrate 401 and the shallow trench isolation of being formed atFrom the volume of structure 415b seam crossing oxide layer 407, ensureing fleet plough groove isolation structure and Semiconductor substrateWhen seam crossing does not occur groove, reduce oxide layer 407 to formed fleet plough groove isolation structure performanceImpact, improved the electric property of the semiconductor devices that comprises formed fleet plough groove isolation structure 415b.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (10)
1. a formation method for fleet plough groove isolation structure, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form cushion oxide layer;
In described cushion oxide layer, form mask layer;
Mask layer described in etching, forms the opening that runs through described mask layer thickness;
Upper surface to described mask layer and the sidewall of described opening carry out oxidation processes, form oxide layer;
Oxide layer, mask layer, pad oxide layer and Semiconductor substrate described in etching, to the mask layer of remainder thickness and be positioned at the oxide layer on its sidewall, form isolated groove, the mask layer of described segment thickness and the oxide layer being positioned on its sidewall are positioned in cushion oxide layer;
In described isolated groove, form fleet plough groove isolation structure.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, described mask layer is single layer structure, and the material of described mask layer is polysilicon or silicon nitride.
3. the formation method of fleet plough groove isolation structure as claimed in claim 2, is characterized in that, after formation runs through the opening of described mask layer thickness, also comprises: the mask layer to described opening both sides carries out dry etching, makes the edge of described opening be circular-arc.
4. the formation method of fleet plough groove isolation structure as claimed in claim 3, is characterized in that, the etching gas of described dry etching is CF4、CHF3, Ar, He and O2Mist.
5. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, described mask layer is double-decker, described mask layer comprises the first mask layer being positioned in described cushion oxide layer and is positioned at the second mask layer on described the first mask layer, the material of described the first mask layer is polysilicon or silicon nitride, and the material of described the second mask layer is silica.
6. the formation method of fleet plough groove isolation structure as claimed in claim 5, is characterized in that, the mask layer of described remainder thickness at least comprises described the first mask layer.
7. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the gas of described oxidation processes is the mist of oxygen and Krypton, the flow of oxygen is 100sccm～1000sccm, the flow of Krypton is 100sccm～1000sccm, the temperature of oxidation processes is 0 DEG C～100 DEG C, and pressure is 5mTorr～5Torr, and the time of oxidation processes is 10s～300s.
8. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, forms fleet plough groove isolation structure and comprise in described isolated groove:
In oxide layer on mask layer and the sidewall thereof of remainder thickness He in described isolated groove, form separation layer;
Separation layer described in planarization, to the oxide layer exposing on mask layer and the sidewall thereof of remainder thickness, forms fleet plough groove isolation structure;
Remove the mask layer of remainder thickness by wet-etching technology.
9. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the method for oxide layer, mask layer, pad oxide layer and Semiconductor substrate is anisotropic dry etch described in etching.
10. the formation method of fleet plough groove isolation structure as claimed in claim 9, is characterized in that, the etching gas of described anisotropic dry etch is HBr, N2And NF3Mist.
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| TW410423B (en) * | 1998-10-21 | 2000-11-01 | United Microelectronics Corp | Manufacture method of shallow trench isolation |
| CN1353864A (en) * | 1999-10-28 | 2002-06-12 | 皇家菲利浦电子有限公司 | Method for suppressing narrow width effects in CMOS Technology |
| CN1428835A (en) * | 2001-12-20 | 2003-07-09 | 东部电子株式会社 | Method for forming isolated film of semiconductor element |
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| JP2002043408A (en) * | 2000-07-28 | 2002-02-08 | Nec Kansai Ltd | Manufacturing method of semiconductor device |
| KR100561522B1 (en) * | 2003-12-30 | 2006-03-16 | 동부아남반도체 주식회사 | Method For Fabricating Of Shallow Trench Isolation Of Semiconductor Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW410423B (en) * | 1998-10-21 | 2000-11-01 | United Microelectronics Corp | Manufacture method of shallow trench isolation |
| CN1353864A (en) * | 1999-10-28 | 2002-06-12 | 皇家菲利浦电子有限公司 | Method for suppressing narrow width effects in CMOS Technology |
| CN1428835A (en) * | 2001-12-20 | 2003-07-09 | 东部电子株式会社 | Method for forming isolated film of semiconductor element |
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