CN101770974A - Method for fabricating shallow-trench isolation structure - Google Patents
Method for fabricating shallow-trench isolation structure Download PDFInfo
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- CN101770974A CN101770974A CN200810205387A CN200810205387A CN101770974A CN 101770974 A CN101770974 A CN 101770974A CN 200810205387 A CN200810205387 A CN 200810205387A CN 200810205387 A CN200810205387 A CN 200810205387A CN 101770974 A CN101770974 A CN 101770974A
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Abstract
The invention relates to a method for fabricating a shallow-trench isolation structure, which comprises the following steps: providing a semiconductor substrate in which a trench is formed; performing an oxygen plasma treating process at the trench top; after the oxygen plasma treating process is completed, performing a cleaning process to the trench to remove an oxide layer at the edge of the trench top; and after the cleaning process is completed, filling a dielectric material into the trench. The method can avoid or reduce the formation of defects at the edge of the trench top during the fabrication of the shallow-trench isolation structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of fleet plough groove isolation structure.
Background technology
Along with the semiconductor integrated circuit manufacturing technology constantly develops, also (Local Oxidation ofSilicon LOCOS) develops into the shallow trench isolation technology to the isolation technology of device and device by original silicon carrying out local oxide isolation in the semiconductor integrated circuit manufacturing process.
Fleet plough groove isolation structure is by forming earlier groove in Semiconductor substrate, and then fills the dielectric material and form in groove.At publication number is in the Chinese patent application file of CN 1649122A, disclose a kind of shallow trench isolation from manufacture method.Fig. 1 to Fig. 5 be the disclosed shallow trench isolation of described Chinese patent application file from each step corresponding construction generalized section of manufacture method.
Please refer to Fig. 1, Semiconductor substrate 12 is provided, on described Semiconductor substrate 12, form pad oxide 12A, then on described pad oxide 12A, form silicon nitride layer as first hard mask layer 14, on described first hard mask layer 14, form the second hard mask layer 14B, on the described second hard mask layer 14B, form photoresist layer 16A, and the described photoresist layer 16A of patterning forms the opening 16B that the described second hard mask layer 14B is exposed in the bottom.
As shown in Figure 2, the second hard mask layer 14B, first hard mask layer 14 and the pad oxide 12A of the described opening 16B of etching bottom form opening 16C, and the surface of described Semiconductor substrate 12 is exposed in the bottom of described opening 16C.
As shown in Figure 3, remove described photoresist layer 16A, the Semiconductor substrate 12 of the described opening 16C of etching bottom forms groove 18 in described Semiconductor substrate 12.
As shown in Figure 4, form cushion oxide layer 20 on described groove 18 surfaces.Filling oxide layer 22 in described groove 18 is removed the described second hard mask layer 14B by cmp then and is gone up unnecessary oxide layer 22 and the described second hard mask layer 14B.
As shown in Figure 5, first hard mask layer 14 as described in removing by wet etching (as phosphoric acid), and remove described pad oxide 12A by hydrofluoric acid solution.
Yet; above-mentioned shallow trench isolation from manufacture method in; usually can form weakness (weak point) defective in the top of the groove of the fleet plough groove isolation structure that forms; above-mentioned wet-etching technology makes described weakness defective further worsen; form depression defect, shown in the fringe region 25 as shown in Figure 5.This depression defect can influence isolation effect, and the performance of semiconductor device that can cause forming descends.
Summary of the invention
The invention provides a kind of manufacture method of fleet plough groove isolation structure, method of the present invention can be avoided or reduce in the fleet plough groove isolation structure manufacture process and form the weakness defective in the groove top.
The manufacture method of a kind of fleet plough groove isolation structure provided by the invention comprises:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with groove;
Described groove top is carried out the oxygen gas plasma treatment process;
After described oxygen gas plasma treatment process, described groove is carried out cleaning, remove the oxide skin(coating) of described groove top;
Execute described cleaning filled media material in described groove afterwards.
Optionally, also include the plasma of fluoro-gas in the oxygen gas plasma in described oxygen gas plasma treatment process.
Optionally, described fluoro-gas comprises CF
4, C
2F
6, SF
6, NF
3In a kind of or the combination.
Optionally, described oxygen gas plasma treatment process is a remote plasma treatment technology.
Optionally, also be included in before the described wet clean process, described trenched side-wall carried out the step of removing etch polymers.
Optionally, described groove top being carried out the oxygen gas plasma treatment process carries out after the step of removing etch polymers.
Optionally, described groove top being carried out the oxygen gas plasma treatment process carried out before the step of removing etch polymers.
Optionally, the step of formation groove is as follows in described Semiconductor substrate:
On described Semiconductor substrate, form pad silicon oxide layer and hard mask layer successively;
Form the pattern of definition groove in described hard mask layer, described bottom portion is exposed described pad silicon oxide layer;
Etching is removed the pad silicon oxide layer of the bottom portion of described groove, and continues the described Semiconductor substrate of etching, forms groove in described Semiconductor substrate.
Optionally, before described groove top is carried out the oxygen gas plasma treatment process, remove the part pad silicon oxide layer of described groove top, described pad silicon oxide layer is shunk, with the part surface of the Semiconductor substrate of exposing described groove top towards described hard mask layer bottom.
Optionally, the method for removing described part pad silicon oxide layer is the hydrofluoric acid solution etching technics.
Compared with prior art, the present invention has the following advantages:
By the groove top is carried out the oxygen gas plasma treatment process, with oxygen gas plasma described groove top is carried out oxidation technology, form oxide; And remove described oxide by follow-up cleaning, can make groove top circular arcization; Because oxygen gas plasma has stronger activity, when using oxygen gas plasma that described slot wedge is handled, oxygen gas plasma can fully react with the Semiconductor substrate of groove top, generate oxide, and, plasma also has the bombardment effect, and the oxide that can prune and generate at groove top sharp corner helps reaction and proceeds; Follow by after the follow-up cleaning removal silica littler, the more slick and sly circular arc edge of curvature that can form at the groove top;
The gathering that can reduce or eliminate stress of this circular arc edge, can avoid the follow-up edge of in groove, filling dielectric process-induced damage groove on the one hand, form the weakness defective, and then avoid forming depression defect at the fleet plough groove isolation structure top that forms, help guaranteeing or improving the performance of the semiconductor device of formation; During the semiconductor device work that also can avoid on the other hand forming, electric field top assemble and influence electrically, help the raising of stability of semiconductor device.
Description of drawings
Fig. 1 to Fig. 5 be existing a kind of shallow trench isolation from each step corresponding structure generalized section of manufacture method;
Fig. 6 is the flow chart of embodiment of the manufacture method of fleet plough groove isolation structure of the present invention;
The generalized section of each step corresponding structure of the embodiment of the manufacture method of Fig. 7 to Figure 14 fleet plough groove isolation structure of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fleet plough groove isolation structure is widely used in the semiconductor integrated circuit manufacturing process as the isolation structure between semiconductor device and the device.The manufacturing process of typical fleet plough groove isolation structure is to form groove on Semiconductor substrate earlier, then fills dielectric in described groove, promptly forms fleet plough groove isolation structure.Wherein, groove generally forms by etching technics, and its width and the degree of depth are determined according to the characteristic of semiconductor device; The dielectric of filling is generally the silica material, and silica and Semiconductor substrate have binding characteristic preferably, and have the good insulation effect.
The invention provides a kind of manufacture method of fleet plough groove isolation structure, comprise Semiconductor substrate is provided, in described Semiconductor substrate, be formed with groove; Then, described groove top is carried out the oxygen gas plasma treatment process; Then described groove is carried out cleaning, remove the oxide skin(coating) of described groove top; Execute after the described oxygen gas plasma treatment process filled media material in described groove.
In the above-mentioned method,, described groove top is carried out oxidation technology, form oxide with oxygen gas plasma by the groove top is carried out the oxygen gas plasma treatment process; And remove described oxide by follow-up cleaning, make groove top circular arcization.Because oxygen gas plasma has stronger activity, when using oxygen gas plasma that described slot wedge is handled, oxygen gas plasma can fully react with the Semiconductor substrate of groove top, generates oxide; And plasma also has the bombardment effect, and the oxide that can prune and generate at groove top wedge angle everywhere helps reaction and proceeds; Follow by after the follow-up cleaning removal silica littler, the more slick and sly circular arc edge of curvature that can form at the groove top.
The gathering that can reduce or eliminate stress of this circular arc edge, can avoid the follow-up fill process of in groove, filling dielectric to damage the edge of groove on the one hand, form the weakness defective, and then avoid forming depression defect at the fleet plough groove isolation structure top that forms, help guaranteeing or improving the performance of the semiconductor device of formation.Also can reduce when device is worked charge carrier on the other hand and gather influence opening feature.Help the raising of stability of semiconductor device.
In addition, in the above-mentioned method, described groove is carried out cleaning, when removing the oxide skin(coating) of described groove top, also can remove the natural oxidizing layer of described trenched side-wall and bottom in the lump, so that form pad silicon oxide layer, and filled media material in the groove on described pad silicon oxide layer at described trenched side-wall and bottom.That is to say that the cleaning in the said method can be merged into a step with the cleaning of the nature layer of removing described trenched side-wall and bottom and carry out, and needn't carry out separately.
In addition, the oxygen gas plasma in described oxygen gas plasma treatment process can also include the plasma of fluoro-gas, and wherein, described fluoro-gas can comprise CF
4, C
2F
6, SF
6, NF
3In a kind of or the combination.
By in oxygen gas plasma, mixing the plasma of fluoro-gas, can improve the activity of oxygen gas plasma on the one hand, edge to described groove top also has corrasion on the other hand, more helps forming oxide skin(coating), helps the circular arcization of groove top.
Can adjust the ratio of oxygen gas plasma and fluoro-gas plasma by the flow of adjusting oxygen and fluoro-gas, be not described in detail here.Those skilled in the art can adjust accordingly according to arts demand.
In addition, in the above-mentioned method, described oxygen gas plasma treatment process is a remote plasma treatment technology.Because in the remote plasma, free radical in the plasma has certain distance apart from plasma discharge, when utilizing this free radical to carry out plasma treatment, can suppress to a certain extent or reduce to be positioned at the electronics of plasma discharge region, the corrasion of ion, and strengthen the reaction of free radical.Thereby; remote plasma treatment technology by oxygen and fluoro-gas; help obtaining better treatment effect in the groove top; and in processing procedure; the electronics in the plasma and the corrasion of ion pair trenched side-wall and bottom be can also suppress, trenched side-wall and bottom helped protecting.
Fig. 6 is the flow chart of embodiment of the manufacture method of fleet plough groove isolation structure of the present invention.
Please refer to Fig. 6, step S100 provides Semiconductor substrate, is formed with groove in described Semiconductor substrate.
Step S110 carries out the oxygen gas plasma treatment process to described groove top.
Step S120 after described oxygen gas plasma treatment process, carries out cleaning to described groove, removes the oxide skin(coating) of described groove top.
Step S130 executes described cleaning filled media material in described groove afterwards.
Be described in detail below in conjunction with the manufacture method of specific embodiment fleet plough groove isolation structure of the present invention.Need to prove; description to some details in the following examples only is schematic; it should not limit the protection range of claim improperly, and those skilled in the art can make corresponding modification, deletion and replacement without departing from the spirit and substance in the present invention.
Please refer to Fig. 7, Semiconductor substrate 100 is provided, this Semiconductor substrate 100 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, described Semiconductor substrate 100 also can be a kind of in silicon Germanium compound, the silicon gallium compound, described Semiconductor substrate 100 can comprise silicon on epitaxial loayer or the insulating barrier (Silicon On Insulator, SOI) structure.
On described Semiconductor substrate 100, form pad oxide 110, the method that forms described pad oxide 110 can be that high temperature furnace pipe oxidation, rapid thermal oxidation, original position steam produce a kind of in the oxidizing process, described pad oxide 110 is as the sticking and layer between hard mask layer that forms in the subsequent technique and Semiconductor substrate 100 surfaces, be used to increase the caking property between described hard mask layer and Semiconductor substrate 100 surfaces, and the stress between described hard mask layer of balance and described Semiconductor substrate 100 surfaces.In a further embodiment, described pad oxide 110 also can form by the method for chemical vapour deposition (CVD).
Then, form hard mask layer 120 on described pad oxide 110, hard mask layer described in the present embodiment 120 is a silicon nitride; The method that forms described hard mask layer 120 can be chemical vapour deposition (CVD).Described hard mask layer 120 is on the one hand as the hard mask of etching groove in described Semiconductor substrate 100, on the other hand as the layer that stops of the cmp planarization of the dielectric material of filling in groove.In other embodiments, described hard mask layer 120 can be a multilayer.
As shown in Figure 8, spin coating photoresist layer 130 on described hard mask layer 120, and form first opening 140 by exposure imaging technology, the surface of described hard mask layer 120 is exposed in the bottom of described first opening 140.In addition, before the described photoresist layer 130 of spin coating, can form the anti-reflecting layer (not shown) on described hard mask layer 120, described anti-reflecting layer can be an inorganic material, for example silicon oxynitride, or organic material; And then form photoresist layer 130 on described anti-reflecting layer, and exposure imaging forms first opening 140.
As shown in Figure 9, the hard mask layer 120 and the pad oxide 110 of described first opening of etching 140 bottoms form second opening 150, and the surface of described Semiconductor substrate 100 is exposed in the bottom of described second opening 150.Described etching is the anisotropic etching, for example is the plasma dry etching, and the etching gas of this plasma dry etching can be CF
4
As shown in figure 10, the Semiconductor substrate 100 of described second opening of etching 150 bottoms forms groove 160 in described Semiconductor substrate 100.The method of the described groove 160 of etching is the plasma dry etching, the etching gas that described plasma dry etching is selected for use will make the sidewall of described groove 160 comparatively smooth, has less silicon crystal lattice defective, and make the corner, bottom of described groove 160 comparatively level and smooth, described etching gas also will make described groove 160 sidewalls have the comparatively profile of inclination, for example can be 70 to 90 degree.The etching gas of described etching can be Cl
2With the mist of HBr, or HBr and O
2And Cl
2Mist, or HBr and NF
3With mist of He etc., enumerate no longer one by one here.The degree of depth of the groove 160 that etching forms is by the time control of etching.Then, remove described photoresist layer 120.
Then, described groove 160 top are carried out the oxygen plasma treatment process, form oxide skin(coating) in described groove 160 edge top, in the present embodiment, be silicon oxide layer, remove described oxide skin(coating) by cleaning then, make described groove 160 top circular arcizations.
Because oxygen gas plasma has stronger activity, when using oxygen gas plasma that described slot wedge is handled, oxygen gas plasma can fully react with the semiconductor substrate materials of groove 160 top, generates oxide; And plasma also has the bombardment effect, and the oxide that can prune and generate at groove 160 top wedge angles everywhere helps reaction and proceeds; Follow by after the follow-up cleaning removal silica littler, the more slick and sly circular arc edge of curvature that can form at groove 160 tops.
The gathering that can reduce or eliminate stress of this circular arc edge, can avoid the follow-up edge of in groove 160, filling dielectric process-induced damage groove on the one hand, form the weakness defective, and then avoid forming depression defect at the fleet plough groove isolation structure top that forms, help guaranteeing or improving the performance of the semiconductor device of formation.Can also reduce when device is worked charge carrier on the other hand and gather influence opening feature.Help improving stability of semiconductor device.
In addition, can also include the plasma of fluoro-gas in described oxygen gas plasma treatment process, wherein, described fluoro-gas can comprise CF
4, C
2F
6, SF
6, NF
3In a kind of or the combination.In the present embodiment, described fluorine-containing gas is CF
4Temperature during plasma treatment is 250 ℃.
By in oxygen gas plasma, mixing the plasma of fluoro-gas, can improve the activity of oxygen gas plasma on the one hand, edge to described groove 160 tops also has corrasion on the other hand, more helps forming oxide skin(coating), helps the circular arcization of groove 160 top.
Can adjust the ratio of oxygen gas plasma and fluoro-gas plasma by the flow of adjusting oxygen and fluoro-gas, be not described in detail here.Those skilled in the art can adjust accordingly according to arts demand.
In the present embodiment, described oxygen gas plasma treatment process is a remote plasma treatment technology.Because in the remote plasma, free radical in the plasma has certain distance apart from plasma discharge, when utilizing this free radical to carry out plasma treatment, can suppress to a certain extent or reduce to be positioned at the electronics of plasma discharge region, the corrasion of ion, and strengthen the reaction of free radical.Thereby; remote plasma treatment technology by oxygen and fluoro-gas; help obtaining better treatment effect in groove 160 top; and in processing procedure; the corrasion of electronics, ion pair groove 160 sidewalls and bottom in the plasma be can also suppress, groove 160 sidewalls and bottom helped protecting.
In addition, in the above-mentioned method, described groove 160 is carried out cleaning, when removing the oxide skin(coating) of described groove 160 top, also can remove the natural oxidizing layer of described groove 160 sidewalls and bottom in the lump, so that follow-up, and filled media material in the groove on described pad silicon oxide layer in described groove 160 sidewalls and bottom formation pad silicon oxide layer.That is to say that the cleaning in the said method can be merged into a step with the cleaning of the nature layer of removing described trenched side-wall and bottom and carry out, and needn't carry out separately.
In addition, before carrying out described oxygen gas plasma treatment process, also can remove the part pad silicon oxide layer 110 of described groove 160 top earlier, described pad silicon oxide layer 110 is shunk towards described hard mask layer 120 bottoms, with the part surface of the Semiconductor substrate of exposing described groove 160 top, as shown in figure 11.Wherein said etching technics can be the wet etching of hydrofluoric acid solution.
By etched portions pad silicon oxide layer 110, the part surface of the Semiconductor substrate of described groove 160 top is exposed, and then carry out described oxygen gas plasma treatment process and cleaning, help the better effects if of described groove 160 top circular arcizations.
In addition, before described wet clean process, the step that can also comprise the polymer of removing the etching generation, wherein, polymer mainly is the etching polymer that etching agent and photoresist produce when forming described groove 160, this polymer can influence follow-up technology and carry out attached to the sidewall of described groove 160.Remove described polymer by the sulfuric acid solution cleaning in the present embodiment, certainly, also can use other technology to remove described polymer, do not enumerating one by one here.
Wherein, describedly groove 160 top are carried out the oxygen gas plasma treatment process can after the step of removing etch polymers, carry out, also can be in execution before.
Then, please refer to Figure 12, generate laying 180 on described groove 160 surfaces with thermal oxidation method.
Please refer to Figure 13, deposition medium material in described groove 160 and on the described hard mask layer 120, described dielectric material can be silica or silicon oxynitride.Medium described in the present embodiment is a silica material.The method that deposits described dielectric material can be a high density plasma CVD.It also can be other depositing operation.
Because the edge that described groove 160 tops have circular arcization, so in the technology of carrying out metallization medium layer, the etching technics in the high density plasma CVD technology can not cause damage to described groove top, can avoid the weakness defective.
Then, remove described hard mask layer 120 surfaces by chemical mechanical milling tech and go up unnecessary dielectric material, in described groove 160, form dielectric layer 190.
Please refer to Figure 14, remove described hard mask layer 120 and pad oxide 110 by wet etching.
The wet etching solution of removing described hard mask layer 120 can be phosphoric acid solution; Removing described pad oxide 110 wet etching solution can be hydrofluoric acid solution.
Because in the above-mentioned step described groove 160 top being carried out oxygen gas plasma handles, can avoid forming the weakness defective in groove 160 top, thereby after removing described hard mask layer 120 and pad oxide 110, the fleet plough groove isolation structure top that can avoid being formed on formation forms depression defect, helps improving the performance of the semiconductor device of formation.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the manufacture method of a fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with groove;
Described groove top is carried out the oxygen gas plasma treatment process;
After described oxygen gas plasma treatment process, described groove is carried out cleaning, remove the oxide skin(coating) of described groove top;
Execute described cleaning filled media material in described groove afterwards.
2. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: the plasma that also includes fluoro-gas in the oxygen gas plasma in described oxygen gas plasma treatment process.
3. the manufacture method of fleet plough groove isolation structure as claimed in claim 2, it is characterized in that: described fluoro-gas comprises CF
4, C
2F
6, SF
6, NF
3In a kind of or the combination.
4. as the manufacture method of claim 1 or 2 or 3 described fleet plough groove isolation structures, it is characterized in that: described oxygen gas plasma treatment process is a remote plasma treatment technology.
5. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: also be included in before the described wet clean process, described trenched side-wall carried out the step of removing etch polymers.
6. the manufacture method of fleet plough groove isolation structure as claimed in claim 5 is characterized in that: described groove top is carried out the oxygen gas plasma treatment process carry out after the step of removing etch polymers.
7. the manufacture method of fleet plough groove isolation structure as claimed in claim 5 is characterized in that: described groove top is carried out the oxygen gas plasma treatment process carried out before the step of removing etch polymers.
8. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: the step that forms groove in described Semiconductor substrate is as follows:
On described Semiconductor substrate, form pad silicon oxide layer and hard mask layer successively;
Form the pattern of definition groove in described hard mask layer, described bottom portion is exposed described pad silicon oxide layer;
Etching is removed the pad silicon oxide layer of the bottom portion of described groove, and continues the described Semiconductor substrate of etching, forms groove in described Semiconductor substrate.
9. the manufacture method of fleet plough groove isolation structure as claimed in claim 8, it is characterized in that: before described groove top is carried out the oxygen gas plasma treatment process, remove the part pad silicon oxide layer of described groove top, described pad silicon oxide layer is shunk, with the part surface of the Semiconductor substrate of exposing described groove top towards described hard mask layer bottom.
10. the manufacture method of fleet plough groove isolation structure as claimed in claim 9, it is characterized in that: the method for removing described part pad silicon oxide layer is the hydrofluoric acid solution etching technics.
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| CN103137483A (en) * | 2011-11-30 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for eliminating sharp corner at top end of groove |
| CN103871841A (en) * | 2014-03-19 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Device isolation groove surface repairing method |
| CN104103569A (en) * | 2014-07-25 | 2014-10-15 | 上海华力微电子有限公司 | Forming method of shallow groove isolation structure |
| CN104143522A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench forming method |
| CN104347377A (en) * | 2013-08-07 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of NMOS (N-channel Metal Oxide Semiconductor) metal gate transistor |
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| CN109411404A (en) * | 2018-10-31 | 2019-03-01 | 武汉新芯集成电路制造有限公司 | Fleet plough groove isolation structure and its manufacturing method and semiconductor devices |
| CN112563190A (en) * | 2020-12-09 | 2021-03-26 | 广州粤芯半导体技术有限公司 | Method for forming shallow trench isolation structure |
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| US6541382B1 (en) * | 2000-04-17 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Lining and corner rounding method for shallow trench isolation |
| CN101075574A (en) * | 2007-06-12 | 2007-11-21 | 上海宏力半导体制造有限公司 | Method for producing shallow groove isolating structure of high-voltage assembly |
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| CN103137483A (en) * | 2011-11-30 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for eliminating sharp corner at top end of groove |
| CN103137483B (en) * | 2011-11-30 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | A kind of method eliminating sharp corner at top end of groove |
| CN104143522B (en) * | 2013-05-09 | 2017-05-24 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench forming method |
| CN104143522A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench forming method |
| CN104347377A (en) * | 2013-08-07 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of NMOS (N-channel Metal Oxide Semiconductor) metal gate transistor |
| CN103871841A (en) * | 2014-03-19 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Device isolation groove surface repairing method |
| CN105097695A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105097695B (en) * | 2014-05-22 | 2018-08-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
| CN104103569A (en) * | 2014-07-25 | 2014-10-15 | 上海华力微电子有限公司 | Forming method of shallow groove isolation structure |
| CN105448820A (en) * | 2014-09-02 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Active region forming method and semiconductor device |
| CN109411404A (en) * | 2018-10-31 | 2019-03-01 | 武汉新芯集成电路制造有限公司 | Fleet plough groove isolation structure and its manufacturing method and semiconductor devices |
| CN112563190A (en) * | 2020-12-09 | 2021-03-26 | 广州粤芯半导体技术有限公司 | Method for forming shallow trench isolation structure |
| CN113651292A (en) * | 2021-10-21 | 2021-11-16 | 绍兴中芯集成电路制造股份有限公司 | Method for forming film layer in cavity and method for manufacturing electronic device |
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| CN101770974B (en) | 2012-06-06 |
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