CN103811403A - Shallow groove isolation structure forming method - Google Patents
Shallow groove isolation structure forming method Download PDFInfo
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- CN103811403A CN103811403A CN201210454954.0A CN201210454954A CN103811403A CN 103811403 A CN103811403 A CN 103811403A CN 201210454954 A CN201210454954 A CN 201210454954A CN 103811403 A CN103811403 A CN 103811403A
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- mask layer
- isolation structure
- groove isolation
- fleet plough
- plough groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
A shallow groove isolation structure forming method comprises providing a semiconductor substrate; forming into a substrate oxidation layer on the semiconductor substrate; forming into a mask layer on the substrate oxidation layer; etching the mask layer and forming into an opening which penetrates through the mask layer; performing oxidation treatment on the lateral wall of the opening and forming into an oxidation layer; etching the oxidation layer, the mask layer, the substrate oxidation layer and the semiconductor until the remaining partial thickness mask layer and the oxidation layer which is arranged on the lateral wall of the mask layer and forming into an isolation groove; forming into a shallow groove isolation structure inside the isolation groove. The shallow groove isolation structure forming method has the advantages of avoiding a groove is formed in a joint between the shallow groove isolation structure and the semiconductor, improving the shape of the formed shallow groove isolation structure and accordingly improves the electrical performance of a semiconductor device which comprises the formed shallow groove isolation structure.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, 0.18 micron of following element (for example, between the active area of CMOS integrated circuit) adopts fleet plough groove isolation structure (STI) to carry out lateral isolation mostly.
Fleet plough groove isolation structure is as a kind of device separation, its concrete technology comprises: with reference to figure 1, Semiconductor substrate 101 is provided, in described Semiconductor substrate 101, be formed with successively from the bottom to top pad oxide layer 103, hard mask layer 105 and mask layer 109, in described mask layer 109, be formed with the opening 111 that exposes hard mask layer 105, described opening 111 has the shape corresponding with the isolation structure that defines active area; With reference to figure 2, take the mask layer 109 that comprises opening 111 in Fig. 1 as mask, hard mask layer 105, pad oxide layer 103 and Semiconductor substrate 101 described in etching successively, forms isolated groove 11 3; With reference to figure 3, remove mask layer 109 described in Fig. 2, and cvd silicon oxide material 115a in isolated groove 113 described in Fig. 2 and on the mask layer 109 of isolated groove 113 both sides; With reference to figure 4, silica material 115a described in planarization Fig. 3, to exposing hard mask layer 105, forms fleet plough groove isolation structure 115b; With reference to figure 5, remove hard mask layer 105 described in Fig. 4 by wet-etching technology.
But, the fleet plough groove isolation structure 115b forming by above-mentioned technique is easily prone to groove 117 at the seam crossing of itself and pad oxide layer 103, Semiconductor substrate 101, cause formed semiconductor device that " narrow width effect " (narrow width effect) easily occurs and the PMOS transistor forming easily forms electric leakage, had a strong impact on the electric property of the semiconductor device that comprises above-mentioned fleet plough groove isolation structure 11 5b.
In the United States Patent (USP) that is US7112513 in the patent No., can also find more relevant informations about fleet plough groove isolation structure.
Therefore, how to avoid formed fleet plough groove isolation structure to occur groove at itself and Semiconductor substrate seam crossing, just become one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fleet plough groove isolation structure, can avoid formed fleet plough groove isolation structure to occur groove at itself and the seam crossing of Semiconductor substrate, the electric property of the raising semiconductor device that forms.
For addressing the above problem, the invention provides a kind of formation method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form cushion oxide layer;
In described cushion oxide layer, form mask layer;
Mask layer described in etching, forms the opening that runs through described mask layer thickness;
The sidewall of described opening is carried out to oxidation processes, form oxide layer;
Oxide layer, mask layer, pad oxide layer and Semiconductor substrate described in etching, to the mask layer of remainder thickness and be positioned at the oxide layer on its sidewall, form isolated groove;
In described isolated groove, form fleet plough groove isolation structure.
Optionally, after formation runs through the opening of described mask layer thickness, also comprise: the mask layer to described opening both sides carries out dry etching, make the edge of described opening be circular-arc.
Optionally, the gas of described oxidation processes is the mist of oxygen and Krypton, and the flow of oxygen is 100sccm ~ 1000sccm, the flow of Krypton is 100sccm ~ 1000sccm, the temperature of oxidation processes is 0 ℃ ~ 100 ℃, and pressure is 5mTorr ~ 5Torr, and the time of oxidation processes is 10s ~ 300s.
Compared with prior art, technical solution of the present invention has the following advantages:
Before forming isolated groove, first the mask layer on opening sidewalls is carried out to oxidation processes, form oxide layer, again oxide layer, mask layer, pad oxide layer and Semiconductor substrate are carried out to etching, to the mask layer of remainder thickness and be positioned at the oxide layer on its sidewall, form isolated groove, then in described isolated groove, form fleet plough groove isolation structure.After forming fleet plough groove isolation structure, because the oxide layer being positioned on the mask layer sidewall of remainder thickness can stop etching solution to infiltrate the seam crossing of fleet plough groove isolation structure and Semiconductor substrate, avoid fleet plough groove isolation structure and the etching solution of seam crossing to react, and then avoid occurring groove at fleet plough groove isolation structure and Semiconductor substrate seam crossing, improve the pattern of the fleet plough groove isolation structure that forms, and then improve the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure.
Further, before the sidewall of opening is carried out to oxidation processes, the mask layer of opening both sides is carried out to dry etching, make the edge of opening be circular-arc, to reduce to form isolated groove remaining oxide layer afterwards, avoid when groove appears in fleet plough groove isolation structure and Semiconductor substrate seam crossing, avoid remaining oxide layer too much the performance of fleet plough groove isolation structure to be impacted, further improved the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the schematic diagram that prior art forms fleet plough groove isolation structure;
Fig. 6 to Figure 11 is the schematic diagram of formation method first embodiment of fleet plough groove isolation structure of the present invention;
Figure 12 to Figure 15 is the schematic diagram of formation method second embodiment of fleet plough groove isolation structure of the present invention;
Figure 16 to Figure 20 is the schematic diagram of formation method the 3rd embodiment of fleet plough groove isolation structure of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, in existing technique, be prone to groove at the seam crossing of fleet plough groove isolation structure and Semiconductor substrate, had a strong impact on the performance of the semiconductor device that comprises fleet plough groove isolation structure.
Inventor finds through research: after isolated groove forms, in isolated groove and on the mask layer of isolated groove both sides when cvd silicon oxide material, because silica material is different from the material of Semiconductor substrate, silica material is combined not tight with Semiconductor substrate, in the time removing hard mask layer by wet-etching technology, etching solution easily infiltrates the seam crossing of silica material and Semiconductor substrate, cause partial oxidation silicon materials to be etched, form groove at the seam crossing of silica material and Semiconductor substrate.When formed fleet plough groove isolation structure is as the isolation structure between MOS device, in the time that Semiconductor substrate is carried out to Implantation, the existence of groove can cause adulterating ion more easily to the Semiconductor substrate diffusion of grid structure below, and then cause the channel length of MOS device to shorten, its impact of performance (as: threshold voltage) on the short MOS device of channel length is more obvious, occur " narrow width effect ", had a strong impact on the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure.
For above-mentioned defect, the invention provides a kind of formation method of fleet plough groove isolation structure, before forming isolated groove, first the mask layer on opening sidewalls is carried out to oxidation processes, form oxide layer, in the time forming isolated groove, retain the partial oxidation layer in isolated groove semiconductor substrates on two sides, after forming at fleet plough groove isolation structure, while removing the mask layer of remainder thickness, stop etching solution to infiltrate the seam crossing of fleet plough groove isolation structure and Semiconductor substrate, the fleet plough groove isolation structure that prevents seam crossing is etched, avoid forming groove at the seam crossing of fleet plough groove isolation structure and Semiconductor substrate, improve the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure.
Be elaborated below in conjunction with accompanying drawing.
The first embodiment
With reference to figure 6, Semiconductor substrate 201 is provided, in described Semiconductor substrate 201, be formed with successively from the bottom to top cushion oxide layer 203 and mask layer 205a.
In the present embodiment, the material of described Semiconductor substrate 201 is monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, the present invention does not limit this.
Described mask layer 205a is single layer structure, and the material of described mask layer 205a is silicon nitride or polysilicon.
The material of described cushion oxide layer 203 is silica, can form by thermal oxidation technology or chemical vapor deposition method.The defect that described pad oxide layer 203 exists in order to repairing semiconductor substrate 201 surface, improves the conjugation of mask layer 205a and Semiconductor substrate 201, avoids mask layer 205a and Semiconductor substrate 201 in conjunction with bad and peel off from Semiconductor substrate 201.
In addition, because silicon nitride has stress, in the time that the material of described mask layer 205a is silicon nitride, described pad oxide layer 203, to mask layer 205a and 201 buffer actions of Semiconductor substrate, avoids the stress in mask layer 205a to impact Semiconductor substrate 201.
Continue with reference to figure 6, form the opening 211 that runs through described mask layer 205a thickness, described opening 211 is corresponding with the shape of the fleet plough groove isolation structure of follow-up formation.
With reference to figure 7, oxidation processes is carried out in the 205a of mask layer described in Fig. 6 surface (comprising the upper surface of mask layer 205a and the sidewall of opening 211), form oxide layer 207a.
The method of described oxidation processes is free-radical oxidation (radical oxidation), and the reacting gas of described oxidation processes is Krypton (Kr) and oxygen (O
2) mist, the flow of oxygen is 100sccm ~ 1000sccm, the flow of Krypton is 100sccm ~ 1000sccm, the temperature of oxidation processes is 0 ℃ ~ 100 ℃, pressure is 5mTorr ~ 5Torr, the time of oxidation processes is 10s ~ 300s.
In the present embodiment, in the time that the material of described mask layer 205a is silicon nitride, the material of the oxide layer 207a that forms comprises the compound such as silica, silicon oxynitride; In the time that the material of described mask layer 205a is polysilicon, the material of the oxide layer 207a that forms is silica.
In other embodiments, after described oxide layer 207a forms, also can clean described oxide layer 207a by the mixed solution of hydrochloric acid and hydrofluoric acid, be formed the thickness of oxide layer 207a with further attenuate.
With reference to figure 8, the 207a of oxide layer described in Fig. 7, mask layer 205b, pad oxide layer 203 and Semiconductor substrate 201 are carried out to etching, to the mask layer 205c of remainder thickness and be positioned at the oxide layer 207b on its sidewall, form isolated groove 213.
In the present embodiment, the method for oxide layer 207a, mask layer 205b, pad oxide layer 203 and Semiconductor substrate 201 being carried out to etching is anisotropic dry etch, and the etching gas of described anisotropic dry etch is HBr, N
2and NF
3mist, the flow of HBr is 100sccm ~ 500sccm, N
2flow be 5sccm ~ 200sccm, NF
3flow be 5sccm～100sccm, power is that 100W ~ 2000W, bias generator power are 100W ~ 500W, etch period is 10s ~ 300s.
Due to the good directionality of described anisotropic dry etch, can vertically carry out etching to oxide layer 207a, mask layer 205b, pad oxide layer 203 and Semiconductor substrate 201 simultaneously, in the time forming isolated groove 213, also remove mask layer 205b and the oxide layer 207a of segment thickness, made the thinner thickness of mask layer 205c and oxide layer 207b in pad oxide layer 203.
With reference to figure 9, layer deposited isolating 215a on the oxide layer 207b of isolated groove 213 described in Fig. 8 and isolated groove 213 both sides and mask layer 205c.
In the present embodiment, the material of described separator 215a is silica, can deposit by thermal oxidation technology or chemical vapor deposition method, but the invention is not restricted to this.
With reference to Figure 10, separator 215a described in planarization Fig. 9, to exposing described oxide layer 207b and mask layer 205c, forms fleet plough groove isolation structure 215b.
In the present embodiment, the method for separator 215a is chemical mechanical milling tech (CMP) described in planarization.In the time that the material of described mask layer 205c is silicon nitride, it also can be used as the stop-layer in planarization separator 215a process, avoids chemical mechanical milling tech to cause damage to pad oxide layer 203 and Semiconductor substrate 201.
With reference to Figure 11, remove the 205c of mask layer described in Figure 10 by wet-etching technology.
In the present embodiment, in the time that the material of described mask layer 205c is silicon nitride, the etching solution of described wet etching is phosphoric acid solution, and in described phosphoric acid solution, the volume ratio of phosphoric acid and water is 1:1 ~ 1:20, and the temperature of phosphoric acid solution is 100 ℃ ~ 250 ℃.
In the time that the material of described mask layer 205c is polysilicon, the etching solution of described wet etching is TMAH(tetramethyl aqua ammonia) solution.
In the time removing described mask layer 205c by wet-etching technology, described oxide layer 207b can effectively stop etching solution to infiltrate the seam crossing of Semiconductor substrate 201 and fleet plough groove isolation structure 215b, avoid the fleet plough groove isolation structure 215b of seam crossing because reacting and be removed with etching solution, and then avoid occurring groove at the seam crossing of fleet plough groove isolation structure 215b and Semiconductor substrate 201, the pattern that makes fleet plough groove isolation structure 215b better, isolation effect is better, improved the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure 215b.
It should be noted that, the present embodiment is forming after fleet plough groove isolation structure 215b, the oxide layer 207b of fleet plough groove isolation structure 215b and Semiconductor substrate 201 seam crossings does not remove, but, because oxide layer 207b is the material that comprises silica, it is insulator, can equally with fleet plough groove isolation structure 215b play buffer action, little to the performance impact of semiconductor device.
The second embodiment
With reference to Figure 12, Semiconductor substrate 301 is provided, in described Semiconductor substrate 301, be formed with successively from the bottom to top cushion oxide layer 303 and mask layer 305a, in described mask layer 305a, be formed with the opening 311 that exposes pad oxide layer 303.
With reference to Figure 13, the mask layer 305a of the both sides of opening 311 described in Figure 12 is carried out to etching, make the edge of described opening 311 be circular-arc., make the edge of the mask layer 305b after etching be circular-arc.
In the present embodiment, the method for the mask layer 305a of opening 311 both sides being carried out to etching is dry etching.Be CF as adopted etching gas
4, CHF
3, Ar, He and O
2mist, CF
4flow be 50sccm ~ 500sccm, CHF
3flow be 50sccm ~ 500sccm, the flow of Ar is 100sccm ~ 500sccm, the flow of He is 50sccm ~ 500sccm, O
2flow be 10sccm ~ 100sccm, power is that 100W ~ 1000W, bias generator power are 100W ~ 1000W, etch period is 10s ~ 300s.But the invention is not restricted to this, it also can adopt and well known to a person skilled in the art that other lithographic methods make the edge of described opening 311 be circular-arc.
With reference to Figure 14, oxidation processes is carried out on surface to the 305a of mask layer described in Figure 13 (comprising that the upper surface of mask layer 305a and edge are the sidewall of circular-arc opening 311), forms oxide layer 307a.
In the present embodiment, the method for the surface of mask layer 305a being carried out to oxidation processes is identical with the first embodiment, does not repeat them here.
With reference to Figure 15, the 307a of oxide layer described in Figure 14, mask layer 305b, pad oxide layer 303 and Semiconductor substrate 301 are carried out to etching, to the mask layer 305d of remainder thickness and be positioned at the oxide layer 307b on its sidewall, form isolated groove (not shown); And in formed isolated groove, fill full isolated material, form fleet plough groove isolation structure 315b.
In the present embodiment, form isolated groove and in isolated groove, form the method for fleet plough groove isolation structure 315b identical with the first embodiment, do not repeat them here.
In the present embodiment, before the sidewall of opening 311 is carried out to oxidation processes, first mask layer 305a is carried out to etching, make the edge of mask layer 305b split shed 311 after etching be circular-arc; In the time that mask layer 305b is carried out to oxidation processes, then by the thickness of the upper oxide layer 307a of mask layer 305c after control oxidation processes control oxidation processes; In the time forming isolated groove, can reduce the volume of isolated groove both sides oxide layer 307b, utilizing oxide layer 307b to stop etching solution to infiltrate fleet plough groove isolation structure 315b and Semiconductor substrate 301 seam crossings, avoid when seam crossing forms groove, reduce the impact of oxide layer 307b on formed fleet plough groove isolation structure 315b performance, further improved the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure 315b.
The 3rd embodiment
With reference to Figure 16, Semiconductor substrate 401 is provided, in described Semiconductor substrate 401, be formed with successively from the bottom to top cushion oxide layer 403 and mask layer.
In the present embodiment, described mask layer is double-decker, and described mask layer comprises the first mask layer 405a being positioned in pad oxide layer 403 and is positioned at the second mask layer 409a on the first mask layer 405a.
In the present embodiment, the material of described the second mask layer 409a is silica, and the formation method of described the second mask layer 409a is thermal oxidation technology or chemical vapor deposition method, but the invention is not restricted to this.
Continue with reference to Figure 16, form the opening 411 that runs through described the first mask layer 405a and the second mask layer 409a, described opening 411 is corresponding with the shape of the fleet plough groove isolation structure of follow-up formation.
The technique that forms described opening 411 is conventionally known to one of skill in the art, does not repeat at this.
With reference to Figure 17, the sidewall of Figure 16 split shed 411 is carried out to oxidation processes, form oxide layer 407.
In the present embodiment, in the time that the sidewall of Figure 16 split shed 411 is carried out to oxidation processes, the shielding rete 405a of first on the upper surface to the second mask layer 409a, opening 411 sidewalls and the second mask layer 409a carry out oxidation processes simultaneously.But because the material of the second mask layer 409a is silica, after oxidation processes, the material of the second mask layer 409 does not change; And the material of the first mask layer 405a is polysilicon or silicon nitride, after oxidation processes, the second mask layer 409a surface on opening 411 sidewalls forms oxide layer 407.The thickness of oxide layer 407 can accurately be controlled by described oxidation processes, and its height can accurately be controlled by the thickness of mask layer 405b.
In the present embodiment, the method for the sidewall of opening 411 being carried out to oxidation processes is identical with the first embodiment, does not repeat at this.
Continue with reference to Figure 17, described the second mask layer 409a, pad oxide layer 403 and Semiconductor substrate 401 are carried out to etching, to the mask layer of remainder thickness, form isolated groove 413.
In the present embodiment, form after isolated groove 413, the mask layer of remainder thickness comprises the second mask layer 409b of the first mask layer 405b and segment thickness.
In other embodiments, the mask layer of remainder thickness can be only also the first mask layer 405b.
In the present embodiment, the method for described the second mask layer 409a, pad oxide layer 403 and Semiconductor substrate 401 being carried out to etching is anisotropic dry etch.The gas of described anisotropic dry etch is HBr, N
2and NF
3mist, the flow of HBr is 100sccm ~ 500sccm, N
2flow be 5sccm ~ 200sccm, NF
3flow be 5sccm ~ 100sccm, power is that 100W ~ 2000W, bias generator power are 100W ~ 500W, etch period is 10s ~ 300s.
Due to the good directionality of described anisotropic dry etch, can vertically carry out etching to the second mask layer 409a, pad oxide layer 403 and Semiconductor substrate 401 simultaneously, without formation mask in the situation that, form isolated groove 413.
With reference to Figure 18, in isolated groove 413 described in Figure 17 and on the second mask layer 409b of isolated groove 413 both sides, deposit isolated material 415a.
The material of the 415a of isolated material described in the present embodiment is identical with formation method with the material of isolated material 215a in the first embodiment respectively with formation method, does not repeat them here.
With reference to Figure 19, isolated material 415a described in planarization Figure 18, to exposing described oxide layer 407 and mask layer 405b, forms fleet plough groove isolation structure 415b.
In the present embodiment, the method for isolated material 415a is chemical mechanical milling tech described in planarization.
With reference to Figure 20, remove the 405b of mask layer described in Figure 19 by wet-etching technology.
In the present embodiment, the method for removing described mask layer 405b is identical with the removal method of mask layer 205c in the first embodiment, does not repeat them here.
In the present embodiment, because the upper surface of mask layer 405a is covered by the second mask layer 409a, 407 of described oxide layers are formed at mask layer 405b surface on the sidewall of opening 411, its thickness can be controlled by oxidation processes, and the height of oxide layer 407 can be controlled by the thickness of controlling the mask layer 405a that forms, therefore, the present embodiment can accurately be controlled the follow-up volume that is formed at Semiconductor substrate 401 and fleet plough groove isolation structure 415b seam crossing oxide layer 407, in guaranteeing that fleet plough groove isolation structure and Semiconductor substrate seam crossing do not occur groove, reduce the impact of oxide layer 407 on formed fleet plough groove isolation structure performance, improve the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure 415b.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for fleet plough groove isolation structure, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form cushion oxide layer;
In described cushion oxide layer, form mask layer;
Mask layer described in etching, forms the opening that runs through described mask layer thickness;
The sidewall of described opening is carried out to oxidation processes, form oxide layer;
Oxide layer, mask layer, pad oxide layer and Semiconductor substrate described in etching, to the mask layer of remainder thickness and be positioned at the oxide layer on its sidewall, form isolated groove;
In described isolated groove, form fleet plough groove isolation structure.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, described mask layer is single layer structure, and the material of described mask layer is polysilicon or silicon nitride.
3. the formation method of fleet plough groove isolation structure as claimed in claim 2, is characterized in that, after formation runs through the opening of described mask layer thickness, also comprises: the mask layer to described opening both sides carries out dry etching, makes the edge of described opening be circular-arc.
4. the formation method of fleet plough groove isolation structure as claimed in claim 3, is characterized in that, the etching gas of described dry etching is CF
4, CHF
3, Ar, He and O
2mist.
5. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, described mask layer is double-decker, described mask layer comprises the first mask layer being positioned in described cushion oxide layer and is positioned at the second mask layer on described the first mask layer, the material of described the first mask layer is polysilicon or silicon nitride, and the material of described the second mask layer is silica.
6. the formation method of fleet plough groove isolation structure as claimed in claim 5, is characterized in that, the mask layer of described remainder thickness at least comprises described the first mask layer.
7. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the gas of described oxidation processes is the mist of oxygen and Krypton, the flow of oxygen is 100sccm ~ 1000sccm, the flow of Krypton is 100sccm ~ 1000sccm, the temperature of oxidation processes is 0 ℃ ~ 100 ℃, and pressure is 5mTorr ~ 5Torr, and the time of oxidation processes is 10s ~ 300s.
8. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, forms fleet plough groove isolation structure and comprise in described isolated groove:
In oxide layer on mask layer and the sidewall thereof of remainder thickness He in described isolated groove, form separator;
Separator described in planarization, to the oxide layer exposing on mask layer and the sidewall thereof of remainder thickness, forms fleet plough groove isolation structure;
Remove the mask layer of remainder thickness by wet-etching technology.
9. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the method for oxide layer, mask layer, pad oxide layer and Semiconductor substrate is anisotropic dry etch described in etching.
10. the formation method of fleet plough groove isolation structure as claimed in claim 9, is characterized in that, the etching gas of described anisotropic dry etch is HBr, N
2and NF
3mist.
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| CN111627808A (en) * | 2019-02-28 | 2020-09-04 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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| CN111627808B (en) * | 2019-02-28 | 2023-10-20 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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