CN103137559B - The removing method of dummy poly and the manufacture method of CMOS metal gates - Google Patents
The removing method of dummy poly and the manufacture method of CMOS metal gates Download PDFInfo
- Publication number
- CN103137559B CN103137559B CN201110397447.3A CN201110397447A CN103137559B CN 103137559 B CN103137559 B CN 103137559B CN 201110397447 A CN201110397447 A CN 201110397447A CN 103137559 B CN103137559 B CN 103137559B
- Authority
- CN
- China
- Prior art keywords
- dummy poly
- pmos
- nmos
- patterned photo
- photo glue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of removing method of dummy poly, photoresist is utilized to carry out phosphonium ion dopant implant as mask to dummy poly, and at ashing photoresist, before cooling grid structure is exposed in atmosphere, and utilize the most of polysilicon of dioxysulfate aqueous cleaning grid structure brokenization, tetramethyl ammonium hydroxide solution is finally used to etch dummy poly, to remove dummy poly completely, achieve while removal dummy poly, minimize the effect of other semiconductor structures loss.Present invention also offers a kind of manufacture method of CMOS metal gates.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, particularly relate to a kind of removing method of dummy poly and the manufacture method of CMOS metal gates.
Background technology
Along with the development of semiconductor integrated circuit, existing semiconductor device, polysilicon gate as generally used in complementary metal oxide semiconductors (CMOS) (CMOS) device manifests following problem gradually: because grid loss causes gate insulator effective thickness to increase, alloy easily penetrates into substrate by polysilicon gate and causes threshold voltage to change, and is difficult to realize low-resistance value etc. in fine width.
For solving the problem, semiconductor technology evolves to substitute the semiconductor device of existing polysilicon gate with metal gates, and use high-k (high k) material as the semiconductor device of gate insulation layer, be referred to as high dielectric layer metal gate (HKMG, high-k metal-gate) device.Before generation metal gates, generally first form dummy poly (dummy poly) grid, continue process until interlayer dielectric layer (ILD), remove as pseudo-crystal silicon grid and substitute with real metal grid.According to the difference removing dummy poly grid mode, prior art is divided into entirety to remove and removes two kinds of techniques respectively, still for cmos device, as Fig. 1 a ~ Fig. 1 d illustrates the existing Making programme removing dummy poly grid technique respectively.As shown in Figure 1a, CMOS comprises nmos area and PMOS district, is formed with shallow trench isolation from 8 (STI) between nmos area and PMOS district; The NMOS dummy poly 6 nmos area being formed with NMOS height dielectric layer 1 and being arranged on NMOS height dielectric layer 1, is formed with NMOS sidewall oxide 4 in the both sides of NMOS height dielectric layer 1 and NMOS dummy poly 6, forms NMOS grid structure; PMOS district is formed with equally the PMOS sidewall oxide 5 of PMOS height dielectric layer 2, PMOS dummy poly 7 and PMOS height dielectric layer 2 and PMOS dummy poly 7 both sides, forms PMOS grid structure; After the above-mentioned semiconductor structure of formation, deposition interlayer insulating barrier 3 between NMOS sidewall oxide 4 and PMOS sidewall oxide 5, carries out cmp for the first time and removes unnecessary deposition materials, to expose dummy poly 6 and 7; Then as shown in Figure 1 b, NMOS grid structure forms the photoresist 9 covering NMOS grid structure, remove PMOS dummy poly 7 by dry etching; As illustrated in figure 1 c, after removing photoresist 9, whole CMOS deposits one deck PMOS metal work function layer 10, and at PMOS metal work function layer 10 depositing metal layers, as metallic aluminium (Al), carry out second time cmp, the PMOS metal work function layer 10 on removing layer insulating barrier 3 and unnecessary metal, just on the position of former PMOS dummy poly 7, define PMOS metal gates 11 like this to expose interlayer insulative layer 3; With same operation, mask covers PMOS grid structure with photoresist, utilize dry etching to remove NMOS dummy poly 6, remove the photoresist mask covering PMOS, deposition NMOS metal work function layer and metal level, carry out third time cmp, remove the NMOS metal work function layer 12 on interlayer insulative layer 3 and metal level, so just define NMOS metal gates 13 in the position of former NMOS dummy poly 6, and then, define high dielectric layer metal gate CMOS structure, as shown in Figure 1 d.
In the middle of actual process, when removing NMOS and PMOS dummy poly 6 and 7, twice dry etching will be carried out respectively, this can make interlayer insulative layer 3 have certain loss, and then make in whole CMOS structure, the height reduction of metal gates 11 and 13 formation of NMOS and PMOS, and the reduction of metal gates height can affect subsequent ion injection technology, and then affect high dielectric layer metal gate device performance, make device performance off-design standard; If use wet etching to remove dummy poly, due to the isotropism of wet etching, gate lateral wall oxide layer etc. is lost too when wet etching, affects device performance.
Summary of the invention
The invention provides a kind of removing method of dummy poly and the manufacture method of CMOS metal gates.
The technological means that the present invention adopts is as follows: a kind of removing method of dummy poly, comprising:
Substrate is formed the grid structure comprising high dielectric layer, dummy poly and sidewall oxide;
Form interlayer insulative layer at deposited on substrates, and carry out cmp to expose described dummy poly;
Described grid structure and interlayer insulative layer are formed patterned photo glue, and described patterned photo glue exposes described dummy poly;
With patterned photo glue for mask, phosphonium ion dopant implant is carried out to described dummy poly;
Described patterned photo glue is removed in ashing, is exposed in atmosphere by grid structure before cooling, and utilizes dioxysulfate aqueous cleaning grid structure;
Tetramethyl ammonium hydroxide solution is used to etch described dummy poly, to remove described dummy poly.
Further, the concentration of described phosphonium ion dopant implant is 10
15to 10
17, the energy of ion implantation is 2KV-50KV.
Further, described ashing temperature is 250 to 300 degrees Celsius.
Further, in the described dioxysulfate aqueous solution, the molar ratio of sulfuric acid and hydrogen peroxide is 5: 1, and described dioxysulfate concentration of aqueous solution is 73%.
Further, the concentration of described tetramethyl ammonium hydroxide solution is 5%-20%.
Present invention also offers a kind of manufacture method of CMOS metal gates, comprising:
Substrate defines nmos area and PMOS district, and formed between nmos area and PMOS district shallow trench isolation from; Nmos area and PMOS district are formed NMOS height dielectric layer and PMOS height dielectric layer respectively, and NMOS dummy poly and PMOS dummy poly, and form sidewall oxide in the both sides of the both sides of NMOS height dielectric layer, NMOS dummy poly and PMOS height dielectric layer, PMOS dummy poly;
Described NMOS sidewall oxide on substrate and between PMOS sidewall oxide deposition form interlayer insulative layer, and carry out cmp to expose NMOS dummy poly and PMOS dummy poly;
Described NMOS grid structure and interlayer insulative layer are formed the first patterned photo glue, and described first patterned photo glue exposes described PMOS dummy poly;
With described first patterned photo glue for mask, phosphonium ion injection is carried out to described PMOS dummy poly;
Described first patterned photo glue is removed in ashing, is exposed in atmosphere by PMOS dummy poly before cooling, and utilizes dioxysulfate aqueous cleaning PMOS dummy poly;
Form the second patterned photo glue covering described NMOS grid structure, and use tetramethyl ammonium hydroxide solution to etch described PMOS dummy poly, to remove described PMOS dummy poly;
Remove described second patterned photo glue, deposit PMOS metal work function layer and metal gates successively, and carry out first time cmp, to expose interlayer insulative layer;
Tetramethyl ammonium hydroxide solution is used to etch described NMOS dummy poly, to remove described NMOS dummy poly;
Deposit NMOS metal work function layer and metal gates successively, and carry out second time cmp, to expose interlayer insulative layer.
Further, the concentration that described phosphonium ion injects is 10
15to 10
17, the energy of ion implantation is 2KV-50KV.
Further, described ashing temperature is 250 to 300 degrees Celsius.
Further, in the described dioxysulfate aqueous solution, the molar ratio of sulfuric acid and hydrogen peroxide is 5: 1, and described dioxysulfate concentration of aqueous solution is 73%.
Further, the concentration of described tetramethyl ammonium hydroxide solution is 5%-20%.
Further, described PMOS metal work function layer material is TiN; Described NMOS metal work function layer material is TiAl; The metal gate material of described PMOS and NMOS is Al.
In the present invention, phosphonium ion is utilized to inject dummy poly, dummy poly is adulterated, and after ashing photoresist mask, in uncooled situation, the dummy poly of doping is contacted with air, moisture now in air can generate metaphosphoric acid with the phosphorus reaction in dummy poly, the metaphosphoric acid generated can be dissolved when the recycling dioxysulfate aqueous solution carries out cleaning dummy poly and form phosphoric acid, and phosphoric acid can react with dummy poly, therefore most of dummy poly is removed, TMAH solution is finally utilized to carry out wet etching, remove remaining dummy poly, can while removal dummy poly, minimize the loss of other semiconductor structures.
Accompanying drawing explanation
Fig. 1 a ~ Fig. 1 d is that prior art removes dummy poly grid technique formation HKMG cmos device schematic flow sheet respectively;
Fig. 2 is the method flow diagram that the present invention removes dummy poly;
Fig. 3 a ~ Fig. 3 f is the Making programme structural representation of CMOS metal gates of the present invention.
Embodiment
Be described principle of the present invention and feature below in conjunction with accompanying drawing, example, only for explaining the present invention, is not intended to limit scope of the present invention.
As shown in Figure 2, the invention provides a kind of method removing dummy poly, comprising:
Substrate is formed the grid structure comprising high dielectric layer, dummy poly and sidewall oxide;
Form interlayer insulative layer at deposited on substrates, and carry out cmp to expose dummy poly;
Grid structure and interlayer insulative layer are formed patterned photo glue, and patterned photo glue exposes dummy poly;
With patterned photo glue for mask, phosphonium ion dopant implant is carried out to dummy poly;
Patterned photo glue is removed in ashing, is exposed in atmosphere by grid structure before cooling, and utilizes dioxysulfate aqueous cleaning grid structure;
Tetramethyl ammonium hydroxide solution is used to etch dummy poly, to remove dummy poly.
With reference to a kind of embodiment shown in Fig. 3 a ~ Fig. 3 f, specifically describe and utilize the above-mentioned method removing dummy poly to manufacture the process of CMOS metal gates.
As shown in Figure 3 a, substrate defines nmos area and PMOS district, nmos area and PMOS district are formed NMOS height dielectric layer and 21 and PMOS height dielectric layer 22 respectively, and NMOS dummy poly 26 and PMOS dummy poly 27, and form sidewall oxide 24,25 in the both sides of the both sides of NMOS height dielectric layer 21, NMOS dummy poly 26 and PMOS height dielectric layer 22, PMOS dummy poly 27, form NMOS grid structure and PMOS grid structure;
NMOS sidewall oxide 24 on substrate and between PMOS sidewall oxide 25 deposition form interlayer insulative layer 23, and carry out cmp to expose NMOS dummy poly 26 and PMOS dummy poly 27;
With reference to Fig. 3 b, substrate is formed the first patterned photo glue 29, first patterned photo glue 29 and exposes PMOS dummy poly 27;
With the first patterned photo glue 29 for mask, carry out phosphonium ion injection to PMOS dummy poly, as preferably, the concentration that phosphonium ion injects is 10
15to 10
17, the energy of ion implantation is 2KV-50KV;
Described first patterned photo glue 29 is removed in ashing, preferred ashing temperature is 250 to 300 degrees Celsius, before cooling PMOS dummy poly 27 is exposed in atmosphere, and utilize dioxysulfate aqueous cleaning PMOS dummy poly 27, preferably, in the dioxysulfate aqueous solution, the molar ratio of sulfuric acid and hydrogen peroxide is 5: 1, and dioxysulfate concentration of aqueous solution is 73%.
Due to after ashing photoresist mask, in uncooled situation, the PMOS dummy poly 27 of Doping Phosphorus is contacted with air, moisture now in air can generate metaphosphoric acid with the phosphorus reaction in dummy poly, the metaphosphoric acid generated can be dissolved when the recycling dioxysulfate aqueous solution carries out cleaning dummy poly, and then formation phosphoric acid, most of PMOS dummy poly 27 can be removed by the phosphoric acid of generation.
As shown in Figure 3 c, form the second patterned photo glue 30 covering NMOS grid structure, Tetramethylammonium hydroxide TMAH solution is used to etch residual PMOS dummy poly 27 ', 5%-20% is preferably with the concentration removing residual PMOS dummy poly 27 ', Tetramethylammonium hydroxide TMAH solution; Due to the former corrosion rate higher than silicon dioxide of the corrosion rate of TMAH to silicon, silicon dioxide is then the main component of interlayer insulative layer, so utilizing TMAH wet etching to remove in the process of residual PMOS dummy poly 27 ', the loss of interlayer insulative layer can be reduced to minimum, compare and directly use isotropism wet etching to remove dummy poly, it has excellent performance in the loss of selectivity and interlayer insulative layer.
Remove the second patterned photo glue-line 30, as shown in Figure 3 d, deposit PMOS metal work function layer 31 and metal gates 32 successively, and carry out first time cmp, to expose interlayer insulative layer 23;
As shown in Figure 3 e, tetramethyl ammonium hydroxide solution is used to etch NMOS dummy poly, to remove NMOS dummy poly; Deposit NMOS metal work function layer 33 and metal gates 34 successively;
Carry out second time cmp, remove unnecessary NMOS metal work function layer 33 and metal gates 34, with reference to Fig. 3 f, to expose interlayer insulative layer 23, the final CMOS structure forming metal gates.
Wherein, PMOS metal work function layer material is preferably TiN; NMOS metal work function layer material is preferably TiAl; The metal gate material of PMOS and NMOS is preferably Al.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (9)
1. a removing method for dummy poly, comprising:
Substrate is formed the grid structure comprising high dielectric layer, dummy poly and sidewall oxide;
Form interlayer insulative layer at deposited on substrates, and carry out cmp to expose described dummy poly;
Described grid structure and interlayer insulative layer are formed patterned photo glue, and described patterned photo glue exposes described dummy poly;
With patterned photo glue for mask, phosphonium ion dopant implant is carried out to described dummy poly;
Described patterned photo glue is removed in ashing, is exposed in atmosphere by grid structure before cooling, and utilizes dioxysulfate aqueous cleaning grid structure, to remove part dummy poly;
Tetramethyl ammonium hydroxide solution is used to etch remaining dummy poly, to remove remaining dummy poly.
2. method according to claim 1, is characterized in that, described ashing temperature is 250 to 300 degrees Celsius.
3. method according to claim 1, is characterized in that, in the described dioxysulfate aqueous solution, the molar ratio of sulfuric acid and hydrogen peroxide is 5:1, and described dioxysulfate concentration of aqueous solution is 73%.
4. method according to claim 1, is characterized in that, the concentration of described tetramethyl ammonium hydroxide solution is 5%-20%.
5. a manufacture method for CMOS metal gates, comprising:
Substrate defines nmos area and PMOS district, and formed between nmos area and PMOS district shallow trench isolation from; Nmos area and PMOS district are formed NMOS height dielectric layer and PMOS height dielectric layer respectively, and NMOS dummy poly and PMOS dummy poly, and form sidewall oxide in the both sides of the both sides of NMOS height dielectric layer, NMOS dummy poly and PMOS height dielectric layer, PMOS dummy poly;
Described NMOS sidewall oxide on substrate and between PMOS sidewall oxide deposition form interlayer insulative layer, and carry out cmp to expose NMOS dummy poly and PMOS dummy poly;
Described NMOS grid structure and interlayer insulative layer are formed the first patterned photo glue, and described first patterned photo glue exposes described PMOS dummy poly;
With described first patterned photo glue for mask, phosphonium ion injection is carried out to described PMOS dummy poly;
Described first patterned photo glue is removed in ashing, is exposed in atmosphere by PMOS dummy poly before cooling, and utilizes dioxysulfate aqueous cleaning PMOS dummy poly, to remove part PMOS dummy poly;
Form the second patterned photo glue covering described NMOS grid structure, and use tetramethyl ammonium hydroxide solution to etch remaining PMOS dummy poly, to remove residue PMOS dummy poly;
Remove described second patterned photo glue, deposit PMOS metal work function layer and metal gates successively, and carry out first time cmp, to expose interlayer insulative layer;
Tetramethyl ammonium hydroxide solution is used to etch described NMOS dummy poly, to remove described NMOS dummy poly;
Deposit NMOS metal work function layer and metal gates successively, and carry out second time cmp, to expose interlayer insulative layer.
6. method according to claim 5, is characterized in that, described ashing temperature is 250 to 300 degrees Celsius.
7. method according to claim 5, is characterized in that, in the described dioxysulfate aqueous solution, the molar ratio of sulfuric acid and hydrogen peroxide is 5:1, and described dioxysulfate concentration of aqueous solution is 73%.
8. method according to claim 5, is characterized in that, the concentration of described tetramethyl ammonium hydroxide solution is 5%-20%.
9. method according to claim 5, is characterized in that, described PMOS metal work function layer material is TiN; Described NMOS metal work function layer material is TiAl; The metal gate material of described PMOS and NMOS is Al.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110397447.3A CN103137559B (en) | 2011-12-02 | 2011-12-02 | The removing method of dummy poly and the manufacture method of CMOS metal gates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110397447.3A CN103137559B (en) | 2011-12-02 | 2011-12-02 | The removing method of dummy poly and the manufacture method of CMOS metal gates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103137559A CN103137559A (en) | 2013-06-05 |
| CN103137559B true CN103137559B (en) | 2015-08-19 |
Family
ID=48497188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110397447.3A Active CN103137559B (en) | 2011-12-02 | 2011-12-02 | The removing method of dummy poly and the manufacture method of CMOS metal gates |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103137559B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517900B (en) * | 2013-09-27 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN106328510A (en) * | 2016-08-31 | 2017-01-11 | 上海华力微电子有限公司 | Metal gate forming method |
| CN108281382B (en) * | 2018-01-22 | 2021-01-15 | 京东方科技集团股份有限公司 | Display substrate manufacturing method and display substrate |
| CN108807397A (en) * | 2018-05-31 | 2018-11-13 | 武汉新芯集成电路制造有限公司 | A method of improving grid hole defect |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188212A (en) * | 2006-11-15 | 2008-05-28 | 株式会社瑞萨科技 | Method of manufacturing semiconductor device |
| CN101252083A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Method for cleaning polycrystalline silicon gate surface |
| CN101714526A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
| CN102237310A (en) * | 2010-04-29 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method of manufacturing same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI256688B (en) * | 2002-02-01 | 2006-06-11 | Grand Plastic Technology Corp | Method for wet etching of high k thin film at low temperature |
-
2011
- 2011-12-02 CN CN201110397447.3A patent/CN103137559B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188212A (en) * | 2006-11-15 | 2008-05-28 | 株式会社瑞萨科技 | Method of manufacturing semiconductor device |
| CN101252083A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Method for cleaning polycrystalline silicon gate surface |
| CN101714526A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
| CN102237310A (en) * | 2010-04-29 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103137559A (en) | 2013-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110620040B (en) | Method for improving process stability in production | |
| JP5404671B2 (en) | Semiconductor device | |
| JP6355139B2 (en) | Memory structure having self-aligned floating gate and control gate and associated method | |
| CN102148191B (en) | Formation method for contact hole | |
| CN104701164A (en) | Semiconductor device and method for manufacturing same | |
| CN104167391A (en) | Method for manufacturing CMOS structure | |
| CN105336660A (en) | Semiconductor device and formation method therefor | |
| CN103137559B (en) | The removing method of dummy poly and the manufacture method of CMOS metal gates | |
| CN104217954A (en) | Formation method of transistors | |
| CN103474391B (en) | Method for forming high-k metal-gate device contact hole | |
| CN104779147A (en) | Metal gate structure and preparation method thereof | |
| CN104752205A (en) | Semiconductor device and forming method thereof | |
| CN104752228B (en) | Semiconductor device structure and its manufacturing method | |
| CN105448730A (en) | Semiconductor structure and method of forming same | |
| CN105575908B (en) | The forming method of semiconductor structure | |
| CN104752215A (en) | Transistor forming method | |
| CN104143535A (en) | Method for manufacturing CMOS structure | |
| CN104900501A (en) | Semiconductor structure and forming method thereof | |
| CN102983104B (en) | The manufacture method of CMOS transistor | |
| CN105529265A (en) | MOS transistor and MOS transistor manufacturing method | |
| CN104752422A (en) | Semiconductor device and forming method thereof | |
| US7867901B2 (en) | Method for forming silicide in semiconductor device | |
| CN103377896B (en) | The manufacture method of high dielectric layer metal gate device | |
| CN109003899B (en) | Semiconductor structure, forming method thereof and forming method of fin field effect transistor | |
| CN102856179A (en) | Method for forming semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |