CN104517900B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN104517900B CN104517900B CN201310451415.6A CN201310451415A CN104517900B CN 104517900 B CN104517900 B CN 104517900B CN 201310451415 A CN201310451415 A CN 201310451415A CN 104517900 B CN104517900 B CN 104517900B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 100
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- 239000012535 impurity Substances 0.000 description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002386 leaching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor substrate is provided, the laminated construction being made of boundary layer, high k dielectric layer, coating and the sacrificial gate material floor being laminated from bottom to top is formed on the NMOS area of Semiconductor substrate and PMOS areas；Removal is located at the sacrificial gate material floor in PMOS areas to form groove；The first metal gates are formed in a groove；Part removal is positioned at the sacrificial gate material layer of NMOS area；Using the removal of the first remote plasma etch technique positioned at the remainder of the sacrificial gate material layer of NMOS area, another groove is formed；The residuals of cover surface exposed using the removal of the second remote plasma etch technique；The second metal gates are formed in another groove.According to the present invention it is possible to be independently adjusted the work function for the workfunction setting metal layer for being respectively formed in PMOS areas and NMOS area, damage when avoiding etching sacrificial gate material layer to coating and high k dielectric layer reduces the loss of interlayer dielectric layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method for forming high k- metal gates.
Background technology
In the manufacturing process of next generation's integrated circuit, for complementary metal oxide semiconductor（CMOS）Grid system
Make, the high k- metal gate process of generally use.For there is the CMOS compared with high technology node, the high k- metal gates work
Skill is usually post tensioned unbonded prestressed concrete technique, and implementation process is metal gates two after metal gates after first high k dielectric layer and rear high k dielectric layer
Kind.The former implementation process includes：Dummy gate structure is formed on a semiconductor substrate, and the dummy gate structure is by layer from bottom to top
Folded boundary layer, high k dielectric layer, coating（capping layer）It is formed with sacrificial gate material layer；In dummy gate structure
Both sides form side wall construction, remove the sacrificial gate material layer in dummy gate structure, the ditch left between side wall construction later
Workfunction layers are sequentially depositing in slot（workfunction metal layer）, barrier layer（barrier layer）And leaching
Moisten layer（wetting layer）；Carry out metal gate material（Usually aluminium）Filling.The implementation process of the latter includes：Half
Form dummy gate structure on conductor substrate, the dummy gate structure is by the sacrificial dielectric that is laminated from bottom to top and sacrifices grid material
The bed of material is formed；Side wall construction is formed in the both sides of dummy gate structure, removes the sacrificial dielectric and sacrificial in dummy gate structure later
Domestic animal gate material layers are sequentially depositing boundary layer, high k dielectric layer, coating, work function in the groove left between side wall construction
Metal layer, barrier layer and soakage layer；Carry out metal gate material（Usually aluminium）Filling.With feature sizes of semiconductor devices
Continuous reduction, after implementation after high k dielectric layer during metal gate process, removal sacrificial dielectric and sacrificial gate material layer it
Before the filling of laggard row metal grid material, need to be sequentially depositing boundary layer, high k dielectric layer, coating, workfunction metal
Layer, barrier layer and soakage layer, the process window of the deposition by dummy gate structure characteristic size very big limitation, described in implementation
The normal filling of subsequent metal grid material will be influenced after deposition, and after the first high k dielectric layer of implementation during metal gate process,
After sacrificial gate material layer is removed carry out metal gate material filling before, only need to be sequentially depositing workfunction layers,
Barrier layer and soakage layer do not interfere with the normal filling of subsequent metal grid material.
After the first high k dielectric layer of implementation during metal gate process, usually there are the sacrifice grids that two kinds remove dummy gate structure
The mode of material layer.First way is sacrificial in the dummy gate structure of NMOS area and PMOS areas of the removal simultaneously in CMOS
Domestic animal gate material layers, for example, first, as shown in Figure 1A, isolation structure 101 divides Semiconductor substrate 100 for NMOS area and PMOS
Area is each formed with dummy gate structure 102 in NMOS area and PMOS areas, as an example, dummy gate structure 102 by being laminated from bottom to top
High k dielectric layer 102a and sacrificial gate material layer 102b form, between high k dielectric layer 102a and Semiconductor substrate 100 also shape
Into interfacial TCO layer, coating is also formed between high k dielectric layer 102a and sacrificial gate material layer 102b, to put it more simply, diagram
In omitted, be formed with side wall construction 103 in the both sides of dummy gate structure 102, sequentially form connect on a semiconductor substrate 100
After contact hole etching stopping layer 104 and interlayer dielectric layer 105, chemical mechanical grinding is performed to expose the top of dummy gate structure 102；
Then, as shown in Figure 1B, while removal is formed in sacrificial gate material floor in the dummy gate structure 102 in NMOS area and PMOS areas
102b, deposition suitable for PMOS areas workfunction layers 106, covering positioned at NMOS area and PMOS areas interlayer dielectric layer 105,
Side wall construction 103 and high k dielectric layer 102a；Then, as shown in Figure 1 C, by etching workfunction metal of the removal positioned at NMOS area
Layer 106, deposition is suitable for the workfunction layers 107 of NMOS area, and covering is positioned at interlayer dielectric layer 105, the side wall knot of NMOS area
Structure 103 and high k dielectric layer 102a and the workfunction layers 106 positioned at PMOS areas；Finally, as shown in figure iD, it is sequentially depositing
Barrier layer 108 and metal gate material layer 109 to cover workfunction layers 107, perform chemical mechanical grinding to expose interlayer
Dielectric layer 105 completes the making of high k- metal gates.The shortcomings that such mode is, the high k- metal gates positioned at PMOS areas
In be formed with workfunction layers 107 suitable for NMOS area, therefore inconvenient separately adjustment is located at NMOS area and PMOS
The work function of workfunction layers in the high k- metal gates in area.
The second way is that removal is located at the sacrificial gate in the dummy gate structure in the NMOS area in CMOS and PMOS areas respectively
Pole material layer, for example, first, as shown in Figure 2 A, isolation structure 201 divides Semiconductor substrate 200 for NMOS area and PMOS areas,
NMOS area and PMOS areas are each formed with dummy gate structure 202, as an example, dummy gate structure 202 is by the high k that is laminated from bottom to top
Dielectric layer 202a and sacrificial gate material layer 202b is formed, and boundary is also formed between high k dielectric layer 202a and Semiconductor substrate 200
Face layer, coating is also formed between high k dielectric layer 202a and sacrificial gate material layer 202b, to put it more simply, giving in diagram
It omits, is formed with side wall construction 203 in the both sides of dummy gate structure 202, sequentially forms contact pitting on semiconductor substrate 200
After carving stop-layer 204 and interlayer dielectric layer 205, chemical mechanical grinding is performed to expose the top of dummy gate structure 202；Then,
As shown in Figure 2 B, patterned photoresist layer 206 is formed, only covers NMOS area, and is mask with the photoresist layer 206, is led to
Overetch removal is formed in the sacrificial gate material floor 202b in the dummy gate structure 202 in PMOS areas；Then, as shown in Figure 2 C,
The photoresist layer 206 is removed, is sequentially depositing workfunction layers 207a, barrier layer 207b and metal gate suitable for PMOS areas
Pole material layer 207c performs chemical mechanical grinding to expose interlayer dielectric layer 205, completes the high k- metal gates positioned at PMOS areas
207 making；Then, as shown in Figure 2 D, another patterned photoresist layer is formed, only covers PMOS areas, and with described another
Photoresist layer is mask, the sacrificial gate material layer 202b being formed in the dummy gate structure 202 of NMOS area by etching removal,
Then, remove the photoresist layer 206, be sequentially depositing the workfunction layers 208a suitable for NMOS area, barrier layer 207b and
Metal gate material layer 207c performs chemical mechanical grinding to expose interlayer dielectric layer 205, completes the high k- gold positioned at NMOS area
Belong to the making of grid 208.Although such mode can overcome aforementioned first way there are the shortcomings that, it still has following
Problem：Since the corrosive liquid of wet etching is insensitive on the dopant in sacrificial gate material layer 202b and then influences etching speed
Therefore rate, wet etching removal sacrificial gate material layer 202b is replaced using dry etching；Since dry etching is to sacrificing grid
The etching selectivity of material layer 202b and interlayer dielectric layer 205 is poor, the loss of interlayer dielectric layer 205 is caused to increase, Jin Erzao
Into the decline of metal gates height being subsequently formed, meanwhile, after removal sacrificial gate material layer 202b completely, to lower section
Coating causes to damage, and then causes plasma damage to the high k dielectric layer 202a below coating, leads to high k dielectric layer
202a through when dielectric breakdown（TDDB）Performance is remarkably decreased.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including：Step a)：It carries
For Semiconductor substrate, boundary layer, high k by being laminated from bottom to top are formed on the NMOS area of the Semiconductor substrate and PMOS areas
The laminated construction that dielectric layer, coating and sacrificial gate material layer are formed；Step b)：Removal is positioned at the sacrificial gate in the PMOS areas
Pole material layer is to form groove；Step c)：The first metal gates are formed in the groove；Step d)：Part removal is located at institute
State the sacrificial gate material layer of NMOS area；Step e)：The NMOS is located at using the removal of the first remote plasma etch technique
The remainder of the sacrificial gate material floor in area, forms another groove；Step f)：Using the second remote plasma etch technique
Remove the residuals for the cover surface exposed；Step g)：The second metal gates are formed in another groove.
Further, the step b) includes：Form the photoresist layer for only covering the NMOS area；Using the photoresist layer as
Mask implements the removal using dry method etch technology；The photoresist layer is removed using cineration technics.
Further, the technological parameter of the dry etching includes：The flow of etching gas HBr be 20-500sccm, pressure
For 2-40mTorr, power 100-2000W.
Further, the step d) includes：Form another photoresist layer for only covering the PMOS areas；With another light
Photoresist layer is mask, and implementing the part using another dry method etch technology removes.
Further, the technological parameter of another dry etching includes：Etching gas is HBr and O2, the flow of HBr is
50-100sccm, O2Flow be 0-10sccm, pressure 2-20mTorr, source power 100-1000W, bias power 20-
200W。
Further, after implementing the part removal, the thickness of the remaining sacrificial gate material layer is 30-100 angstroms.
Further, the technological parameter of first remote plasma etch includes：Etching gas H2Flow be 100-
2000sccm, temperature are 20-60 DEG C, pressure 0.5-2.0Torr, power 500-5000W.
Further, the technological parameter of second remote plasma etch includes：Etching gas is NF3And H2, NF3's
Flow is 5-50sccm, H2Flow for 100-2000sccm, temperature is 20-60 DEG C, pressure 0.5-2.0Torr, and power is
500-5000W。
Further, it after the step f) and before the step g), further includes described another using cineration technics removal
The step of one photoresist layer.
Further, before the step b), following step is further included：Side wall knot is formed in the both sides of the laminated construction
Structure；Source/drain region is formed in the Semiconductor substrate of the side wall construction both sides；The shape in the PMOS areas of the side wall construction both sides
Into embedded germanium silicon layer；Self-aligned silicide is formed on the top of the embedded germanium silicon layer and the source/drain region；Institute
State the contact etch stop layer and interlayer dielectric layer for being formed in Semiconductor substrate and the laminated construction being completely covered；Perform chemistry
Mechanical lapping is to expose the top of the laminated construction.
Further, after the material of the first metal gates and second metal gates described in sedimentary composition respectively, also
The step of including performing chemical mechanical grinding, until being terminated when exposing the interlayer dielectric layer.
Further, first metal gates include the first workfunction setting metal layer stacked gradually from bottom to top, resistance
Barrier and metal gate material layer；Second metal gates include the second workfunction setting metal stacked gradually from bottom to top
Layer, another barrier layer and another metal gate material layer.
Further, first workfunction setting metal layer includes one or more layers metal or metallic compound, forms
Material is the metal material suitable for the PMOS；Second workfunction setting metal layer includes one or more layers metal or gold
Belong to compound, constituent material is the metal material suitable for the NMOS
According to the present invention it is possible to it is independently adjusted the first work function setting for being respectively formed in the PMOS areas and NMOS area
The work function of metal layer and the second workfunction setting metal layer, by using described in remote plasma etch technique removal
Sacrificial gate material layer avoids damage of the etching to the coating and high k dielectric layer, reduces the interlayer dielectric layer
Loss.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A-Fig. 1 D are to be implemented successively according to the exemplary embodiment one of the existing method for forming high k- metal gates
The schematic cross sectional view for the device that step obtains respectively；
Fig. 2A-Fig. 2 D are to be implemented successively according to the exemplary embodiment two of the existing method for forming high k- metal gates
The schematic cross sectional view for the device that step obtains respectively；
Fig. 3 A- Fig. 3 F are to form the step of high k- metal gates are implemented successively according to the method for exemplary embodiment of the present
The schematic cross sectional view of the device obtained respectively；
Fig. 4 is the flow chart that high k- metal gates are formed according to the method for exemplary embodiment of the present.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
The high k- metal gates of formation method.Obviously, execution of the invention be not limited to semiconductor applications technical staff institute it is ripe
The specific details of habit.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention may be used also
With with other embodiment.
It should be understood that it when the term " comprising " and/or " including " is used in this specification, indicates described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment]
In the following, high k- metals are formed to describe method according to an exemplary embodiment of the present invention with reference to Fig. 3 A- Fig. 3 F and Fig. 4
The detailed step of grid.
With reference to Fig. 3 A- Fig. 3 F, method according to an exemplary embodiment of the present invention is shown and implements the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 3A, Semiconductor substrate 300 is provided, the constituent material of Semiconductor substrate 300, which may be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）, silicon is laminated on insulator（SSOI）, insulator upper strata
Folded SiGe（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And germanium on insulator（GeOI）Deng.As an example, at this
In embodiment, the constituent material of Semiconductor substrate 300 selects monocrystalline silicon.Isolation structure is formed in Semiconductor substrate 300
301, as an example, isolation structure 301 is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
In the present embodiment, isolation structure 301 is fleet plough groove isolation structure, and Semiconductor substrate 300 is divided for NMOS area and PMOS areas.Half
Various traps (well) structure is also formed in conductor substrate 300, to put it more simply, being omitted in diagram.
Laminated construction 302 is respectively formed in the NMOS area of Semiconductor substrate 300 and PMOS areas, as an example, lamination knot
Structure 302 includes the boundary layer 302a, high k dielectric layer 302b, coating 302c and the sacrificial gate material layer that are laminated from bottom to top
302d.The constituent material of boundary layer 302a includes Si oxide（SiOx）, effect is to improve high k dielectric layer 302b and semiconductor
Interfacial characteristics between substrate 300；The k values of high k dielectric layer 302b（Dielectric constant）Usually more than 3.9, constituent material packet
Include hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium,
Barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably hafnium oxide, zirconium oxide or aluminium oxide；The composition of coating 302c
Material includes titanium nitride or tantalum nitride, and effect is to prevent metal material in the workfunction setting metal layer that is subsequently formed to height
The diffusion of k dielectric layer 302b；The material of sacrificial gate material layer 302d includes polysilicon, silicon nitride or amorphous carbon, preferably more
Crystal silicon.
In addition, as an example, it is formed with side wall construction 303 in the both sides of laminated construction 302.Wherein, side wall construction 303 to
Include oxide skin(coating) and/or nitride layer less.Source/drain region is formed in the Semiconductor substrate 300 of 303 both sides of side wall construction,
To put it more simply, it is omitted in diagram.
Be formed with embedded germanium silicon layer 306 in the PMOS areas of 303 both sides of side wall construction, forming process generally include with
Lower step：∑ shape groove is formed in the PMOS areas of 303 both sides of side wall construction using the technique of first dry etching wet etching again；
Embedded germanium silicon layer 306 is formed using selective epitaxial growth process, to be filled up completely the ∑ shape groove, formation it is embedded
Germanium silicon layer 306 can adulterate boron, and low-pressure chemical vapor deposition may be used in the selective epitaxial growth process（LPCVD）, etc.
Gas ions enhance chemical vapor deposition（PECVD）, ultra-high vacuum CVD（UHVCVD）, rapid thermal CVD
（RTCVD）And molecular beam epitaxy（MBE）In one kind.It is described elder generation dry etching again the technique of wet etching specific steps such as
Under：The PMOS areas of 303 both sides of dry method etch technology longitudinal direction etching side wall structure are first used to form groove, in the present embodiment,
Using CF4With HBr as main etching gas, 40-60 DEG C of temperature, power 200-400W biases 50-200V, etching period according to
Depending on etch depth；Continue to etch the groove using isotropic dry method etch technology again, it is rectangular under the groove
Ovalisation groove forms bowl-shape groove, in the present embodiment, using Cl2And NF3As main etching gas, temperature 40-60
DEG C, power 100-500W biases 0-10V, and etching period is recessed according to the channel region in side wall to the PMOS areas of the bowl-shape groove
Depth depending on；The bowl-shape groove is finally etched using wet etching process extension, it is described wet to form the ∑ shape groove
The temperature of method etching is 30-60 DEG C, depending on the desired size of ∑ shape groove described in basis of time, generally 100-300s, at this
In embodiment, using tetramethylammonium hydroxide（TMAH）Corrosive liquid of the solution as the wet etching.
Self-aligned silicide is formed on the source/drain region of the top of embedded germanium silicon layer 306 and NMOS area, for letter
Change, it is illustrated that in omitted.The technique for forming self-aligned silicide is familiar with by those skilled in the art, and details are not described herein.
It is formed after self-aligned silicide, the contact hole that laminated construction 302 is completely covered is formed in Semiconductor substrate 300
Etching stopping layer 304 and interlayer dielectric layer 305.The preferred silicon nitride of material of contact etch stop layer 304, interlayer dielectric layer
The oxide that the 305 preferred using plasma enhancing chemical vapor deposition method of material is formed.Then, chemical machinery is performed to grind
Grind the top to expose laminated construction 302.
Then, as shown in Figure 3B, the photoresist layer 307 for only covering NMOS area is formed by the techniques such as expose, develop, and with
Photoresist layer 307 is mask, and removal is located at the sacrificial gate material floor 302d in PMOS areas to form groove 308.In the present embodiment
In, the removal is implemented using dry method etch technology, technological parameter includes：The flow of etching gas HBr is 20-500sccm,
Pressure is 2-40mTorr, and power 100-2000W, wherein mTorr represent milli millimetres of mercury, sccm represent cubic centimetre/point
Clock.After the dry etching is implemented, using wet etching process remove etch residues that the dry etching generates and
Impurity.
Then, as shown in Figure 3 C, photoresist layer 307 is removed, and the first metal gates 309 are formed in groove 308.As
Example, the first metal gates 309 include the first workfunction setting metal layer 309a, the barrier layer 309b that stack gradually from bottom to top
With metal gate material layer 309c.First workfunction setting metal layer 309a includes one or more layers metal or metallic compound,
Its constituent material is the metal material suitable for PMOS, including ruthenium, palladium, platinum, tungsten and its alloy, further includes above-mentioned metallic element
Carbide, nitride etc.；The material of barrier layer 309b includes tantalum nitride or titanium nitride, the material packet of metal gate material layer 309c
Include tungsten or aluminium.It should be noted that soakage layer can also be formed between barrier layer 309b and metal gate material layer 309c,
Constituent material includes titanium or titanium-aluminium alloy, and the effect for forming soakage layer is to improve barrier layer 309b and metal gate material layer 309c
Between interfacial characteristics, to put it more simply, diagram in omitted.In the present embodiment, photoresist layer is removed using cineration technics
307, the first workfunction setting metal layer 309a and barrier layer are formed using atom layer deposition process or physical gas-phase deposition
309b forms metal gate material layer 309c using chemical vapor deposition method or physical gas-phase deposition.Then, execution
Mechanical lapping is learned to grind above layers material, until being terminated when exposing interlayer dielectric layer 305.
Then, as shown in Figure 3D, another photoresist layer 310 in only covering PMOS areas is formed by the techniques such as expose, develop,
And with another photoresist layer 310 be mask, part removal is positioned at the sacrificial gate material layer 302d of NMOS area.In the present embodiment
In, the part is implemented using dry method etch technology and is removed, technological parameter includes：Etching gas is HBr and O2, the stream of HBr
It measures as 50-100sccm, O2Flow for 0-10sccm, pressure 2-20mTorr, source power（TCP）For 100-1000W, biasing
Power is 20-200W, and wherein mTorr represents milli millimetres of mercury, and sccm represents cc/min.Implement the part removal
Later, the thickness of remaining sacrificial gate material layer 302d is 30-100 angstroms.
Then, as shown in FIGURE 3 E, it is mask with another photoresist layer 310, removal is positioned at the sacrificial gate material of NMOS area
The remainder of layer 302d, forms another groove 311.In the present embodiment, using the first remote plasma etch technique reality
The part removal is applied, technological parameter includes：Etching gas H2Flow for 100-2000sccm, temperature is 20-60 DEG C, pressure
Power is 0.5-2.0Torr, and power 500-5000W, wherein Torr represent millimetres of mercury, and sccm represents cc/min.
Then, the residuals on coating 302c surfaces are removed using the second remote plasma etch technique, including
Coating 302c and sacrificial gate material layer 302d react the conjugate to be formed.In the present embodiment, second distal end wait from
The technological parameter of daughter etching includes：Etching gas is NF3And H2, NF3Flow be 5-50sccm, H2Flow be 100-
2000sccm, temperature are 20-60 DEG C, and pressure 0.5-2.0Torr, wherein power 500-5000W, Torr represent millimeter mercury
Column, sccm represent cc/min.
Then, as illustrated in Figure 3 F, another photoresist layer 310 is removed, and the second metal gates are formed in another groove 311
312.As an example, the second metal gates 312 include the second workfunction setting metal layer 312a stacked gradually from bottom to top, another
One barrier layer 312b and another metal gate material layer 312c.Second workfunction setting metal layer 312a includes one or more layers gold
Belong to or metallic compound, constituent material are the metal material suitable for NMOS, including titanium, tantalum, aluminium, zirconium, hafnium and its alloy, go back
Carbide, nitride including above-mentioned metallic element etc.；The material of another barrier layer 312b includes tantalum nitride or titanium nitride, another
The material of metal gate material layer 312c includes tungsten or aluminium.It should be noted that in another barrier layer 312b and another metal gate
Soakage layer can also be formed between the material layer 312c of pole, constituent material includes titanium or titanium-aluminium alloy, forms the effect of soakage layer
It is the interfacial characteristics improved between another barrier layer 312b and another metal gate material layer 312c, to put it more simply, being given in diagram
To omit.In the present embodiment, another photoresist layer 310 is removed using cineration technics, using atom layer deposition process or physics
Gas-phase deposition forms the second workfunction setting metal layer 312a and another barrier layer 312b, using chemical vapor deposition method
Or physical gas-phase deposition forms another metal gate material layer 312c.Then, it is above-mentioned to grind to perform chemical mechanical grinding
Layers of material, until being terminated when exposing interlayer dielectric layer 305.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, next, it is possible to implement
Remaining semiconductor devices front end fabrication process, including：Covering 309 He of the first metal gates is formed on interlayer dielectric layer 305
Another interlayer dielectric layer of second metal gates 312, forms first contact hole at the top for connecting the metal gates and connects
Second contact hole of the self-aligned silicide fills metal（Usually tungsten）Connection is formed in the contact hole to be subsequently formed
Interconnecting metal layer and the self-aligned silicide and the metal gates contact plug.
Next, it is possible to implement conventional semiconductor devices back end fabrication, including：The shape of multiple interconnecting metal layers
It is completed into, generally use dual damascene process；The formation of metal pad, for implementing wire bonding during device encapsulation.
With reference to Fig. 4, the flow that method according to an exemplary embodiment of the present invention forms high k- metal gates is shown
Figure, for schematically illustrating the flow of entire manufacturing process.
In step 401, Semiconductor substrate is provided, formed on the NMOS area of Semiconductor substrate and PMOS areas by from lower and
The laminated construction that the boundary layer of upper stacking, high k dielectric layer, coating and sacrificial gate material layer are formed；
In step 402, removal is located at the sacrificial gate material floor in PMOS areas to form groove；
In step 403, the first metal gates are formed in a groove；
In step 404, part removal is positioned at the sacrificial gate material layer of NMOS area；
In step 405, using the removal of the first remote plasma etch technique positioned at the sacrificial gate material of NMOS area
The remainder of layer, forms another groove；
In a step 406, the residue of cover surface exposed using the removal of the second remote plasma etch technique
Matter；
In step 407, the second metal gates are formed in another groove.
According to the present invention it is possible to it is independently adjusted the first workfunction setting metal for being respectively formed in PMOS areas and NMOS area
The work function of layer 309a and the second workfunction setting metal layer 312a, removes by using the remote plasma etch technique
Sacrificial gate material layer 302d avoids damage of the etching to coating 302c and high k dielectric layer 302b, reduces interlayer dielectric
The loss of layer 305.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of manufacturing method of semiconductor devices, including：
Step a)：Semiconductor substrate is provided, is formed on the NMOS area of the Semiconductor substrate and PMOS areas by floor from bottom to top
The laminated construction that folded boundary layer, high k dielectric layer, coating and sacrificial gate material layer is formed；
Step b)：Removal is located at the sacrificial gate material floor in the PMOS areas to form groove；
Step c)：The first metal gates are formed in the groove；
Step d)：Part removal is positioned at the sacrificial gate material layer of the NMOS area；
Step e)：Using the removal of the first remote plasma etch technique positioned at the surplus of the sacrificial gate material layer of the NMOS area
Remaining part point forms another groove, and the etching avoids generating the coating and high k dielectric layer damage, first distal end
The etching gas of plasma etching includes H2；
Step f)：The residuals of the cover surface exposed using the removal of the second remote plasma etch technique, institute
The etching gas for stating the second remote plasma etch includes NF3And H2；
Step g)：The second metal gates are formed in another groove.
2. according to the method described in claim 1, it is characterized in that, the step b) includes：Formation only covers the NMOS area
Photoresist layer；Using the photoresist layer as mask, the removal is implemented using dry method etch technology；It is removed using cineration technics
The photoresist layer.
3. according to the method described in claim 2, it is characterized in that, the technological parameter of the dry etching includes：Etching gas
The flow of HBr is 20-500sccm, pressure 2-40mTorr, power 100-2000W.
4. according to the method described in claim 1, it is characterized in that, the step d) includes：Formation only covers the PMOS areas
Another photoresist layer；Using another photoresist layer as mask, the part is implemented using another dry method etch technology and is removed.
5. according to the method described in claim 4, it is characterized in that, the technological parameter of another dry etching includes：Etching
Gas is HBr and O2, the flow of HBr is 50-100sccm, O2Flow for 0-10sccm, pressure 2-20mTorr, source power
For 100-1000W, bias power 20-200W.
6. according to the method described in claim 4, it is characterized in that, after implementing part removal, the remaining sacrifice
The thickness of gate material layers is 30-100 angstroms.
7. the according to the method described in claim 1, it is characterized in that, technological parameter packet of first remote plasma etch
It includes：Etching gas H2Flow for 100-2000sccm, temperature is 20-60 DEG C, pressure 0.5-2.0Torr, power 500-
5000W。
8. the according to the method described in claim 1, it is characterized in that, technological parameter packet of second remote plasma etch
It includes：Etching gas is NF3And H2, NF3Flow be 5-50sccm, H2Flow for 100-2000sccm, temperature is 20-60 DEG C,
Pressure is 0.5-2.0Torr, power 500-5000W.
9. according to the method described in claim 4, it is characterized in that, after the step f) and before the step g), go back
The step of including removing another photoresist layer using cineration technics.
10. according to the method described in claim 1, it is characterized in that, before the step b), following step is further included：
The both sides of the laminated construction form side wall construction；Source/drain region is formed in the Semiconductor substrate of the side wall construction both sides；
Embedded germanium silicon layer is formed in the PMOS areas of the side wall construction both sides；At the top of the embedded germanium silicon layer and described
Self-aligned silicide is formed on source/drain region；The contact hole that the laminated construction is completely covered is formed on the semiconductor substrate
Etching stopping layer and interlayer dielectric layer；Chemical mechanical grinding is performed to expose the top of the laminated construction.
11. according to the method described in claim 10, it is characterized in that, in the first metal gates and institute described in sedimentary composition respectively
After the material for stating the second metal gates, the step of performing chemical mechanical grinding is further included, until exposing the interlayer dielectric layer
When terminate.
12. according to the method described in claim 1, it is characterized in that, first metal gates include from bottom to top layer successively
Folded the first workfunction setting metal layer, barrier layer and metal gate material layer；Second metal gates are included from bottom to top
The second workfunction setting metal layer, another barrier layer and another metal gate material layer stacked gradually.
13. according to the method for claim 12, which is characterized in that first workfunction setting metal layer include one layer or
Multiple layer metal or metallic compound, constituent material are the metal material suitable for the PMOS；The second work function setting
Metal layer includes one or more layers metal or metallic compound, and constituent material is the metal material suitable for the NMOS.
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| CN106298666A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
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| CN103137559A (en) * | 2011-12-02 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Removing method of pseudo polycrystalline silicon and manufacturing method of complementary metal oxide semiconductor (CMOS) metal grid |
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| DE102009010846B4 (en) * | 2009-02-27 | 2013-08-29 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | A method of fabricating a high-ε gate electrode structure to increase its integrity by including a metal capping layer after deposition |
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| CN103137559A (en) * | 2011-12-02 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Removing method of pseudo polycrystalline silicon and manufacturing method of complementary metal oxide semiconductor (CMOS) metal grid |
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