CN106298666A - The forming method of semiconductor device - Google Patents
The forming method of semiconductor device Download PDFInfo
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- CN106298666A CN106298666A CN201510271614.8A CN201510271614A CN106298666A CN 106298666 A CN106298666 A CN 106298666A CN 201510271614 A CN201510271614 A CN 201510271614A CN 106298666 A CN106298666 A CN 106298666A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor device, including: the Semiconductor substrate of second area including first area and isolating therewith is provided, formation is positioned at the interlayer dielectric layer of semiconductor substrate surface, runs through inter-level dielectric layer thickness, and lay respectively at the first semiconductor structure and second semiconductor structure in first and second region, wherein, the second semicon-ductor structure surface is the metal level being easily corroded；Formed and cover interlayer dielectric layer and the first photoresist layer of the second semiconductor structure, and described first photoresist layer exposes the first semiconductor structure；Remove the first semiconductor structure with the first photoresist layer for mask, form the first opening；Remote plasma etching technics is used to remove the first photoresist layer；Dry ice or compact fluid is used to clean the second semicon-ductor structure surface；Forming the 3rd semiconductor structure being positioned at described first opening, the 3rd semicon-ductor structure surface flushes with interlayer dielectric layer surface.The superior performance of semiconductor device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of semiconductor device.
Background technology
Metal-oxide semiconductor (MOS) (MOS) transistor is one of most important active device in integrated circuit,
Wherein, the CMOS structure being complementarily shaped to nmos pass transistor and PMOS transistor is deep-submicron super large
The component units of integrated circuit.
The process forming CMOS transistor in prior art includes: first, at NMOS area and PMOS
The semiconductor substrate surface in region forms dummy gate structure, dummy gate electrode structure by interlayer dielectric layer every
From；Form the first photoresist layer of the dummy gate structure covering interlayer dielectric layer and NMOS area, with described
First photoresist layer is mask etching, removes the dummy gate structure of PMOS area, forms the first groove；Shape
Become to be positioned at the grid structure of described groove；After forming grid structure in staying in described first groove, remove
First photoresist layer；Form the second photoresist of the grid structure covering interlayer dielectric layer and PMOS area
Layer, with described second photoresist layer as mask etching, removes the dummy gate structure of PMOS area, forms the
Two grooves；Form the grid structure being positioned at described second groove；Grid are formed in staying in described second groove
After electrode structure, remove the second photoresist layer.
But, prior art use the performance of the CMOS transistor of above-mentioned steps formation have much room for improvement.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor device, described semiconductor device
Performance more superior.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor device, including: provide
Semiconductor substrate, described Semiconductor substrate includes first area and the second area isolated therewith, forms position
In described semiconductor substrate surface interlayer dielectric layer, run through the first the half of described inter-level dielectric layer thickness and lead
Body structure and the second semiconductor structure, wherein, described first semiconductor structure is positioned at first area, described
Second semiconductor structure is positioned at second area, and described second semicon-ductor structure surface is metal level；Formed
Cover interlayer dielectric layer and the photoresist layer of the second semiconductor structure, and described photoresist layer exposes first
Semiconductor structure；Remove the first semiconductor structure with described photoresist layer for mask, form the first opening；
Remote plasma etching technics is used to remove the first photoresist layer；Dry ice or compact fluid is used to clean the
Two semicon-ductor structure surface；Formed and be positioned at the 3rd semiconductor structure of described first opening, the described 3rd
Semicon-ductor structure surface flushes with interlayer dielectric layer surface.
Alternatively, the etching gas that described remote plasma etching technics uses is the mixed of nitrogen and hydrogen
Compound.
Alternatively, in described etching gas, hydrogen content accounts for the percent by volume of total gas content more than 40%.
Alternatively, the temperature of described remote plasma etching technics is more than 300 DEG C.
Alternatively, the step of described employing Dry ice cleaning the second semicon-ductor structure surface includes: turned by dry ice
Becoming the carbon dioxide that flow is 1 kg/min-2 kg/min, being aligned with rotary speed is 5
Second semicon-ductor structure surface of revs/min-20 revs/min.
Alternatively, the step that described employing compact fluid cleans the second semicon-ductor structure surface includes: by 20
The ammonia of normal atmosphere-25 normal atmosphere is passed into the second semiconductor structure that temperature is 20 DEG C-25 DEG C
Surface.
Alternatively, before forming the 3rd semiconductor structure, dry ice or compact fluid is used to clean the second quasiconductor
After body structure surface, also include: form the passivation layer being positioned at described second semicon-ductor structure surface.
Alternatively, the material of described passivation layer is AlN.
Alternatively, described first semiconductor structure is the first dummy gate structure, described second semiconductor structure
For second grid structure, the 3rd semiconductor structure is first grid structure.
Alternatively, described first grid structure includes the first work-function layer and covers described first work-function layer
First gate electrode layer；Described second grid structure includes the second work-function layer and covers described second work content
The second gate electrode layer of several layers.
Alternatively, the forming step of described second grid structure includes: is formed and is positioned at described Semiconductor substrate
The interlayer dielectric layer on surface, the first dummy gate structure running through described inter-level dielectric layer thickness and the second pseudo-grid
Electrode structure；Formed and cover described interlayer dielectric layer and the second photoresist layer of the first dummy gate structure, and institute
State the second photoresist layer and expose the second dummy gate structure；Institute is removed for mask with described second photoresist layer
State the second dummy gate structure, form the second opening；Form the second grid knot being positioned at described second opening
Structure, described second grid body structure surface flushes with interlayer dielectric layer surface.
Alternatively, also include: formed and be positioned at the first grid dielectric layer of described first open bottom, described the
One grid structure covers described first grid dielectric layer surface；Formed and be positioned at the second of described second open bottom
Gate dielectric layer, described second grid structure covers described second gate dielectric layer surface.
Alternatively, described first grid dielectric layer is formed before described first dummy gate structure or is removing first
Formed after dummy gate structure.
Alternatively, described second gate dielectric layer is formed before described second dummy gate structure or is removing second
Formed after dummy gate structure.
Compared with prior art, technical scheme has the advantage that
Owing to the second semicon-ductor structure surface of second area is metal level, this metal level is easily corroded, because of
This is after the first semiconductor structure removing first area, before forming the 3rd semiconductor structure, uses remotely
Plasma etch process removes the first photoresist layer；And use dry ice or compact fluid to clean the second half to lead
Body body structure surface.Both can effectively remove above-mentioned first photoresist layer, effectively prevent again the second quasiconductor
The metal level of body structure surface is corroded removing during the first photoresist layer, thus ensure that the second half
The quality of conductor structure, is effectively increased the performance of semiconductor device.
Further, before forming the 3rd semiconductor structure, dry ice or compact fluid is used to clean the second quasiconductor
After body structure surface, also include: form the passivation layer being positioned at described second semicon-ductor structure surface.Described blunt
During change layer is so that be subsequently formed the 3rd semiconductor structure, the second semiconductor structure is passivated layer
It is protected against damage, has ensured the quality of the second semiconductor structure further, improve semiconductor device
Performance.
Further, described first semiconductor structure is the first dummy gate structure, described second semiconductor structure
For second grid structure, the 3rd semiconductor structure is first grid structure.The semiconductor device formed is
CMOS transistor, its superior performance.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the cross-sectional view of the forming process of the semiconductor device of the embodiment of the present invention.
Detailed description of the invention
As described in background, the performance of the CMOS transistor that prior art is formed has much room for improvement.
Find after research, during forming CMOS transistor, high-K dielectric layer, work function
Layer etc. sustains damage, and the metal gate in grid structure, all can be to CMOS transistor by reasons such as corrosion
Performance impact.
Further, inventor provide the forming method of a kind of CMOS transistor, be prevented effectively from or subtract
Light high-K dielectric layer and metal gate impaired, improves the performance of CMOS transistor.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Refer to Fig. 1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 includes first area I
The second area II isolated therewith, forms the interlayer dielectric layer being positioned at described Semiconductor substrate 100 surface
103, the first semiconductor structure and second semiconductor structure of described interlayer dielectric layer 103 thickness are run through, its
In, described first semiconductor structure is positioned at first area I, and described second semiconductor structure is positioned at second area
II, and described second semicon-ductor structure surface is metal level.
Described Semiconductor substrate 100 is silicon substrate, germanium substrate, silicon nitrate substrate or silicon-on-insulator lining
The end etc..Those skilled in the art can select the type of described Semiconductor substrate 100 as required, because of
This, the type of described Semiconductor substrate 100 should not limit the scope of the invention.
In the present embodiment, described Semiconductor substrate 100 is silicon substrate, and described first area I is NMOS
Transistor area, is used for being formed nmos pass transistor, and described second area II is PMOS transistor region,
For forming PMOS transistor.
It should be noted that in embodiments of the invention, the PMOS crystal of described Semiconductor substrate 100
N-type well region (not shown), the NMOS crystal of described Semiconductor substrate 100 it is also formed with in territory, area under control
P type trap zone (not shown) it is also formed with in territory, area under control.
It should be noted that in other embodiments of the invention, described first area I can also be
PMOS transistor region, described second area II can also be nmos transistor region.Or,
Described first area I can also form other semiconductor structures, such as transistor, electric capacity, conductive plunger
Deng, second area II can also form other semiconductor structures, such as transistor, electric capacity, conductive plunger
Deng.As long as second semicon-ductor structure surface of second area II is the metal level being easily corroded, the most applicable
In the present invention.That is, although embodiments of the invention are show as a example by CMOS transistor
Plasticity explanation, but technical scheme is not limited to protect the gate electrode layer of CMOS transistor.
Described first area I and second area II is isolated by fleet plough groove isolation structure 101.Described shallow
The forming step of groove isolation construction 101 includes: etch described Semiconductor substrate 100, at described quasiconductor
Shallow trench (not shown) is formed in substrate 100；In described shallow trench, fill isolated material, formed and half
The fleet plough groove isolation structure 101 that conductor substrate 100 flushes.In embodiments of the invention, also include: fill
Before isolated material, form laying (not shown) in described shallow trench inner wall surface.So so that shallow
Trench wall better quality, more smooth, during follow-up filling isolated material, filling effect is preferable, is beneficial to improve
The isolation effect of fleet plough groove isolation structure 101.
Described first semiconductor structure for define the size of semiconductor structure of first area I, shape and
Position.The semiconductor structure of described first area I may be used for forming transistor, electric capacity, conductive plunger etc..
In embodiments of the invention, described first semiconductor structure is the first dummy gate structure 105, and described first is pseudo-
Grid structure 105 at least includes the pseudo-gate electrode layer that material is polysilicon.
Described second semiconductor structure is for defining the size of semiconductor structure of second area II, shape
And position.The semiconductor structure of described second area II may be used for formed transistor, electric capacity, conduction insert
Plug etc..In embodiments of the invention, described second semiconductor structure is second grid structure.Described second
The forming step of grid structure includes: form the interlayer dielectric layer being positioned at described Semiconductor substrate 100 surface
103, the first dummy gate structure 105 and the second dummy gate structure of described interlayer dielectric layer 103 thickness is run through
(not shown)；Formed and cover described interlayer dielectric layer 103 and the second photoresist layer of the first dummy gate structure
(not shown), and described second photoresist layer exposes the second dummy gate structure；With described second photoresist
Layer removes described second dummy gate structure for mask, forms the second opening (sign)；Formation is positioned at described
Second grid structure in second opening, described second grid body structure surface and interlayer dielectric layer 103 surface
Flush.
Wherein, described second grid structure includes the second work-function layer 1071 and covers described second work function
The second gate electrode layer 1072 of layer 1071.Described second work-function layer 1071 is subsequently formed for regulation
The work function of PMOS transistor, described second gate electrode layer 1072 is for the grid as PMOS transistor
Pole.In embodiments of the invention, follow-up at the first photoresist layer removing second gate electrode layer 1072 surface
Time, remove the perishable Al of chemical reagent of the first photoresist layer, or subsequent chemical-mechanical polishing forms the
During three quasiconductors, the most perishable Al of lapping liquid, damages second gate electrode layer 1072.The most described
Two gate electrode layer 1072 is the metal level being easily corroded, and its material is Al.
It should be noted that in other embodiments of the present invention, the material of described second gate electrode layer 1072
Can also be other metal materials, such as copper, titanium, for avoiding the metal as second gate electrode layer 1072
Material sustains damage, and is all necessary to be protected it.
It should be noted that in embodiments of the invention, described second dummy gate structure at least includes material
For the pseudo-gate electrode layer of polysilicon, do not repeat them here.
For forming CMOS transistor, also include: formed and be positioned at described first opening (sign) bottom
First grid dielectric layer 104, described first dummy gate structure 105 or first grid structure cover described first
Gate dielectric layer 104 surface；Formed and be positioned at the second gate dielectric layer 106 of described second open bottom, described the
Two grid structures cover described second gate dielectric layer surface.Further, described first grid dielectric layer 104 is in institute
State and formed before the first dummy gate structure 105 or formed after removing the first dummy gate structure 105, described the
Two gate dielectric layers 106 are in the front formation of described second dummy gate structure (not shown) or removing the second pseudo-grid
Formed after electrode structure.
In embodiments of the invention, described first grid dielectric layer 104 is shape before the first dummy gate structure 105
Becoming, described second gate dielectric layer 106 is formed before the second dummy gate structure.Further, the described first grid is situated between
Matter layer 104 and second gate dielectric layer 106 are formed in same processing step, and its material is the most identical.Specifically
, the forming step of described first grid dielectric layer 104 and second gate dielectric layer 106 includes: is formed and covers
The interlayer medium film on described Semiconductor substrate 100 surface；Formation runs through described interlayer medium film thickness
The first groove and the second groove, wherein said first groove is positioned at first area I, and the second groove is positioned at
Two region II；Formed and cover described semiconductor substrate surface, the bottom of described first groove and sidewall, institute
State the bottom of the second groove and sidewall and cover the gate dielectric membrane on interlayer medium film surface；Planarization
Described gate dielectric membrane, until exposing interlayer medium film, forms first grid dielectric layer 104 and second gate
Dielectric layer 106.
It should be noted that for preventing from being formed during the first groove and the second groove to Semiconductor substrate
100 cause damage, also include: before forming interlayer medium film, are formed and cover described Semiconductor substrate 100
The etch stop film on surface, after forming the first groove and the second groove, described interlayer medium film becomes
Interlayer dielectric layer 103, described etch stop film becomes etching barrier layer 102.
It should be noted that in other embodiments of the present invention, described first grid dielectric layer 104 and second
The forming step of gate dielectric layer 106 can also be: forms the grid covering described Semiconductor substrate 100 surface
Dielectric film；Form the mask layer covering described gate dielectric membrane surface, carve for mask with described mask layer
Lose described gate dielectric membrane and form first grid dielectric layer 104 and second gate dielectric layer 106, cambium layer the most again
Between dielectric layer 103, do not repeat them here.
Refer to Fig. 2, formed and cover interlayer dielectric layer 103 and the first photoresist layer of the second semiconductor structure
110, and described first photoresist layer 110 exposes the first semiconductor structure；
Described first photoresist layer 110 is subsequently used for as mask, removes the first semiconductor structure.This
In bright embodiment, described first photoresist layer 110 is for as removing the first dummy gate structure 105
Mask.
Refer to Fig. 3, remove the first semiconductor structure with described first photoresist layer 110 for mask, formed
First opening 111.
The technique removing described first semiconductor structure is dry or wet etch technique.The enforcement of the present invention
In example, dry etch process is used to remove described first dummy gate structure 105 (as shown in Figure 2).Further,
After removing described first dummy gate structure 105, expose first grid dielectric layer 104.The most described first grid is situated between
Matter layer 104 is positioned at bottom the first opening 111.
Refer to Fig. 4, use remote plasma etching technics to remove the first photoresist layer 110 (such as Fig. 3
Shown in).
For avoiding the second semiconductor structure bottom the first photoresist layer 110 removing the first photoresist layer 110
During impaired, use remote plasma etching technics remove the first photoresist layer 110, can will etch
The damage of the second semiconductor structure is preferably minimized by technique.It reason for this is that, uses remote plasma to carve
During etching technique, plasma source forms plasma outside reaction zone, then by air-flow, electric field, magnetic
Plasma is introduced reaction zone by the modes such as field, performs etching technique, it is to avoid formation plasma process
In the damage to the second semiconductor structure of the powerful impulsive force, and when plasma enters reaction zone, its
The most active, can effectively remove the first photoresist layer 110.In embodiments of the invention, described
The mixture that etching gas is nitrogen and hydrogen that remote plasma etching technics uses.Described etching gas
In body, hydrogen content accounts for the percent by volume of total gas content more than 40%.Described remote plasma etches
The temperature of technique is more than 300 DEG C.Damage under above-mentioned process conditions, to the second gate electrode layer 1072 of bottom
Wound is preferably minimized.
Please continue to refer to Fig. 4, dry ice or compact fluid is used to clean the second semicon-ductor structure surface.
As it was noted above, owing to the second semicon-ductor structure surface is the metal level being easily corroded, according to often
The mode of the chemical reagent of rule cleans its surface, easily damages this surface.It has been investigated that, dry ice is low
Pressure can rise rapidly the carbon dioxide of Huawei's gaseous state, and the carbon dioxide of now gaseous state have bigger,
Towards impulsive force from all directions, when the flow of the above-mentioned carbon dioxide with impulsive force reaches certain value,
Effectively the photoresist of bulk of the second semicon-ductor structure surface residual can be smashed, and by it by the
Two semicon-ductor structure surface are peeled off.Meanwhile, the chemical stability of carbon dioxide is relatively strong, is not easy to the second half
Conductor structure reacts, thus can be used to clean the second semicon-ductor structure surface
Further, for making the first photoresist of residual be cleaned, it is also possible to revolve while cleaning
Turn the second semiconductor structure to be cleaned, so that the first photoresist residual being crashed to pieces is more easy to be stripped.This
In one embodiment of invention, dry ice is used to remove second gate electrode layer 1072 and the second work-function layer 1071
The photoresist on surface is remaining.The step of described employing Dry ice cleaning second grid body structure surface includes: will be dry
Ice is transformed into the carbon dioxide that flow is 1 kg/min-2 kg/min, is aligned with rotary speed
It it is the second grid body structure surface of 5 revs/min-20 revs/min.
Find through further inventor, some material being under high pressure in a liquid state, such as ammonia, at room temperature
In gaseous state under normal pressure, these materials are become also producing during gaseous state impulsive force, this punching from liquid
The power of hitting can also play the effect of the photoresist smashing bulk, thus these materials under high pressure are (i.e. fine and close
Fluid, Densified Fluid) can also be used to remove the first photoresist of the second semicon-ductor structure surface
Remaining.In an alternative embodiment of the invention, employing compact fluid cleaning (Densified Fluid Cleaning,
DFC) step on second grid structure (i.e. second gate electrode layer 1072 and the second work-function layer 1071) surface
Suddenly include: the ammonia of 20 normal atmosphere-25 normal atmospheres is passed into that temperature is 20 DEG C-25 DEG C second
Grid structure surface.This kind of method is cleaned second grid body structure surface and is led except can effectively remove the second half
First photoresist of body body structure surface is remaining, does not the most damage outside the second semicon-ductor structure surface, also have with
Lower advantage: low cost, safety height and the threat to environmental and human health impacts are less.
It should be noted that in other embodiments of the invention, it is also possible to use other kinds of densification
Fluid cleans second grid body structure surface, as long as can reach to remove photoresist residual the most do not damage second grid
The purpose of structure.
Refer to Fig. 5, form the passivation layer 113 being positioned at described second semicon-ductor structure surface.
Although above-mentioned steps has removed photoresist layer and the residue thereof of the second semicon-ductor structure surface, but examines
Consider and in the first opening 111, also to form the 3rd semiconductor structure to follow-up, unavoidably can be at the second quasiconductor
Body structure surface forms other layers and maybe needs to perform etching technique.For avoiding the second semiconductor structure at subsequent technique
In step injury-free, therefore, formed before the 3rd semiconductor structure, also including that formation is positioned at described
The step of the passivation layer 113 of the second semicon-ductor structure surface.In embodiments of the invention, described passivation layer
The material of 113 is AlN.The formation process of described passivation layer 113 is plasma nitridation process, will wait from
The nitrogen of daughter state is passed into second grid body structure surface so that it is with second gate electrode layer 1072 surface
Al reacts, and generates AlN.
It should be noted that in other embodiments of the present invention, it is also possible to it is formed without passivation layer 113 and straight
Connect formation the 3rd semiconductor structure, do not repeat them here.
Refer to Fig. 6, form the 3rd semiconductor structure being positioned at described first opening, the described 3rd half leads
Body body structure surface flushes with interlayer dielectric layer 103 surface.
Described 3rd semiconductor structure is used for forming transistor, electric capacity, conductive plunger etc..The reality of the present invention
Executing in example, described 3rd semiconductor structure is first grid structure, and described first grid structure includes first
Work-function layer 1051 and first gate electrode layer 1052.The forming step of described first grid structure includes: shape
Become to cover bottom and the sidewall of described first opening 111, and cover described interlayer dielectric layer 103 surface
First work function thin film；Form the first gate electrode thin film covering described first work function film surface；Flat
Smoothization (such as chemically mechanical polishing) described first gate electrode thin film and the first work function thin film are until exposing
Go out interlayer dielectric layer 103 surface, form the first work-function layer 1051 and first gate electrode layer 1052.
During planarization forms the first work-function layer 1051 and first gate electrode layer 1052, due to
Having the protection of passivation layer 113, the second work-function layer 1071 and second gate electrode layer 1072 will not be above-mentioned
Flatening process damages, thus can ensure that above-mentioned two-layer is not damaged, and its quality is ensured.Finally
The semiconductor device formed, the superior performance of such as CMOS transistor.
After above-mentioned steps completes, completing of the semiconductor device of the embodiment of the present invention.Due to the secondth district
Second semicon-ductor structure surface in territory is the metal level being easily corroded, and is therefore removing the first of first area
After semiconductor structure, formed before the 3rd semiconductor structure, use remote plasma etching technics to remove the
One photoresist layer；And use dry ice or compact fluid to clean the second semicon-ductor structure surface.Both can be effective
Removing above-mentioned first photoresist layer, the metal level that effectively prevent again the second semicon-ductor structure surface is being removed
It is corroded during photoresist layer, thus ensure that the quality of the second semiconductor structure, be effectively increased
The performance of semiconductor device.
Further, before forming the 3rd semiconductor structure, dry ice or compact fluid is used to clean the second quasiconductor
After body structure surface, also include: form the passivation layer being positioned at described second semicon-ductor structure surface.Described blunt
During change layer is so that be subsequently formed the 3rd semiconductor structure, the second semiconductor structure is passivated layer
It is protected against damage, has ensured the quality of the second semiconductor structure further, improve semiconductor device
Performance.
Further, described first semiconductor structure is the first dummy gate structure, described second semiconductor structure
For second grid structure, the 3rd semiconductor structure is first grid structure.The semiconductor device formed is
CMOS transistor, its superior performance.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (14)
1. the forming method of a semiconductor device, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate includes first area and the second area isolated therewith,
Formed and be positioned at the interlayer dielectric layer of described semiconductor substrate surface, run through the of described inter-level dielectric layer thickness
Semiconductor structure and the second semiconductor structure, wherein, described first semiconductor structure is positioned at first area,
Described second semiconductor structure is positioned at second area, and the metal level that described second semicon-ductor structure surface is；
Formed and cover interlayer dielectric layer and the first photoresist layer of the second semiconductor structure, and described first light
Photoresist layer exposes the first semiconductor structure；
Remove the first semiconductor structure with described first photoresist layer for mask, form the first opening；
Remote plasma etching technics is used to remove the first photoresist layer；
Dry ice or compact fluid is used to clean the second semicon-ductor structure surface；
Form the 3rd semiconductor structure being positioned at described first opening, described 3rd semicon-ductor structure surface
Flush with interlayer dielectric layer surface.
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described long-range grade from
The mixture that etching gas is nitrogen and hydrogen that daughter etching technics uses.
3. the forming method of semiconductor device as claimed in claim 2, it is characterised in that described etching gas
Middle hydrogen content accounts for the percent by volume of total gas content more than 40%.
4. the forming method of semiconductor device as claimed in claim 2, it is characterised in that described long-range grade from
The temperature of daughter etching technics is more than 300 DEG C.
5. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described employing dry ice
The step cleaning the second semicon-ductor structure surface includes: it is 1 kg/min-2 that dry ice is transformed into flow
The carbon dioxide of kg/min, be aligned with that rotary speed is 5 revs/min-20 revs/min
Two semicon-ductor structure surface.
6. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described employing is fine and close
Fluid cleans the step of the second semicon-ductor structure surface and includes: by 20 normal atmosphere-25 standard atmospheres
The ammonia of pressure is passed into the second semicon-ductor structure surface that temperature is 20 DEG C-25 DEG C.
7. the forming method of semiconductor device as claimed in claim 1, it is characterised in that form the 3rd half and lead
Before body structure, after using dry ice or compact fluid to clean the second semicon-ductor structure surface, also include: shape
Become to be positioned at the passivation layer of described second semicon-ductor structure surface.
8. the forming method of semiconductor device as claimed in claim 7, it is characterised in that described passivation layer
Material is AlN.
9. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described the first half lead
Body structure is the first dummy gate structure, and described second semiconductor structure is second grid structure, the 3rd half
Conductor structure is first grid structure.
10. the forming method of semiconductor device as claimed in claim 9, it is characterised in that described first grid
Structure includes the first work-function layer and covers the first gate electrode layer of described first work-function layer；Described
Two grid structures include the second work-function layer and cover the second gate electrode layer of described second work-function layer.
The forming method of 11. semiconductor device as claimed in claim 9, it is characterised in that described second grid
The forming step of structure includes: formation is positioned at the interlayer dielectric layer of described semiconductor substrate surface, runs through
First dummy gate structure of described inter-level dielectric layer thickness and the second dummy gate structure；Formed described in covering
Interlayer dielectric layer and the second photoresist layer of the first dummy gate structure, and described second photoresist layer exposure
Go out the second dummy gate structure；Described second dummy gate structure is removed for mask with described second photoresist layer,
Form the second opening；Form the second grid structure being positioned at described second opening, described second grid
Body structure surface flushes with interlayer dielectric layer surface.
The forming method of 12. semiconductor device as claimed in claim 11, it is characterised in that also include: formed
Being positioned at the first grid dielectric layer of described first open bottom, described first grid structure covers described first
Gate dielectric layer surface；Form the second gate dielectric layer being positioned at described second open bottom, described second gate
Electrode structure covers described second gate dielectric layer surface.
The forming method of 13. semiconductor device as claimed in claim 11, it is characterised in that the described first grid is situated between
Matter layer is formed before described first dummy gate structure or is formed after removing the first dummy gate structure.
The forming method of 14. semiconductor device as claimed in claim 11, it is characterised in that described second gate is situated between
Matter layer is formed before described second dummy gate structure or is formed after removing the second dummy gate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| US20020045347A1 (en) * | 2000-10-13 | 2002-04-18 | Worm Steven L. | Divided pressure vessel apparatus for carbon dioxide based systems and methods of using same |
| US20070202446A1 (en) * | 2006-02-28 | 2007-08-30 | Fujitsu Limited | Semiconductor device fabrication method having step of removing photo-resist film or the like, and photo-resist film removal device |
| US20140327117A1 (en) * | 2013-05-03 | 2014-11-06 | Applied Materials, Inc. | Optically tuned hardmask for multi-patterning applications |
| CN104517900A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020045347A1 (en) * | 2000-10-13 | 2002-04-18 | Worm Steven L. | Divided pressure vessel apparatus for carbon dioxide based systems and methods of using same |
| US20070202446A1 (en) * | 2006-02-28 | 2007-08-30 | Fujitsu Limited | Semiconductor device fabrication method having step of removing photo-resist film or the like, and photo-resist film removal device |
| US20140327117A1 (en) * | 2013-05-03 | 2014-11-06 | Applied Materials, Inc. | Optically tuned hardmask for multi-patterning applications |
| CN104517900A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
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