CN103578988A - Fin part and finned-type field-effect transistor and forming method thereof - Google Patents
Fin part and finned-type field-effect transistor and forming method thereof Download PDFInfo
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- CN103578988A CN103578988A CN201210254002.4A CN201210254002A CN103578988A CN 103578988 A CN103578988 A CN 103578988A CN 201210254002 A CN201210254002 A CN 201210254002A CN 103578988 A CN103578988 A CN 103578988A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 230000005669 field effect Effects 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 238000009413 insulation Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 36
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 238000001312 dry etching Methods 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 14
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 239000003595 mist Substances 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- 230000005012 migration Effects 0.000 description 6
- 238000013508 migration Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000001427 coherent effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin part and a finned-type field-effect transistor and a forming method of the fin part and the finned-type field-effect transistor. The forming method of the fin part includes the steps that a substrate is provided; mask layers provided with multiple first openings are formed on the surface of the substrate, and the first openings are exposed out of the substrate; the substrate is etched with the mask layers provided with the first openings as a mask, so that multiple grooves are formed; insulation layers are filled into the grooves; the mask layers are etched back along the first openings, the width of the first openings is increased, and multiple second openings are formed in the mask layers; insulation layers are etched along the second openings with the mask layers as a mask so that the insulation layers can remain with a preset certain thickness, and the substrate among the remaining insulation layers with the preset thickness serves as first auxiliary fin parts; the substrate above the first auxiliary fin parts is etched to form second auxiliary fin parts located on the first auxiliary fin parts and third auxiliary fin parts located on the second auxiliary fin parts. According to the fin part and the finned-type field-effect transistor and the forming method of the fin part and the finned-type field-effect transistor, stability of the finned-type field-effect transistor is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of fin, fin field effect pipe and fin and fin field effect pipe.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is towards higher component density, and the future development of higher integrated level.Therefore transistor is just being widely used at present as the most basic semiconductor device, and along with the raising of component density and the integrated level of semiconductor device, transistorized grid size is also shorter and shorter.Yet transistorized grid size shortens and can make transistor produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.
In order to overcome transistorized short-channel effect, suppress leakage current, prior art has proposed fin field effect pipe (Fin FET), please refer to Fig. 1 and Fig. 2, Fig. 1 is the cross-sectional view of the fin field effect pipe of prior art, Fig. 2 is the cross-sectional view of Fig. 1 in AA' direction, comprising:
It should be noted that, described grid structure 13 comprises: across the top of described fin 11 and the gate dielectric layer of sidewall 14 and the gate electrode layer 15 that is positioned at described gate dielectric layer 14 surfaces; The top of described fin 11 and sidewall become channel region with the part that grid structure 13 contacts.
In the fin field effect pipe that prior art forms, fin 11 is vertical with substrate 10 surfaces, and it is to the unstressed effect in channel region, and in channel region, the speed of electric charge diffusion is slower, the poor-performing of fin field effect pipe.And the uniformity of the pattern of the sidewall of the fin 11 of existing formation is poor, the lack of homogeneity opposite sex of the pattern of the sidewall of fin 11 can make the threshold voltage of fin field effect pipe be offset, and affects the stability of fin field effect pipe.
More fin field effect pipe please refer to the U.S. patent documents that publication number is US2011068405A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fin, fin field effect pipe and fin and fin field effect pipe, avoids the performance of formed each fin field effect pipe there are differences, and improves the electric property of the fin field effect pipe that forms.
For addressing the above problem, the invention provides a kind of formation method of fin, comprising: substrate is provided; At described substrate surface, form the mask layer that comprises some the first openings, described the first opening exposes substrate; The mask layer that comprises some the first openings of take is mask, and substrate described in etching, forms some grooves; In described groove, fill separator; Along the first opening, mask layer is returned to quarter, increase the width of the first opening, in described mask layer, form some the second openings; Take mask layer as mask, along separator described in the second opening etching, make separator residue predetermined thickness, the substrate between the separator of described residue predetermined thickness is the first sub-fin; The substrate of the sub-fin of etching first top, formation is positioned at the second sub-fin on the first sub-fin and is positioned at the 3rd sub-fin on the second sub-fin, the angle on described the second sub-fin sidewall and the first sub-fin surface is the first angle, the angle on described the 3rd sub-fin sidewall and the second sub-fin surface is the second angle, and described the first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
Optionally, described the first angle is 70～80 degree, and described the second angle is 82 degree.
Optionally, the method for the substrate of the sub-fin of etching first top is dry etching, and the etching gas of described dry etching is Cl
2, O
2with the mist of HBr, wherein, Cl
2flow be 50～150sccm, O
2flow be 5～20sccm, the flow of HBr is 80～180sccm, Cl
2with O
2flow-rate ratio be 7:1～10:1, the power of described dry etching is 800～2500W, bias generator power is 200～700W, etch period is 10～25s.
Accordingly, the present invention also provides a kind of formation method of fin field effect pipe, comprising: the fin that provides above-mentioned any method to form; Formation is across sidewall and the 3rd top of sub-fin and the grid structure of sidewall of described the second sub-fin; In the second sub-fin of described grid structure both sides and the 3rd sub-fin, form heavily doped region.
The present invention also provides a kind of fin, comprising: substrate; Be positioned at some grooves of described substrate; Be positioned at the separator that groove has predetermined thickness, described insulation surface is lower than substrate surface; The first sub-fin between separator; Be positioned on the first sub-fin and the angle on its sidewall and the first sub-fin surface is the second sub-fin of the first angle; Be positioned on the second sub-fin and the angle on its sidewall and the second sub-fin surface is the 3rd sub-fin of the second angle; Wherein, described the first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
Optionally, described the first angle is 70～80 degree, and described the second angle is 82 degree.
Optionally, the height of the height of described fin and the second sub-fin and the 3rd sub-fin and ratio be 4:1～3:2.
Accordingly, the present invention also provides a kind of fin field effect pipe, comprising: above-mentioned any fin; Sidewall and the 3rd top of sub-fin and the grid structure of sidewall across described the second sub-fin; Be positioned at the second sub-fin of described grid structure both sides and the heavily doped region of the 3rd sub-fin.
Compared with prior art, technical solution of the present invention has the following advantages:
First substrate is carried out to etching and form groove, and in groove, form the separator of predetermined thickness, described insulation surface is lower than substrate surface, and the substrate between separator is the first sub-fin; Then to being positioned at the substrate of the first sub-fin top, carry out etching, form the second sub-fin and the 3rd sub-fin, the angle that described the second sub-fin is positioned at the first sub-fin top and its sidewall and the first sub-fin upper surface is the first angle, the angle that described the 3rd sub-fin is positioned at the second sub-fin top and its sidewall and the second sub-fin upper surface is the second angle, because the A/F between the 3rd sub-fin opposing sidewalls is greater than the second sub-fin, be beneficial to the formation of subsequent gate structure; And, because the first sub-fin, the second sub-fin and the 3rd sub-fin are all by substrate etching is formed after substrate forms, the first sub-fin and the second sub-fin angle coherent and the second sub-fin sidewall and the first sub-fin upper surface is less than the angle of the first sub-fin and substrate top surface, after follow-up formation is across the second sub-fin sidewall and the 3rd top of sub-fin and the grid structure of sidewall, can effectively increase the stress putting on the channel region of grid structure below, improve the migration rate of electric charge in channel region.
Further, by adding the hydrofluoric acid solution of ozone to carry out wet etching to the top of the sidewall of described the second sub-fin and the 3rd sub-fin and sidewall, make the sidewall of the second sub-fin and the top of the 3rd sub-fin and the silicon atom on sidewall and the ozone formation oxide layer that reacts, by hydrofluoric acid solution, remove formed oxide layer again, make the pattern on the second sub-fin and the 3rd sub-fin surface even, the threshold voltage of the fin field effect pipe that prevents from comprising formed fin is offset, and has improved the stability of fin field effect pipe.
After above-mentioned fin forms, formation is across the second sub-fin sidewall, the 3rd top of sub-fin and the grid structure of sidewall, and form heavily doped region in the second sub-fin of grid structure both sides and the 3rd sub-fin, effectively improve the migration rate of the electric charge in fin field effect pipe channel region that forms, improved the electric property of fin field effect pipe.
Accompanying drawing explanation
Fig. 1～Fig. 2 is the schematic diagram that existing technique forms fin field effect pipe;
Fig. 3 is the schematic flow sheet of an execution mode of formation method of fin of the present invention;
Fig. 4～Figure 12 is the schematic diagram that embodiment of formation method of fin of the present invention forms each stage fin;
Figure 13～Figure 15 is the schematic diagram that embodiment of formation method of fin field effect pipe of the present invention forms each stage fin field effect pipe.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Just as described in the background section, the fin that prior art forms fin field effect pipe is vertical with substrate, the channel region unstressed effect of fin to the fin field effect pipe that comprises fin, in channel region, the speed of electric charge diffusion is slower, the poor-performing of fin field effect pipe.And the uniformity of the sidewall of the fin of existing formation is poor, the sidewall lack of homogeneity opposite sex of fin is offset the threshold voltage of fin field effect pipe, affects the stability of fin field effect pipe.
For addressing the above problem, inventor proposes a kind of formation method of fin, and with reference to figure 3, the schematic flow sheet for the execution mode of formation method of fin of the present invention, comprising:
Step S1, provides substrate;
Step S2, forms the mask layer that comprises some the first openings at described substrate surface, described the first opening exposes substrate;
Step S3, the mask layer that comprises some the first openings of take is mask, substrate described in etching, forms some grooves;
Step S4 fills separator in described groove;
Step S5, returns quarter along the first opening to mask layer, increases the width of the first opening, forms some the second openings in described mask layer;
Step S6, take mask layer as mask, along separator described in the second opening etching, makes separator residue predetermined thickness, and the substrate between the separator of described residue predetermined thickness is the first sub-fin;
Step S7, the substrate of the sub-fin of etching first top, formation is positioned at the second sub-fin on the first sub-fin and is positioned at the 3rd sub-fin on the second sub-fin, the angle on described the second sub-fin sidewall and the first sub-fin surface is the first angle, the angle on described the 3rd sub-fin sidewall and the second sub-fin surface is the second angle, and described the first sub-fin, the second sub-fin and the 3rd sub-fin form fin;
Step S8, removes the mask layer that comprises some the second openings;
Step S9, by adding the hydrofluoric acid solution of ozone to carry out wet etching to the top of the sidewall of the second sub-fin and the 3rd sub-fin and sidewall.
With reference to figure 4～Figure 12, embodiment of the formation method of fin of the present invention forms the schematic diagram of each stage fin, in conjunction with Fig. 4～Figure 12, by specific embodiment, the formation method of fin of the present invention is described further.
With reference to figure 4, provide substrate 201.
In the present embodiment, the material of described substrate 201 is monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi) or carborundum (SiC); Also can be silicon-on-insulator (SOI) or germanium on insulator (GOI); Can also be for other material, such as III-V compounds of group such as GaAs.
Continuation, with reference to figure 4, forms dielectric layer 205a and the mask layer 207a that comprises some the first openings 203 on described substrate 201 surfaces, and described the first opening 203 exposes dielectric layer 205a.
Wherein, the material of described dielectric layer 205a is silica, to protect described substrate 201 in subsequent etching technique; The mask of described mask layer 207a during as subsequent etching dielectric layer 205a and substrate 201, the material of described mask layer 207a is silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide carbide (SiOC), amorphous carbon (a-C) or carbon silicon oxynitride (SiOCN).In the present embodiment, the material of described mask layer 207a is silicon nitride.
The step of the mask layer 207a that formation comprises some the first openings 203 comprises:
The photoresist layer (not shown) that forms successively dielectric layer 205a, mask layer from the bottom to top and comprise the first patterns of openings on described substrate 201 surfaces;
The described photoresist layer that comprises the first patterns of openings of take is mask, and mask layer described in etching forms the mask layer 207a that comprises some the first openings 203, and described the first opening 203 exposes dielectric layer 205a;
The photoresist layer that comprises the first patterns of openings described in removal.
In other embodiments, can also not comprise described dielectric layer 205a, on substrate 201 surfaces, directly form the mask layer 207a that comprises some the first openings 203, it does not limit the scope of the invention.
With reference to figure 5, the mask layer 207a that comprises some the first openings 203 of take is mask, and the 205a of dielectric layer described in etching Fig. 4 and substrate 201 form some grooves 209.
In the present embodiment, the method that forms described groove 209 is dry etching, as plasma etching.Described groove 209 bottoms are 800～3000 dusts apart from the vertical range at groove 209 both sides substrate 201 tops.
With reference to figure 6, at groove described in Fig. 5 209 and the interior filling separator of corresponding the first opening 203 213a.Described separator 213a is used between the fin of follow-up formation and the electric isolation between fin and substrate 201.
The step that forms described separator 213a comprises:
In described groove 209 and the interior filling separator of corresponding the first opening 203 (not shown), described separator is filled full groove 209 and corresponding the first opening 203 and is covered the mask layer 207a of the first opening 203 both sides;
Separator described in planarization, to exposing described mask layer 207a.
The material of described separator can be silica (SiO
2), silicon oxynitride (SiON) or silicon oxide carbide (SiOC), in the present embodiment, the material of described separator is silica.
The formation technique of described separator is chemical vapour deposition (CVD) (CVD, Chemical Vapor Deposition) technique, such as: high density plasma CVD technique (HDPCVD) or partially aumospheric pressure cvd technique (SACVD), but the invention is not restricted to this.
Described in planarization, the method for separator is cmp (CMP, Chemical Mechanical Polishing) technique.
In conjunction with reference to figure 5～Fig. 7, remove the separator 213a in the first opening 203, make the surface of the separator 213b in remaining groove 209 lower than described mask layer 207a surface.
In the present embodiment, by wet etching, remove the separator 213a in the first opening 203, described etching solution can be hydrofluoric acid solution, but the invention is not restricted to this.
It should be noted that, in the present embodiment, the substrate 201 of groove 209 both sides need, higher than the top of described groove 209 both sides substrates 201, follow-up, the mask layer 207a that comprises some the first openings 203 is returned in process at quarter, be protected in the surface of separator 213b.
With reference to figure 8, along 203 couples of mask layer 207a of the first opening in Fig. 7, return quarter, increase the width of the first opening 203, in described mask layer 207b, form some the second openings 208.
In the present embodiment, it is dry etching that the mask layer 207a that comprises some the first openings 203 is returned to the method for carving, and the etching gas of described dry etching is CH
3f and O
2mist, wherein, CH
3the flow of F is 50～200sccm, O
2flow be 10～40sccm, the power of described dry etching is 500～2500W, etch period is 10～40s.
With reference to figure 9, take mask layer 207b as mask, along separator 213b described in the second opening 208 etchings, make separator 213b residue predetermined thickness, the substrate between the separator 215 of described residue predetermined thickness is the first sub-fin 212a.
Wherein, the surface of the separator 215 of described residue predetermined thickness is lower than the surface of described separator 215 both sides substrates 201.
In the present embodiment, the method for etching separator 213b is wet etching, and the etching solution of described wet etching is hydrofluoric acid solution, and etch rate is 20～40 A/min of clocks.The height h of the substrate 201 of described the first sub-fin 212a top
2be 100～1000 dusts (separator 215 surfaces that remain predetermined thickness are 100～1000 dusts with the vertical range at the top of isolation structure 215 both sides substrates 201), the height h of described fin 212a
1height h with the first sub-fin 212a top substrate 201
2ratio be 4:1～3:2.
With reference to Figure 10, the substrate 201 of the sub-fin 212a of etching first top, formation is positioned at the second sub-fin 212b on the first sub-fin 212a and is positioned at the 3rd sub-fin 212c on the second sub-fin 212b, the angle on described the second sub-fin 212b sidewall and the first sub-fin 212a surface
be the first angle, the angle theta on described the 3rd sub-fin 212c sidewall and the second sub-fin 212b surface is the second angle, and described the first sub-fin 212a, the second sub-fin 212b and the 3rd sub-fin 212c form fin 212.
Wherein, the width between adjacent the 3rd sub-fin 212c top is consistent with the A/F of described the second opening 208.
In the present embodiment, the method for the substrate 201 of the sub-fin 212a of etching first top is dry etching.The etching gas of described dry etching is Cl
2, O
2with the mist of HBr, wherein Cl
2flow be 50～150sccm, O
2flow be 5～20sccm, the flow of HBr is 80～180sccm, Cl
2with O
2flow-rate ratio be 7:1～10:1, the power of dry etching is that 800～2500W, bias generator power are 200～700W, etch period is 10～25s.
Due to the location positioning at the bottom of the second sub-fin 212b and the top of the 3rd sub-fin 212c, while the substrate 201 of the first sub-fin 212a top being carried out to etching by above-mentioned dry etching, when the sidewall of the second sub-fin 212b and the angle on isolation structure 215 surfaces
while being the first angle, the angle theta on the sidewall of the 3rd sub-fin 212c and isolation structure 215 surfaces is the second angle.
Due to the first sub-fin 212a, the second sub-fin 212b and the 3rd sub-fin 212c are all by substrate 201 etchings are formed after substrate 201 forms, described the first sub-fin 212a and the second sub-fin 212b angle coherent and the second sub-fin 212b sidewall and isolation structure 215 upper surfaces is less than the first sub-fin 212a, after follow-up formation is across the second sub-fin 212b sidewall and the 3rd top of sub-fin 212c and the grid structure of sidewall, can effectively increase the stress putting on the channel region of grid structure below, improved the migration rate of electric charge in channel region, further improve the response speed of the fin field effect pipe that comprises formed fin 212.
Preferably, making the second angle is 82 degree, and described the first angle is 70～80 degree, and now the indices of crystallographic plane of the 3rd sub-fin 212c sidewall are (551), the maximum of charge migration speed in channel region.
Meanwhile, due to the first angle
be less than the second angle θ, with the first angle
the situation that equals the second angle θ is compared, the width w of the second sub-fin 212b opening
1larger, be beneficial to the formation of subsequent gate structure.
With reference to Figure 11, remove the mask layer 207b that comprises some the second openings 208 in Figure 10.
In the present embodiment, the method for removing the mask layer 207b that comprises some the second openings 208 is wet etching, and the solution of the employing of described wet etching is hot phosphoric acid solution.
In other embodiments, can also adopt the technique of other any appropriate to remove mask layer 207b, the present invention does not limit this.
With reference to Figure 12, by adding the hydrofluoric acid solution of ozone to carry out wet etching to the sidewall of the oxide layer at the 3rd sub-fin 212c top described in Figure 11 and the second sub-fin 212b and the 3rd sub-fin 212c.
In the present embodiment, the flow that passes into ozone in described hydrofluoric acid solution is 500～2000sccm, and the etch rate of described wet etching is 10～20 A/min of clocks.
In the present embodiment, the silicon atom of ozone and the second sub-fin 211b and the 3rd sub-fin 211c sidewall surfaces reacts, form silica, by hydrofluoric acid solution, the silica etching of the sidewall surfaces of the oxide layer at the 3rd sub-fin 212c top and the second sub-fin 212b and the 3rd sub-fin 212c is removed again, make the sidewall surfaces of form the second sub-fin 212b and the 3rd sub-fin 212c smooth evenly, improve the conjugation between the second sub-fin 211b and the 3rd sub-fin 211c sidewall and follow-up formation gate dielectric layer, the threshold voltage of the fin field effect pipe that makes to comprise formed fin is stable, improved the stability of fin field effect pipe.
In other embodiments, while not comprising dielectric layer 205b between mask layer 207b and substrate 201 in Figure 10, after removing described mask layer 207b, by adding the hydrofluoric acid solution of ozone to carry out wet etching to the sidewall of the 3rd sub-fin 212c top and sidewall and the second sub-fin 212b described in Figure 11, the silicon atom of the sidewall surfaces of ozone and the 3rd sub-fin 212c top and sidewall and the second sub-fin 212b reacts, form silica, by hydrofluoric acid solution, the silica of formation is removed again, make the sidewall of the 3rd sub-fin 212c top and sidewall and the second sub-fin 212b smooth evenly.
The fin forming based on above-mentioned steps as shown in figure 12, comprising:
Be positioned at some grooves of described substrate 201;
Be positioned at the separator 215 that groove has predetermined thickness, described separator 215 surfaces are lower than substrate 201 surfaces;
The first sub-fin 212a between separator 215;
Being positioned at the first sub-fin 212a angle upper and its sidewall and the first sub-fin 212a surface is the second sub-fin 212b of the first angle;
Be positioned at the 3rd sub-fin 212c that the second sub-fin 212b angle upper and its sidewall and the second sub-fin 212b surface is the second angle wherein, described the first sub-fin 212a, the second sub-fin 212b and the 3rd sub-fin 212c formation fin.
Preferably, described the first angle
be 70～80 degree, described the second angle θ is 82 degree; The height of described the second sub-fin 212b and the 3rd sub-fin 212c and be 100～1000 dusts (that is, the vertical range h at the first sub-fin 212c of sub-fin 212a surface lies the 3rd top
2be 100～1000 dusts.The height of the height of described fin 212 and the second sub-fin 212b and the 3rd sub-fin 212c and ratio be 4:1～3:2.
In above embodiment, first substrate is carried out to etching and form groove, in groove, form the separator of predetermined thickness, described insulation surface is lower than substrate surface, and between the separator of predetermined thickness substrate as the first sub-fin of fin, then to being positioned at the substrate of the first sub-fin top, carry out etching, form the second sub-fin and the 3rd sub-fin, described the second sub-fin is positioned on the first sub-fin and the angle on its sidewall and the first sub-fin surface is the first angle, described the 3rd sub-fin is positioned on the second sub-fin and the angle on its sidewall and the second sub-fin surface is the second angle, because the A/F between the opposing sidewalls of adjacent the second sub-fin becomes large, be beneficial to the formation of subsequent gate structure, and, because the first sub-fin, the second sub-fin and the 3rd sub-fin are all by substrate etching is formed after substrate forms, described the first sub-fin and the second sub-fin angle coherent and the second sub-fin sidewall and isolation structure upper surface is less than the first sub-fin, after follow-up formation is across the second sub-fin sidewall and the 3rd top of sub-fin and the grid structure of sidewall, can effectively increase the stress putting on the channel region of grid structure below, improve the migration rate of electric charge in channel region.
In addition, by adding the hydrofluoric acid solution of ozone to carry out wet etching to the top of the sidewall of described the second sub-fin and the 3rd sub-fin and sidewall, make the sidewall of the second sub-fin and the top of the 3rd sub-fin and the silicon atom on sidewall and the ozone formation oxide layer that reacts, by hydrofluoric acid solution, remove formed oxide layer again, make the pattern on the second sub-fin and the 3rd sub-fin surface even, the threshold voltage of the fin field effect pipe that prevents from comprising formed fin is offset, and has improved the stability of fin field effect pipe.
In conjunction with Figure 13～Figure 15, by specific embodiment, the formation method of fin field effect pipe of the present invention is described further.
With reference to Figure 13, a kind of fin forming by above-mentioned steps 312 is provided, described fin 312 comprises by substrate 301 being carried out to the first sub-fin 312a of multiple etching formation, be positioned at the second sub-fin 312b on the first fin 312a and be positioned at the 3rd sub-fin 312c on the second fin 312b, on substrate 301 between described the first sub-fin 312a, be formed with the separator 315 of some predetermined thickness, the angle β on the sidewall of described the second sub-fin 312b and separator 315 surfaces is 70～80 degree, the angle δ on the sidewall of described the 3rd sub-fin 312c and separator 315 surfaces is 82 degree.
With reference to Figure 14, form the grid structure across described the second sub-fin 312b sidewall and the 3rd sub-fin 312c top and sidewall, described grid structure comprises gate dielectric layer 314 and grid 316.
Cutaway view Figure 15 with reference to Figure 14 and Figure 14 along BB ' direction forms heavily doped region 318 in the second sub-fin 312b of described grid structure both sides and the 3rd sub-fin 312c.
Because the formation technique of grid structure and heavily doped region is well known to those skilled in the art, at this, do not repeat.
In the present embodiment, comprising the first sub-fin, (described the second sub-fin is positioned on the first sub-fin and the angle on its sidewall and the first sub-fin surface is the first angle for the fin of the second sub-fin and the 3rd sub-fin, described the 3rd sub-fin is positioned on the second sub-fin and the angle on its sidewall and the second sub-fin surface is the second angle) form after, formation is across the second sub-fin sidewall, the 3rd top of sub-fin and the grid structure of sidewall, in the second sub-fin of grid structure both sides and the 3rd sub-fin, form heavily doped region again, form the fin field effect pipe shown in Figure 14 and 15, effectively improved the migration rate of the electric charge in fin field effect pipe channel region that forms, improved the electric property of fin field effect pipe.
In addition, for the hydrofluoric acid solution by adding ozone, the sidewall of the second sub-fin and the 3rd sub-fin top and sidewall are carried out the fin field effect pipe of wet etching, because the pattern on the second sub-fin and the 3rd sub-fin surface is even, the threshold voltage of the fin field effect pipe of avoiding comprising formed fin is offset, and has improved the stability of fin field effect pipe.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. a formation method for fin, is characterized in that, comprising:
Substrate is provided;
At described substrate surface, form the mask layer that comprises some the first openings, described the first opening exposes substrate;
The mask layer that comprises some the first openings of take is mask, and substrate described in etching, forms some grooves;
In described groove, fill separator;
Along the first opening, mask layer is returned to quarter, increase the width of the first opening, in described mask layer, form some the second openings;
Take mask layer as mask, along separator described in the second opening etching, make separator residue predetermined thickness, the substrate between the separator of described residue predetermined thickness is the first sub-fin;
The substrate of the sub-fin of etching first top, formation is positioned at the second sub-fin on the first sub-fin and is positioned at the 3rd sub-fin on the second sub-fin, the angle on described the second sub-fin sidewall and the first sub-fin surface is the first angle, the angle on described the 3rd sub-fin sidewall and the second sub-fin surface is the second angle, and described the first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
2. the formation method of fin as claimed in claim 1, is characterized in that, described the first angle is 70～80 degree, and described the second angle is 82 degree.
3. the formation method of fin as claimed in claim 1, is characterized in that, the method for the substrate of the sub-fin of etching first top is dry etching.
4. the formation method of fin as claimed in claim 3, is characterized in that, the etching gas of described dry etching is Cl
2, O
2with the mist of HBr, wherein, Cl
2flow be 50～150sccm, O
2flow be 5～20sccm, the flow of HBr is 80～180sccm, Cl
2with O
2flow-rate ratio be 7:1～10:1, the power of described dry etching is 800～2500W, bias generator power is 200～700W, etch period is 10～25s.
5. the formation method of fin as claimed in claim 1, is characterized in that, the height of the height of described fin and the second sub-fin and the 3rd sub-fin and ratio be 4:1～3:2.
6. the formation method of fin as claimed in claim 1, is characterized in that, the step of filling separator in described groove comprises:
In described groove and corresponding the first opening, fill separator, described separator is filled full groove and corresponding the first opening and is covered the mask layer of the first opening both sides;
Separator described in planarization, to exposing described mask layer;
Remove the separator in described the first opening.
7. the formation method of fin as claimed in claim 6, is characterized in that, the method for removing the separator in described the first opening is wet etching, and etch rate is 20～40 A/min of clocks.
8. the formation method of fin as claimed in claim 1, is characterized in that, the material of described separator is silica, silicon oxynitride or silicon oxide carbide.
9. the formation method of fin as claimed in claim 1, is characterized in that, the material of described mask layer is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon or carbon silicon oxynitride.
10. the formation method of fin as claimed in claim 1, is characterized in that, it is dry etching that the mask layer that comprises some the first openings is returned to the method for carving.
The formation method of 11. fins as claimed in claim 10, is characterized in that, the etching gas of described dry etching is CH
3f and O
2mist, CH wherein
3the flow of F is 50～200sccm, O
2flow be 10～40sccm, the power of described dry etching is 500～2500W, etch period is 10～40s.
The formation method of 12. fins as claimed in claim 1, is characterized in that, between described substrate surface and the mask layer that comprises some the first openings, is also formed with dielectric layer, and the material of described dielectric layer is silica.
The formation method of 13. fins as claimed in claim 1, is characterized in that, after forming the second sub-fin and the 3rd sub-fin, also comprises:
The mask layer that removal comprises some the second openings;
By adding the hydrofluoric acid solution of ozone to carry out wet etching to the top of the sidewall of the second sub-fin and the 3rd sub-fin and sidewall.
The formation method of 14. fins as claimed in claim 13, is characterized in that, described wet-etch rate is 10～20 A/min of clocks.
The formation method of 15. 1 kinds of fin field effect pipes, is characterized in that, comprising:
Fin as any method forms in claim 1 to 14 is provided;
Formation is across sidewall and the 3rd top of sub-fin and the grid structure of sidewall of described the second sub-fin;
In the second sub-fin of described grid structure both sides and the 3rd sub-fin, form heavily doped region.
16. 1 kinds of fins, is characterized in that, comprising:
Substrate;
Be positioned at some grooves of described substrate;
Be positioned at the separator that groove has predetermined thickness, described insulation surface is lower than substrate surface;
The first sub-fin between separator;
Be positioned on the first sub-fin and the angle on its sidewall and the first sub-fin surface is the second sub-fin of the first angle;
Be positioned on the second sub-fin and the angle on its sidewall and the second sub-fin surface is the 3rd sub-fin of the second angle; Wherein, described the first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
17. fins as claimed in claim 16, is characterized in that, described the first angle is 70～80 degree, and described the second angle is 82 degree.
18. fins as claimed in claim 17, is characterized in that, the height of the height of described fin and the second sub-fin and the 3rd sub-fin and ratio be 4:1～3:2.
19. 1 kinds of fin field effect pipes, is characterized in that, comprising:
As any fin in claim 16 to 18;
Sidewall and the 3rd top of sub-fin and the grid structure of sidewall across described the second sub-fin;
Be positioned at the second sub-fin of described grid structure both sides and the heavily doped region of the 3rd sub-fin.
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