CN104979209A - Manufacturing method for FinFET device - Google Patents
Manufacturing method for FinFET device Download PDFInfo
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- CN104979209A CN104979209A CN201410141011.1A CN201410141011A CN104979209A CN 104979209 A CN104979209 A CN 104979209A CN 201410141011 A CN201410141011 A CN 201410141011A CN 104979209 A CN104979209 A CN 104979209A
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- fin
- semiconductor substrate
- layer
- remove
- hard mask
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Abstract
The invention provides a manufacturing method for a FinFET device. The manufacturing method comprises the following steps: providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate and forming isolation structures between the fins; carrying out ozone cleaning processing so as to form oxide layers on the surfaces, uncovered by the isolation structures, of the fins respectively; and carrying out SiCoNi cleaning processing until the oxide layers are removed. According to the manufacturing method, by carrying out ozone cleaning processing and the SiCoNi cleaning processing in sequence, roughness of the surfaces of the fins can be improved obviously, and implementation effects of the follow-up process steps are not influenced.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of ganoid method making the fin of FinFET (Fin).
Background technology
Fin formula field effect transistor (FinFET) is the advanced semiconductor device for 22nm and following process node, and it can effective scaled the caused short-channel effect being difficult to overcome of control device.
The technique of existing making FinFET generally includes following step: first, silicon substrate forms buried oxide layer to make silicon-on-insulator (SOI) structure; Then, on insulator silicon structure forms silicon layer, its constituent material can be monocrystalline silicon or polysilicon; Then, graphical silicon layer, and etch through patterned silicon layer to form the fin of FinFET.Next, grid can be formed in the both sides of fin, and form germanium silicon stressor layers at the two ends of fin.
In above-mentioned manufacturing process, due to the very thin thickness of the fin of formation, after forming fin, the surface of fin is comparatively coarse, and existing technique is when not processing the surface of the fin formed, implement subsequent process steps, therefore, the implementation result of the processing step of subsequent implementation will be affected.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of FinFET, comprising: Semiconductor substrate is provided, be formed with multiple fin on the semiconductor substrate, between described fin, be formed with isolation structure; Implement ozone clean process, not formed oxide layer by the surface that described isolation structure covers at described fin; Implement SiCoNi clean, until remove described oxide layer.
Further, the width of described fin is all identical, or described fin is divided into multiple fins group with different in width.
Further, the processing step forming described fin comprises: form hard mask layer on the semiconductor substrate; Hard mask layer described in patterning, is formed for etching described Semiconductor substrate to form multiple masks be isolated from each other of described fin thereon; Etch described Semiconductor substrate to form described fin thereon; Wet etching process is adopted to remove described mask.
Further, the processing step of described patterning process comprises: on described hard mask layer, form the photoresist layer with the pattern of described mask; Adopt dry method etch technology remove not the hard mask layer that covers by described photoresist layer; Cineration technics is adopted to remove described photoresist layer.
Further, the processing step forming described isolation structure comprises: deposition forms insulating barrier on the semiconductor substrate, to cover described fin completely; Perform chemical mechanical milling tech and grind described insulating barrier, to expose the top of described fin; Etch back process is adopted to remove the described insulating barrier of part, to form described isolation structure.
Further, the ozone concentration of described ozone clean process is 80-90ppm, and the processing time is 1-3min.
Further, the ozone concentration of described ozone clean process is 85ppm, and the processing time is for being 2min.
Further, the gas component of described SiCoNi clean is NF
3and NH
3, described NF
3flow be 10-20sccm, described NH
3flow be 60-80sccm, the processing time is 5-10sec.
Further, described NF
3flow be 14sccm, described NH
3flow be 70sccm.
According to the present invention, by the described ozone clean process implemented successively and described SiCoNi clean, obviously can improve the roughness on the surface of described fin, guarantee the implementation result of the processing step not affecting follow-up execution.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that Figure 1A-Fig. 1 C obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 2 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the ganoid method making the fin of FinFET of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
With reference to Figure 1A-Fig. 1 C, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.
Be formed with multiple fin 101 on a semiconductor substrate 100, the width of fin 101 is all identical, or fin 101 is divided into multiple fins group with different in width.The processing step forming fin 101 comprises: form hard mask layer on a semiconductor substrate 100, form the various suitable technique that described hard mask layer can adopt those skilled in the art to have the knack of, such as chemical vapor deposition method, the material of described hard mask layer can be nitride, preferred nitrogen SiClx; Hard mask layer described in patterning, formed and be used for etching semiconductor substrate 100 to form multiple masks be isolated from each other of fin 101 thereon, the processing step of described patterning process comprises successively: on described hard mask layer, form the photoresist layer with the pattern of described mask, adopt dry method etch technology remove not the hard mask layer that covers by described photoresist layer, and adopt cineration technics to remove described photoresist layer; Etching semiconductor substrate 100 is to form fin 101 thereon; Wet etching process is adopted to remove described mask.
Isolation structure 102 is formed between fin 101.The processing step forming isolation structure 102 comprises: adopt chemical vapor deposition method to form insulating barrier, to cover fin 101 completely, and the preferred SiO of material of described insulating barrier
2; Perform chemical mechanical milling tech and grind described insulating barrier, to expose the top of fin 101; Remove the described insulating barrier of part, to form isolation structure 102, in the present embodiment, adopt etch back process to remove the described insulating barrier of part, described etch-back is dry etching or wet etching.
Then, as shown in Figure 1B, implement ozone clean process 103, form oxide layer 104 with the surface that structure 102 covers that is not isolated at fin 101.In the present embodiment, the ozone concentration of ozone clean process 103 is 80-90ppm, preferred 85ppm, and the processing time is 1-3min, preferred 2min.
Then, as shown in Figure 1 C, SiCoNi clean 105 is implemented, until remove oxide layer 104.In the present embodiment, the gas component of SiCoNi clean 105 is NF
3and NH
3, wherein, NF
3flow be 10-20sccm, preferred 14sccm, NH
3flow be 60-80sccm, preferred 70sccm, the processing time is 5-10sec.
So far, the processing step that method is according to an exemplary embodiment of the present invention implemented is completed.According to the present invention, by the ozone clean process 103 implemented successively and SiCoNi clean 105, obviously can improve the roughness on the surface of fin 101, guarantee the implementation result of the processing step not affecting follow-up execution.
Next, the making of whole FinFET can be completed by subsequent technique, conventional FinFET front end fabrication process can be implemented:
In an exemplary embodiment, first, form grid structure in the both sides of fin 101 and top, exemplarily, grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.
Particularly, the constituent material of gate dielectric comprises oxide, such as silicon dioxide (SiO
2).Select SiO
2during constituent material as gate dielectric, form gate dielectric by rapid thermal oxidation process (RTO), its thickness is 8-50 dust, but is not limited thereto thickness.
The constituent material of gate material layers comprise in polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide one or more, wherein, metal can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride comprises titanium nitride (TiN); Conductive metal oxide comprises yttrium oxide (IrO
2); Metal silicide comprises titanium silicide (TiSi).When selecting the constituent material of polysilicon as gate material layers, low-pressure chemical vapor phase deposition (LPCVD) technique can be selected to form gate material layers, and its process conditions comprise: reacting gas is silane (SiH
4), its flow is 100 ~ 200sccm, preferred 150sccm; Temperature in reaction chamber is 700 ~ 750 DEG C; Pressure in reaction chamber is 250 ~ 350mTorr, preferred 300mTorr; Described reacting gas can also comprise buffer gas, and described buffer gas is helium (He) or nitrogen (N
2), its flow is 5 ~ 20 liters/min (slm), preferred 8slm, 10slm or 15slm.
The constituent material of grid hard masking layer comprise in oxide, nitride, nitrogen oxide and amorphous carbon one or more, wherein, oxide comprises boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride comprises silicon nitride (SiN); Nitrogen oxide comprises silicon oxynitride (SiON).Any prior art that the formation method of grid hard masking layer can adopt those skilled in the art to have the knack of, preferred chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
Then, ion implantation is performed, to form source/drain in the fin 101 do not covered by grid structure.Then, form the offset side wall near grid structure in grid structure both sides, its constituent material is SiO
2, a kind of in SiN, SiON or their combination.Formed in grid structure both sides in the process of offset side wall, the both sides of fin 101 also can form offset side wall, therefore, next, remove the offset side wall being positioned at fin 101 both sides.Then, with described offset side wall for mask, epitaxial growth technology is adopted to expand the area being positioned at fin 101 outside grid structure region, with the resistance of the source/drain formed before reducing.
Then, formed successively on a semiconductor substrate 100 and there is the contact etch stop layer and interlayer dielectric layer that can produce stress characteristics, perform cmp to expose the top of grid structure.Then, remove grid structure, in the groove stayed, form high k-metal gate structure, exemplarily, this structure comprises stacked high k dielectric layer, cover layer, workfunction layers, barrier layer and metal material layer from bottom to top.Next, form another interlayer dielectric layer, then, formed in above-mentioned interlayer dielectric layer and be communicated with the top of described metal gate structure and the contact hole of pole, described source/drain region, by described contact hole, the top of the described metal gate structure exposed and described source/drain region extremely on form self-aligned silicide, fill metal (being generally tungsten) and formed in described contact hole and connect enforcement back end fabrication and the contact plug of the interconnecting metal layer that formed and described self-aligned silicide.
Next, conventional FinFET back end fabrication can be implemented, comprising: the formation of multiple interconnecting metal layer, usually adopt dual damascene process; The formation of metal pad, for implementing wire bonding during device package.
With reference to Fig. 2, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide Semiconductor substrate, be formed with multiple fin on a semiconductor substrate, between fin, be formed with isolation structure;
In step 202., implement ozone clean process, form oxide layer with the surface that structure covers that is not isolated at fin;
In step 203, implement SiCoNi clean, until remove oxide layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a manufacture method for FinFET, comprising:
Semiconductor substrate is provided, is formed with multiple fin on the semiconductor substrate, between described fin, be formed with isolation structure;
Implement ozone clean process, not formed oxide layer by the surface that described isolation structure covers at described fin;
Implement SiCoNi clean, until remove described oxide layer.
2. method according to claim 1, is characterized in that, the width of described fin is all identical, or described fin is divided into multiple fins group with different in width.
3. method according to claim 1, is characterized in that, the processing step forming described fin comprises: form hard mask layer on the semiconductor substrate; Hard mask layer described in patterning, is formed for etching described Semiconductor substrate to form multiple masks be isolated from each other of described fin thereon; Etch described Semiconductor substrate to form described fin thereon; Wet etching process is adopted to remove described mask.
4. method according to claim 3, is characterized in that, the processing step of described patterning process comprises: on described hard mask layer, form the photoresist layer with the pattern of described mask; Adopt dry method etch technology remove not the hard mask layer that covers by described photoresist layer; Cineration technics is adopted to remove described photoresist layer.
5. method according to claim 1, is characterized in that, the processing step forming described isolation structure comprises: deposition forms insulating barrier on the semiconductor substrate, to cover described fin completely; Perform chemical mechanical milling tech and grind described insulating barrier, to expose the top of described fin; Etch back process is adopted to remove the described insulating barrier of part, to form described isolation structure.
6. method according to claim 1, is characterized in that, the ozone concentration of described ozone clean process is 80-90ppm, and the processing time is 1-3min.
7. method according to claim 6, is characterized in that, the ozone concentration of described ozone clean process is 85ppm, and the processing time is for being 2min.
8. method according to claim 1, is characterized in that, the gas component of described SiCoNi clean is NF
3and NH
3, described NF
3flow be 10-20sccm, described NH
3flow be 60-80sccm, the processing time is 5-10sec.
9. method according to claim 8, is characterized in that, described NF
3flow be 14sccm, described NH
3flow be 70sccm.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410141011.1A CN104979209A (en) | 2014-04-09 | 2014-04-09 | Manufacturing method for FinFET device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410141011.1A CN104979209A (en) | 2014-04-09 | 2014-04-09 | Manufacturing method for FinFET device |
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| CN104979209A true CN104979209A (en) | 2015-10-14 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120034761A1 (en) * | 2010-08-04 | 2012-02-09 | Applied Materials, Inc. | Method of removing contaminants and native oxides from a substrate surface |
| CN102687249A (en) * | 2009-12-23 | 2012-09-19 | 应用材料公司 | Smooth siconi etch for silicon-containing films |
| CN102822947A (en) * | 2010-03-10 | 2012-12-12 | 应用材料公司 | Apparatus and methods for cyclical oxidation and etching |
| CN103578988A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Fin part and finned-type field-effect transistor and forming method thereof |
-
2014
- 2014-04-09 CN CN201410141011.1A patent/CN104979209A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102687249A (en) * | 2009-12-23 | 2012-09-19 | 应用材料公司 | Smooth siconi etch for silicon-containing films |
| CN102822947A (en) * | 2010-03-10 | 2012-12-12 | 应用材料公司 | Apparatus and methods for cyclical oxidation and etching |
| US20120034761A1 (en) * | 2010-08-04 | 2012-02-09 | Applied Materials, Inc. | Method of removing contaminants and native oxides from a substrate surface |
| CN103578988A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Fin part and finned-type field-effect transistor and forming method thereof |
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Application publication date: 20151014 |