CN103578988B - The formation method of fin, fin field effect pipe and fin and fin field effect pipe - Google Patents
The formation method of fin, fin field effect pipe and fin and fin field effect pipe Download PDFInfo
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- CN103578988B CN103578988B CN201210254002.4A CN201210254002A CN103578988B CN 103578988 B CN103578988 B CN 103578988B CN 201210254002 A CN201210254002 A CN 201210254002A CN 103578988 B CN103578988 B CN 103578988B
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 230000005669 field effect Effects 0.000 title claims abstract description 49
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 79
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 14
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000003595 mist Substances 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- 230000005012 migration Effects 0.000 description 6
- 238000013508 migration Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A formation method for fin, fin field effect pipe and fin, fin field effect pipe, the formation method of fin comprises: provide substrate; Form the mask layer comprising some first openings at described substrate surface, described first opening exposes substrate; To comprise the mask layer of some first openings for mask, etch described substrate, form some grooves; Separator is filled in described groove; Carry out back carving to mask layer along the first opening, increase the width of the first opening, in described mask layer, form some second openings; Take mask layer as mask, etch described separator along the second opening, make separator remain predetermined thickness, the substrate between the separator of described residue predetermined thickness is the first sub-fin; Etch the substrate above the first sub-fin, form the second sub-fin be positioned on the first sub-fin and the 3rd sub-fin be positioned on the second sub-fin.Fin of the present invention, fin field effect pipe and forming method thereof improve the stability of fin field effect pipe.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of fin, fin field effect pipe and fin and fin field effect pipe.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is towards higher component density, and the future development of higher integrated level.Transistor is just being widely used at present as the most basic semiconductor device, and therefore along with the component density of semiconductor device and the raising of integrated level, the grid size of transistor is also shorter and shorter.But the grid size of transistor shortens and transistor can be made to produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes fin field effect pipe (FinFET), please refer to Fig. 1 and Fig. 2, Fig. 1 is the cross-sectional view of the fin field effect pipe of prior art, Fig. 2 is the cross-sectional view of Fig. 1 on AA' direction, comprising:
Semiconductor substrate 10; Be positioned at the fin 11 of described semiconductor substrate surface, the material of described fin 11 is silicon, germanium or SiGe; Be positioned at the insulating barrier 12 of described Semiconductor substrate 10 and fin 11 sidewall surfaces, the surface of described insulating barrier 12 is lower than described fin 11 top; Across the top of described fin 11 and the grid structure 13 of sidewall; Be positioned at the fin heavy doping 16 of described grid structure 13 both sides.
It should be noted that, described grid structure 13 comprises: across the top of described fin 11 and the gate dielectric layer 14 of sidewall and the gate electrode layer 15 being positioned at described gate dielectric layer 14 surface; The part that the top of described fin 11 and sidewall contact with grid structure 13 becomes channel region.
In the fin field effect pipe that prior art is formed, fin 11 is vertical with substrate 10 surface, and it is to the unstressed effect in channel region, and in channel region, the speed of electric charge diffusion is comparatively slow, the poor-performing of fin field effect pipe.And the uniformity of the pattern of the sidewall of the fin 11 of existing formation is poor, the lack of homogeneity opposite sex of the pattern of the sidewall of fin 11 can make the threshold voltage of fin field effect pipe offset, and affects the stability of fin field effect pipe.
More fin field effect pipe please refer to the U.S. patent documents that publication number is US2011068405A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fin, fin field effect pipe and fin and fin field effect pipe, avoids the performance of each formed fin field effect pipe there are differences, improve form the electric property of fin field effect pipe.
For solving the problem, the invention provides a kind of formation method of fin, comprising: substrate is provided; Form the mask layer comprising some first openings at described substrate surface, described first opening exposes substrate; To comprise the mask layer of some first openings for mask, etch described substrate, form some grooves; Separator is filled in described groove; Carry out back carving to mask layer along the first opening, increase the width of the first opening, in described mask layer, form some second openings; Take mask layer as mask, etch described separator along the second opening, make separator remain predetermined thickness, the substrate between the separator of described residue predetermined thickness is the first sub-fin; Etch the substrate above the first sub-fin, form the second sub-fin be positioned on the first sub-fin and the 3rd sub-fin be positioned on the second sub-fin, the angle of described second sub-fin sidewall and the first sub-fin portion surface is the first angle, the angle of described 3rd sub-fin sidewall and the second sub-fin portion surface is the second angle, and described first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
Optionally, described first angle is 70 ~ 80 degree, and described second angle is 82 degree.
Optionally, the method for the substrate above etching the first sub-fin is dry etching, and the etching gas of described dry etching is Cl
2, O
2with the mist of HBr, wherein, Cl
2flow be 50 ~ 150sccm, O
2flow be the flow of 5 ~ 20sccm, HBr be 80 ~ 180sccm, Cl
2with O
2flow-rate ratio be 7:1 ~ 10:1, the power of described dry etching is 800 ~ 2500W, and bias generator power is 200 ~ 700W, and etch period is 10 ~ 25s.
Accordingly, present invention also offers a kind of formation method of fin field effect pipe, comprising: the fin that any one method above-mentioned is formed is provided; Formed across the sidewall of described second sub-fin and the top of the 3rd sub-fin and the grid structure of sidewall; Heavily doped region is formed in the second sub-fin and the 3rd sub-fin of described grid structure both sides.
Present invention also offers a kind of fin, comprising: substrate; Be positioned at some grooves of described substrate; Be positioned at the separator that groove has predetermined thickness, described insulation surface is lower than substrate surface; Between separator first sub-fin; To be positioned on the first sub-fin and the angle of its sidewall and the first sub-fin portion surface is the second sub-fin of the first angle; To be positioned on the second sub-fin and the angle of its sidewall and the second sub-fin portion surface is the 3rd sub-fin of the second angle; Wherein, described first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
Optionally, described first angle is 70 ~ 80 degree, and described second angle is 82 degree.
Optionally, the height of described fin and the height of the second sub-fin and the 3rd sub-fin and ratio be 4:1 ~ 3:2.
Accordingly, present invention also offers a kind of fin field effect pipe, comprising: any one fin above-mentioned; Across the sidewall of described second sub-fin and the top of the 3rd sub-fin and the grid structure of sidewall; Be positioned at the second sub-fin of described grid structure both sides and the heavily doped region of the 3rd sub-fin.
Compared with prior art, technical solution of the present invention has the following advantages:
First carry out etching to substrate and form groove, and in groove, form the separator of predetermined thickness, described insulation surface is lower than substrate surface, and the substrate between separator is the first sub-fin; Then the substrate be positioned at above the first sub-fin is etched, form the second sub-fin and the 3rd sub-fin, described second sub-fin is positioned at above the first sub-fin and the angle of its sidewall and the first sub-fin upper surface is the first angle, described 3rd sub-fin is positioned at above the second sub-fin and the angle of its sidewall and the second sub-fin upper surface is the second angle, because the A/F between the 3rd sub-fin opposing sidewalls is greater than the second sub-fin, be beneficial to the formation of subsequent gate structure; And, because the first sub-fin, the second sub-fin and the 3rd sub-fin are all by being formed substrate etching after substrate is formed, first sub-fin and the second sub-fin link up and the angle of the second sub-fin sidewall and the first sub-fin upper surface is less than the angle of the first sub-fin and substrate top surface, after follow-up formation is across the second sub-fin sidewall and the top of the 3rd sub-fin and the grid structure of sidewall, can effectively increase the stress put on grid structure channel region beneath, improve the migration rate of electric charge in channel region.
Further, by the hydrofluoric acid solution that adds ozone, wet etching is carried out to the sidewall of described second sub-fin and the top of the 3rd sub-fin and sidewall, silicon atom on the top of the sidewall of the second sub-fin and the 3rd sub-fin and sidewall and ozone are reacted formation oxide layer, formed oxide layer is removed again by hydrofluoric acid solution, make the pattern of the second sub-fin and the 3rd sub-fin portion surface even, prevent the threshold voltage of the fin field effect pipe comprising formed fin from offseting, improve the stability of fin field effect pipe.
After above-mentioned fin is formed, formed across the second sub-fin sidewall, the top of the 3rd sub-fin and the grid structure of sidewall, and heavily doped region is formed in the second sub-fin and the 3rd sub-fin of grid structure both sides, effectively improve the migration rate of electric charge in formed fin field effect pipe channel region, improve the electric property of fin field effect pipe.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 forms by existing technique the schematic diagram of fin field effect pipe;
Fig. 3 is the schematic flow sheet of a formation method execution mode of fin of the present invention;
The formation method embodiment that Fig. 4 ~ Figure 12 is fin of the present invention form the schematic diagram of each stage fin;
The formation method embodiment that Figure 13 ~ Figure 15 is fin field effect pipe of the present invention form the schematic diagram of each stage fin field effect pipe.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, prior art form fin and the substrate transverse of fin field effect pipe, fin is to the unstressed effect in channel region of fin field effect pipe comprising fin, and in channel region, the speed of electric charge diffusion is comparatively slow, the poor-performing of fin field effect pipe.And the uniformity of the sidewall of the fin of existing formation is poor, the sidewall uniformity otherness of fin makes the threshold voltage of fin field effect pipe offset, and affects the stability of fin field effect pipe.
For solving the problem, inventor proposes a kind of formation method of fin, with reference to figure 3, is the schematic flow sheet of a formation method execution mode of fin of the present invention, comprises:
Step S1, provides substrate;
Step S2, form the mask layer comprising some first openings at described substrate surface, described first opening exposes substrate;
Step S3, to comprise the mask layer of some first openings for mask, etches described substrate, forms some grooves;
Step S4, fills separator in described groove;
Step S5, carries out back carving to mask layer along the first opening, increases the width of the first opening, form some second openings in described mask layer;
Step S6, take mask layer as mask, etches described separator along the second opening, and make separator remain predetermined thickness, the substrate between the separator of described residue predetermined thickness is the first sub-fin;
Step S7, etch the substrate above the first sub-fin, form the second sub-fin be positioned on the first sub-fin and the 3rd sub-fin be positioned on the second sub-fin, the angle of described second sub-fin sidewall and the first sub-fin portion surface is the first angle, the angle of described 3rd sub-fin sidewall and the second sub-fin portion surface is the second angle, and described first sub-fin, the second sub-fin and the 3rd sub-fin form fin;
Step S8, removes the mask layer comprising some second openings;
Step S9, carries out wet etching by the hydrofluoric acid solution that adds ozone to the top of the sidewall of the second sub-fin and the 3rd sub-fin and sidewall.
With reference to figure 4 ~ Figure 12, the formation method embodiment of fin of the present invention form the schematic diagram of each stage fin, composition graphs 4 ~ Figure 12, is described further by the formation method of specific embodiment to fin of the present invention.
With reference to figure 4, provide substrate 201.
In the present embodiment, the material of described substrate 201 is monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi) or carborundum (SiC); Also can be silicon-on-insulator (SOI) or germanium on insulator (GOI); Can also be other material, the III-V such as such as GaAs.
Continue with reference to figure 4, form dielectric layer 205a on described substrate 201 surface and comprise the mask layer 207a of some first openings 203, described first opening 203 exposes dielectric layer 205a.
Wherein, the material of described dielectric layer 205a is silica, to protect described substrate 201 in subsequent etching processes; Described mask layer 207a is as mask when subsequent etching dielectric layer 205a and substrate 201, and the material of described mask layer 207a is silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide carbide (SiOC), amorphous carbon (a-C) or carbon silicon oxynitride (SiOCN).In the present embodiment, the material of described mask layer 207a is silicon nitride.
Form the step comprising the mask layer 207a of some first openings 203 to comprise:
Form dielectric layer 205a, mask layer on described substrate 201 surface from the bottom to top successively and comprise the photoresist layer (not shown) of the first patterns of openings;
With the described photoresist layer of the first patterns of openings that comprises for mask, etch described mask layer, form the mask layer 207a comprising some first openings 203, described first opening 203 exposes dielectric layer 205a;
The photoresist layer of the first patterns of openings is comprised described in removal.
In other embodiments, can not also comprise described dielectric layer 205a, directly form on substrate 201 surface the mask layer 207a comprising some first openings 203, it does not limit the scope of the invention.
With reference to figure 5, to comprise the mask layer 207a of some first openings 203 for mask, dielectric layer 205a and substrate 201 described in etching Fig. 4, form some grooves 209.
In the present embodiment, the method forming described groove 209 is dry etching, as plasma etching.Vertical range apart from substrate 201 top, groove 209 both sides bottom described groove 209 is 800 ~ 3000 dusts.
With reference to figure 6, fill separator 213a in described groove 209 and corresponding first opening 203 in Figure 5.Between the fin that described separator 213a is used for follow-up formation and electric isolation between fin and substrate 201.
The step forming described separator 213a comprises:
In described groove 209 and corresponding first opening 203, fill separator (not shown), described separator is filled full groove 209 and corresponding first opening 203 and is covered the mask layer 207a of the first opening 203 both sides;
Separator described in planarization, to exposing described mask layer 207a.
The material of described separator can be silica (SiO
2), silicon oxynitride (SiON) or silicon oxide carbide (SiOC), in the present embodiment, the material of described separator is silica.
The formation process of described separator is chemical vapour deposition (CVD) (CVD, ChemicalVaporDeposition) technique, such as: high density plasma CVD technique (HDPCVD) or partially aumospheric pressure cvd technique (SACVD), but the present invention is not limited thereto.
The method of separator described in planarization is cmp (CMP, ChemicalMechanicalPolishing) technique.
In conjunction with reference to figure 5 ~ Fig. 7, remove the separator 213a in the first opening 203, make the surface of the separator 213b in remaining groove 209 lower than described mask layer 207a surface.
In the present embodiment, remove the separator 213a in the first opening 203 by wet etching, described etching solution can be hydrofluoric acid solution, but the present invention is not limited thereto.
It should be noted that, in the present embodiment, the substrate 201 of groove 209 both sides higher than the top of described groove 209 both sides substrate 201, to carry out back in process at quarter at the follow-up mask layer 207a to comprising some first openings 203, need be protected in the surface of separator 213b.
With reference to figure 8, carry out back carving along the first opening 203 couples of mask layer 207a in Fig. 7, increase the width of the first opening 203, in described mask layer 207b, form some second openings 208.
In the present embodiment, the method for carrying out back carving to the mask layer 207a comprising some first openings 203 is dry etching, and the etching gas of described dry etching is CH
3f and O
2mist, wherein, CH
3the flow of F is 50 ~ 200sccm, O
2flow be 10 ~ 40sccm, the power of described dry etching is 500 ~ 2500W, and etch period is 10 ~ 40s.
With reference to figure 9, with mask layer 207b for mask, etch described separator 213b along the second opening 208, make separator 213b remain predetermined thickness, the substrate between the separator 215 of described residue predetermined thickness is the first sub-fin 212a.
Wherein, the surface of the separator 215 of described residue predetermined thickness is lower than the surface of described separator 215 both sides substrate 201.
In the present embodiment, the method for etching separator 213b is wet etching, and the etching solution of described wet etching is hydrofluoric acid solution, and etch rate is 20 ~ 40 A/min of clocks.The height h of the substrate 201 above described first sub-fin 212a
2be 100 ~ 1000 dusts (separator 215 surface namely remaining predetermined thickness is 100 ~ 1000 dusts with the vertical range at the top of isolation structure 215 both sides substrate 201), the height h of described fin 212a
1with the height h of the first sub-fin 212a upper substrate 201
2ratio be 4:1 ~ 3:2.
With reference to Figure 10, etch the substrate 201 above the first sub-fin 212a, form the second sub-fin 212b be positioned on the first sub-fin 212a and the 3rd sub-fin 212c be positioned on the second sub-fin 212b, the angle on described second sub-fin 212b sidewall and the first sub-fin 212a surface
be the first angle, the angle theta on described 3rd sub-fin 212c sidewall and the second sub-fin 212b surface is the second angle, and described first sub-fin 212a, the second sub-fin 212b and the 3rd sub-fin 212c form fin 212.
Wherein, the width between adjacent 3rd sub-fin 212c top is consistent with the A/F of described second opening 208.
In the present embodiment, the method for the substrate 201 above etching the first sub-fin 212a is dry etching.The etching gas of described dry etching is Cl
2, O
2with the mist of HBr, wherein Cl
2flow be 50 ~ 150sccm, O
2flow be the flow of 5 ~ 20sccm, HBr be 80 ~ 180sccm, Cl
2with O
2flow-rate ratio be 7:1 ~ 10:1, the power of dry etching is 800 ~ 2500W, bias generator power is 200 ~ 700W, and etch period is 10 ~ 25s.
Because the position at the bottom of the second sub-fin 212b and the top of the 3rd sub-fin 212c is determined, when being etched the substrate 201 above the first sub-fin 212a by above-mentioned dry etching, when the sidewall of the second sub-fin 212b and the angle on isolation structure 215 surface
when being the first angle, the sidewall of the 3rd sub-fin 212c and the angle theta on isolation structure 215 surface are the second angle.
Due to the first sub-fin 212a, second sub-fin 212b and the 3rd sub-fin 212c is formed by etching substrate 201 after substrate 201 is formed, described first sub-fin 212a and the second sub-fin 212b links up and the angle of the second sub-fin 212b sidewall and isolation structure 215 upper surface is less than the first sub-fin 212a, after follow-up formation is across the second sub-fin 212b sidewall and the top of the 3rd sub-fin 212c and the grid structure of sidewall, can effectively increase the stress put on grid structure channel region beneath, improve the migration rate of electric charge in channel region, further raising comprises the response speed of the fin field effect pipe of formed fin 212.
Preferably, make the second angle be 82 degree, described first angle is 70 ~ 80 degree, and now the indices of crystallographic plane of the 3rd sub-fin 212c sidewall are (551), and in channel region, charge migration speed is maximum.
Meanwhile, due to the first angle
be less than the second angle θ, with the first angle
the situation equaling the second angle θ is compared, the width w of the second sub-fin 212b opening
1comparatively large, be beneficial to the formation of subsequent gate structure.
With reference to Figure 11, remove the mask layer 207b comprising some second openings 208 in Figure 10.
In the present embodiment, removing the method comprising the mask layer 207b of some second openings 208 is wet etching, and the solution of the employing of described wet etching is hot phosphoric acid solution.
In other embodiments, the technique of other any appropriate can also be adopted to remove mask layer 207b, and the present invention does not limit this.
With reference to Figure 12, by the hydrofluoric acid solution adding ozone, wet etching is carried out to the oxide layer at the 3rd sub-fin 212c top described in Figure 11 and the sidewall of the second sub-fin 212b and the 3rd sub-fin 212c.
In the present embodiment, the flow passing into ozone in described hydrofluoric acid solution is 500 ~ 2000sccm, and the etch rate of described wet etching is 10 ~ 20 A/min of clocks.
In the present embodiment, the silicon atom of ozone and the second sub-fin 211b and the 3rd sub-fin 211c sidewall surfaces reacts, form silica, removed by the oxide etch of hydrofluoric acid solution by the oxide layer at the 3rd sub-fin 212c top and the sidewall surfaces of the second sub-fin 212b and the 3rd sub-fin 212c again, make form the sidewall surfaces even uniform of the second sub-fin 212b and the 3rd sub-fin 212c, improve the second sub-fin 211b and the conjugation between the 3rd sub-fin 211c sidewall and follow-up formation gate dielectric layer, make the threshold voltage stabilization of the fin field effect pipe comprising formed fin, improve the stability of fin field effect pipe.
In other embodiments, when not comprising dielectric layer 205b in Figure 10 between mask layer 207b and substrate 201, after the described mask layer 207b of removal, wet etching is carried out by the sidewall of hydrofluoric acid solution to the 3rd sub-fin 212c top and sidewall and the second sub-fin 212b described in Figure 11 adding ozone, the silicon atom of the sidewall surfaces of ozone and the 3rd sub-fin 212c top and sidewall and the second sub-fin 212b reacts, form silica, by hydrofluoric acid solution, the silica formed is removed again, make the sidewall even uniform of the 3rd sub-fin 212c top and sidewall and the second sub-fin 212b.
Based on above-mentioned steps formed fin as shown in figure 12, comprising:
Substrate 201;
Be positioned at some grooves of described substrate 201;
Be positioned at the separator 215 that groove has predetermined thickness, described separator 215 surface is lower than substrate 201 surface;
Between separator 215 first sub-fin 212a;
To be positioned on the first sub-fin 212a and the angle on its sidewall and the first sub-fin 212a surface is the second sub-fin 212b of the first angle;
To be positioned on the second sub-fin 212b and the angle on its sidewall and the second sub-fin 212b surface be the 3rd sub-fin 212c of the second angle wherein, described first sub-fin 212a, the second sub-fin 212b and the 3rd sub-fin 212c form fin.
Preferably, described first angle
be 70 ~ 80 degree, described second angle θ is 82 degree; The height of described second sub-fin 212b and the 3rd sub-fin 212c and be that (that is, the first sub-fin 212a surface is apart from the vertical range h at the 3rd sub-fin 212c top for 100 ~ 1000 dusts
2be 100 ~ 1000 dusts.The height of the height of described fin 212 and the second sub-fin 212b and the 3rd sub-fin 212c and ratio be 4:1 ~ 3:2.
In above embodiment, first etching is carried out to substrate and form groove, the separator of predetermined thickness is formed in groove, described insulation surface is lower than substrate surface, and using the first sub-fin of substrate between the separator of predetermined thickness as fin, then the substrate be positioned at above the first sub-fin is etched, form the second sub-fin and the 3rd sub-fin, described second sub-fin is positioned on the first sub-fin and the angle of its sidewall and the first sub-fin portion surface is the first angle, described 3rd sub-fin is positioned on the second sub-fin and the angle of its sidewall and the second sub-fin portion surface is the second angle, due to adjacent second sub-fin opposing sidewalls between A/F become large, be beneficial to the formation of subsequent gate structure, and, because the first sub-fin, the second sub-fin and the 3rd sub-fin are all by being formed substrate etching after substrate is formed, described first sub-fin and the second sub-fin link up and the angle of the second sub-fin sidewall and isolation structure upper surface is less than the first sub-fin, after follow-up formation is across the second sub-fin sidewall and the top of the 3rd sub-fin and the grid structure of sidewall, can effectively increase the stress put on grid structure channel region beneath, improve the migration rate of electric charge in channel region.
In addition, by the hydrofluoric acid solution that adds ozone, wet etching is carried out to the sidewall of described second sub-fin and the top of the 3rd sub-fin and sidewall, silicon atom on the top of the sidewall of the second sub-fin and the 3rd sub-fin and sidewall and ozone are reacted formation oxide layer, formed oxide layer is removed again by hydrofluoric acid solution, make the pattern of the second sub-fin and the 3rd sub-fin portion surface even, prevent the threshold voltage of the fin field effect pipe comprising formed fin from offseting, improve the stability of fin field effect pipe.
In conjunction with Figure 13 ~ Figure 15, be described further by the formation method of specific embodiment to fin field effect pipe of the present invention.
With reference to Figure 13, a kind of fin 312 formed by above-mentioned steps is provided, described fin 312 comprises the first sub-fin 312a by carrying out multiple etching formation to substrate 301, the 3rd sub-fin 312c being positioned at the second sub-fin 312b on the first fin 312a and being positioned on the second fin 312b, substrate 301 between described first sub-fin 312a is formed with the separator 315 of some predetermined thickness, the described sidewall of the second sub-fin 312b and the angle β on separator 315 surface are 70 ~ 80 degree, the described sidewall of the 3rd sub-fin 312c and the angle δ on separator 315 surface are 82 degree.
With reference to Figure 14, form the grid structure across described second sub-fin 312b sidewall and the 3rd sub-fin 312c top and sidewall, described grid structure comprises gate dielectric layer 314 and grid 316.
With reference to Figure 14 and Figure 14 along the cutaway view Figure 15 in BB ' direction, in the second sub-fin 312b and the 3rd sub-fin 312c of described grid structure both sides, form heavily doped region 318.
Because the formation process of grid structure and heavily doped region is well known to those skilled in the art, do not repeat at this.
In the present embodiment, comprising the first sub-fin, (described second sub-fin is positioned on the first sub-fin and the angle of its sidewall and the first sub-fin portion surface is the first angle for the fin of the second sub-fin and the 3rd sub-fin, described 3rd sub-fin is positioned on the second sub-fin and the angle of its sidewall and the second sub-fin portion surface is the second angle) formed after, formed across the second sub-fin sidewall, the top of the 3rd sub-fin and the grid structure of sidewall, heavily doped region is formed again in the second sub-fin and the 3rd sub-fin of grid structure both sides, form the fin field effect pipe shown in Figure 14 and 15, effectively improve the migration rate of electric charge in formed fin field effect pipe channel region, improve the electric property of fin field effect pipe.
In addition, hydrofluoric acid solution by adding ozone is carried out to the fin field effect pipe of wet etching to the sidewall of the second sub-fin and the 3rd sub-fin top and sidewall, because the pattern of the second sub-fin and the 3rd sub-fin portion surface is even, avoid the threshold voltage of the fin field effect pipe comprising formed fin to offset, improve the stability of fin field effect pipe.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (17)
1. a formation method for fin, is characterized in that, comprising:
Substrate is provided;
Form the mask layer comprising some first openings at described substrate surface, described first opening exposes substrate;
To comprise the mask layer of some first openings for mask, etch described substrate, form some grooves;
Separator is filled in described groove;
Carry out back carving to mask layer along the first opening, increase the width of the first opening, in described mask layer, form some second openings;
Take mask layer as mask, etch described separator along the second opening, make separator remain predetermined thickness, the substrate between the separator of described residue predetermined thickness is the first sub-fin;
Etch the substrate above the first sub-fin, form the second sub-fin be positioned on the first sub-fin and the 3rd sub-fin be positioned on the second sub-fin, the angle of described second sub-fin sidewall and the first sub-fin portion surface is 70 ~ 80 degree, the angle of described 3rd sub-fin sidewall and the second sub-fin portion surface is 82 degree, and described first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
2. the formation method of fin as claimed in claim 1, is characterized in that, the method for the substrate above etching the first sub-fin is dry etching.
3. the formation method of fin as claimed in claim 2, it is characterized in that, the etching gas of described dry etching is Cl
2, O
2with the mist of HBr, wherein, Cl
2flow be 50 ~ 150sccm, O
2flow be the flow of 5 ~ 20sccm, HBr be 80 ~ 180sccm, Cl
2with O
2flow-rate ratio be 7:1 ~ 10:1, the power of described dry etching is 800 ~ 2500W, and bias generator power is 200 ~ 700W, and etch period is 10 ~ 25s.
4. the formation method of fin as claimed in claim 1, is characterized in that, the height of the height of described fin and the second sub-fin and the 3rd sub-fin and ratio be 4:1 ~ 3:2.
5. the formation method of fin as claimed in claim 1, it is characterized in that, the step of filling separator in described groove comprises:
In described groove and corresponding first opening, fill separator, described separator is filled full groove and corresponding first opening and is covered the mask layer of the first opening both sides;
Separator described in planarization, to exposing described mask layer;
Remove the separator in described first opening.
6. the formation method of fin as claimed in claim 5, it is characterized in that, the method removing the separator in described first opening is wet etching, and etch rate is 20 ~ 40 A/min of clocks.
7. the formation method of fin as claimed in claim 1, it is characterized in that, the material of described separator is silica, silicon oxynitride or silicon oxide carbide.
8. the formation method of fin as claimed in claim 1, it is characterized in that, the material of described mask layer is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon or carbon silicon oxynitride.
9. the formation method of fin as claimed in claim 1, is characterized in that, the method for carrying out back carving to the mask layer comprising some first openings is dry etching.
10. the formation method of fin as claimed in claim 9, it is characterized in that, the etching gas of described dry etching is CH
3f and O
2mist, wherein CH
3the flow of F is 50 ~ 200sccm, O
2flow be 10 ~ 40sccm, the power of described dry etching is 500 ~ 2500W, and etch period is 10 ~ 40s.
The formation method of 11. fins as claimed in claim 1, is characterized in that, between described substrate surface and the mask layer comprising some first openings, be also formed with dielectric layer, the material of described dielectric layer is silica.
The formation method of 12. fins as claimed in claim 1, is characterized in that, after forming the second sub-fin and the 3rd sub-fin, also comprises:
Remove the mask layer comprising some second openings;
By the hydrofluoric acid solution that adds ozone, wet etching is carried out to the top of the sidewall of the second sub-fin and the 3rd sub-fin and sidewall.
The formation method of 13. fins as claimed in claim 12, is characterized in that, described wet-etch rate is 10 ~ 20 A/min of clocks.
The formation method of 14. 1 kinds of fin field effect pipes, is characterized in that, comprising:
Fin as any one method in claim 1 to 13 is formed is provided;
Formed across the sidewall of described second sub-fin and the top of the 3rd sub-fin and the grid structure of sidewall;
Heavily doped region is formed in the second sub-fin and the 3rd sub-fin of described grid structure both sides.
15. 1 kinds of fins, is characterized in that, comprising:
Substrate;
Be positioned at some grooves of described substrate;
Be positioned at the separator that groove has predetermined thickness, described insulation surface is lower than substrate surface;
Between separator first sub-fin;
To be positioned on the first sub-fin and the angle of its sidewall and the first sub-fin portion surface is the second sub-fin of 70 ~ 80 degree;
To be positioned on the second sub-fin and the angle of its sidewall and the second sub-fin portion surface is the 3rd sub-fin of 82 degree; Wherein, described first sub-fin, the second sub-fin and the 3rd sub-fin form fin.
16. fins as claimed in claim 15, is characterized in that, the height of the height of described fin and the second sub-fin and the 3rd sub-fin and ratio be 4:1 ~ 3:2.
17. 1 kinds of fin field effect pipes, is characterized in that, comprising:
As any one fin in claim 15 to 16;
Across the sidewall of described second sub-fin and the top of the 3rd sub-fin and the grid structure of sidewall; Be positioned at the second sub-fin of described grid structure both sides and the heavily doped region of the 3rd sub-fin.
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| CN103730362B (en) * | 2012-10-11 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN104425263B (en) * | 2013-08-20 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN104979209A (en) * | 2014-04-09 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for FinFET device |
| CN105097522B (en) * | 2014-05-04 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN106158748B (en) | 2015-04-07 | 2022-01-18 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| KR102328564B1 (en) | 2015-04-14 | 2021-11-18 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
| CN105448968B (en) * | 2015-10-15 | 2020-05-12 | 格科微电子（上海）有限公司 | Method for manufacturing fin field effect transistor |
| CN106960794B (en) * | 2016-01-11 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin and the forming method of fin field effect pipe |
| US9899526B2 (en) * | 2016-01-15 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin-type field effect transistor structure and manufacturing method thereof |
| CN107887425B (en) * | 2016-09-30 | 2020-05-12 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor device |
| CN109962017A (en) * | 2017-12-22 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| US6323092B1 (en) * | 1998-12-19 | 2001-11-27 | United Microelectronics Corp. | Method for forming a shallow trench isolation |
| CN101312148A (en) * | 2007-05-22 | 2008-11-26 | 力晶半导体股份有限公司 | Shallow groove isolation structure and floating grid manufacture method |
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| JP4966153B2 (en) * | 2007-10-05 | 2012-07-04 | 株式会社東芝 | Field effect transistor and manufacturing method thereof |
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| US6323092B1 (en) * | 1998-12-19 | 2001-11-27 | United Microelectronics Corp. | Method for forming a shallow trench isolation |
| CN101312148A (en) * | 2007-05-22 | 2008-11-26 | 力晶半导体股份有限公司 | Shallow groove isolation structure and floating grid manufacture method |
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