CN109148370B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and openings are formed in the second areas of the fin part; forming an initial isolation layer on the substrate, on the side wall of the fin part and in the opening; forming a protection structure on the initial isolation layer and the first areas of the fin parts on two sides of the initial isolation layer, wherein the protection structure comprises: a first protective layer and a second protective layer positioned on the side wall of the first protective layer; and removing part of the initial isolation layer by adopting an etching process to form an isolation layer, wherein the surface of the isolation layer is lower than the top of the fin part and covers part of the side wall of the fin part, and the etching rate of the first protection layer is lower than that of the second protection layer in the process of etching and removing part of the initial isolation layer. The performance of the formed device is better.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

As the integration level of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as the size of the transistor decreases sharply, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, which makes it more difficult to suppress the short channel effect and increases the channel leakage current of the transistor.

The gate of the Fin Field-Effect Transistor (FinFET) has a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewall of the fin, so that the inversion layer is formed on each side of the channel, and the connection of the circuit can be controlled on both sides of the fin. with disconnect.

In order to further improve the integration of semiconductor devices, one method is to form an isolation structure in the fin, and subsequently form a replacement gate structure on the isolation structure.

However, it is very difficult to form the replacement gate structure.

Contents of the invention

The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to reduce the difficulty of forming a replacement gate structure.

In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate has fins, and the fins include several first regions and are located between adjacent first regions The second region of the fin has an opening in the second region of the fin; an initial isolation layer is formed on the base, the sidewall of the fin and in the opening; the fin portion on both sides of the initial isolation layer and the initial isolation layer A protective structure is formed on the first region, and the protective structure includes: a first protective layer and a second protective layer located on the sidewall of the first protective layer; an etching process is used to remove part of the initial isolation layer to form an isolation layer, and the isolation layer The top surface of the fin is lower than the top surface of the fin and covers part of the sidewall of the fin. During the process of removing part of the initial isolation layer by etching, the rate of etching the first protection layer is lower than the rate of etching the second protection layer. rate.

Optionally, the material of the initial isolation layer includes: silicon oxide.

Optionally, during the process of forming the isolation layer, part of the top of the protection structure is also removed.

Optionally, the process of forming the isolation layer includes: a wet etching process; the parameters of the wet etching process include: the etchant includes a hydrofluoric acid solution, and the mass percentage concentration of the etchant is 0.1% to 1%. .

Optionally, during the process of forming the isolation layer, the etching selectivity ratio of the first protection layer and the second protection layer is: 10:1˜200:1.

Optionally, the thickness of the first protective layer is 2 nanometers to 30 nanometers.

Optionally, the step of forming the protective structure includes: forming a mask layer on the top surface of the initial isolation layer and the fin, the mask layer has a mask opening, and the bottom of the mask opening exposes the initial The isolation layer and the top surface of the first region of the fin portion on both sides of the initial isolation layer; the protective structure is formed in the mask opening.

Optionally, along the extending direction of the fin, the size of the mask opening is 32 nm to 80 nm.

Optionally, the material of the mask layer includes: amorphous silicon, titanium nitride or silicon nitride.

Optionally, when the material of the mask layer includes amorphous silicon or titanium nitride, the material of the first protective layer includes: silicon nitride, silicon oxynitride, silicon carbonitride or silicon boride; The material of the second protection layer includes: silicon oxide.

Optionally, when the material of the mask layer is silicon nitride, the material of the first protective layer includes silicon oxide, and there are dopant ions in the first protective layer, and the dopant ions include silicon ions or Nitrogen ions; the material of the second protective layer includes silicon oxide.

Optionally, when the dopant ions are silicon ions, the atomic percentage concentration of the dopant ions in the first protection layer is: 34%˜50%.

Optionally, when the dopant ions are nitrogen ions, the atomic percentage concentration of the dopant ions in the first protective layer is: 10%-25%.

Optionally, the process of doping the dopant ions in the first protection layer includes: an ion implantation process.

Optionally, the parameters of the ion implantation process include: when the dopant ions are silicon, the implantation energy is 1 keV to 20 keV, and the implantation dose is 1.0E14atm/cm ² to 1.0E20atm/cm ² , The injection angle ranges from 0° to 45°.

Optionally, during the process of forming the first protection layer, after the ion implantation process, the method further includes: annealing the first protection layer.

Optionally, the parameters of the annealing process include: a temperature of 800°C to 1100°C, and a time of 0 seconds to 100 seconds.

Optionally, after forming the isolation layer, it further includes: forming a replacement gate structure on the protection structure; forming a gate structure spanning part of the first region of the fin; forming the gate structure and the replacement gate structure. After the gate structure, an epitaxial layer is formed in the first region of the fin adjacent to both sides of the gate structure, and the epitaxial layer covers a part of the sidewall of the replacement gate structure.

Optionally, the step of forming the epitaxial layer includes: using the gate structure and the replacement gate structure as a mask, forming source and drain openings in the first regions of the fins on both sides of the gate structure, the Both the sidewall and the bottom of the source and drain opening expose the base; the epitaxial layer is formed in the source and drain opening; the material of the base includes: silicon, and the forming process of the epitaxial layer includes an epitaxial growth process.

Correspondingly, the present invention also provides a semiconductor structure formed by the above-mentioned method, including: a substrate having fins on the substrate, the fins including several first regions and adjacent first regions In the second area, there is an opening in the second area of the fin; there is an initial isolation layer in the opening, and a protective structure is provided on the initial isolation layer, and the protective structure includes: a first protective layer and a protective structure located on the first protective layer. A second protection layer for sidewalls; an isolation layer is provided on the substrate, the top surface of the isolation layer is lower than the top surface of the fin and covers part of the sidewall of the fin.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, part of the initial isolation layer is removed to form the isolation layer. During the removal of part of the initial isolation layer, part of the top of the protective structure is also removed. Since the protection structure includes: a first protection layer and a second protection layer located on the sidewall of the first protection layer, during the process of removing part of the initial isolation layer, the top and part of the sides of the first protection layer Both walls are etched, while only the top surface of the second protective layer is etched. In the process of removing part of the initial isolation layer, since the removal rate of the first protection layer is lower than that of the second protection layer, the first protection layer can reduce the removal rate of the top edge region of the protection structure and the removal rate of the middle region of the protection structure. The difference in speed makes the top surface of the protection structure relatively flat after the formation of the isolation layer, so that the subsequent replacement gate structure formed on the protection structure is not easy to fall.

Further, the replacement gate structure is located on the initial isolation layer and the first region of the fin portion on both sides of the initial isolation layer. When the epitaxial layer is subsequently formed in the first region of the fin portion on both sides of the gate structure, the replacement gate structure is used to limit the growth space of the epitaxial layer and avoid bridging between adjacent epitaxial layers.

Description of drawings

1 to 3 are structural schematic diagrams of the formation process of a semiconductor structure;

4 to 15 are structural schematic diagrams of the formation process of the semiconductor structure in the first embodiment of the present invention.

Detailed ways

There are many problems in the method of forming the semiconductor structure, for example, it is difficult to form the replacement gate structure.

In combination with a method for forming a semiconductor structure, the reason why it is difficult to form a replacement gate structure formed by the method is analyzed:

1 to 3 are structural schematic diagrams of steps in a method for forming a semiconductor structure.

Referring to FIG. 1 , a base (not shown) is provided on which a fin 100 is provided, and the fin 100 includes a plurality of first regions A and second regions B between adjacent first regions A. , there is an opening (not shown in the figure) in the second region B of the fin portion 100; an initial isolation layer 101 is formed in the base, the sidewall of the fin portion 100, and the opening, and the top surface of the initial isolation layer 101 Exposing the top surface of the fin portion 100; forming a mask layer 102 on the initial isolation layer 101, the mask layer 102 has a mask opening 103, and the bottom of the mask opening 103 exposes the initial isolation layer 101 and Part of the top surface of the first region A of the fin portion 100 on both sides of the initial isolation layer 101 .

Please refer to FIG. 2 , an initial protection structure 104 is formed in the mask opening 103 (see FIG. 1 ); after the initial protection structure 104 is formed, the mask layer 102 is removed to expose the top surface of the first region A of the fin portion 100 And part of the top surface of the initial isolation layer 101 .

Please refer to FIG. 3 , after removing the mask layer 102 , remove part of the initial isolation layer 101 to form an isolation layer 105 , the top surface of the isolation layer 105 is lower than the top surface of the fin 100 and covers part of the fin 100 side wall.

However, the performance of semiconductor devices prepared by the above method is poor because of:

In the above method, the material of the initial isolation layer 101 includes: silicon oxide, the formation process of the isolation layer 105 includes: a wet etching process, and the parameters of the wet etching process include: the etchant includes hydrogen fluoride acid solution. Since the material of the protection structure 104 includes silicon oxide, part of the top of the initial protection structure 104 is also removed during the process of removing part of the initial isolation layer 101 by using a wet etching process.

Specifically, during the process of removing part of the initial isolation layer 101 , the removed top portion of the initial protection structure 104 includes: the top edge region 1 of the initial protection structure 104 and the top middle region 2 of the initial protection structure 104 . The removal rate of the top edge region 1 of the initial protection structure 104 includes: the first etching rate of the sidewall of the top edge region 1 of the initial protection structure 104 and the second etching rate of the top of the top edge region 1 of the initial protection structure 104, and The top middle region 2 of the initial protection structure 104 has only the third etch rate. Since the initial protection structure 104 is a single-layer structure, the material of the initial protection structure 104 includes: silicon oxide, therefore, the first etching rate, the second etching rate and the third etching rate are all the same, so that the The etching rate of the top edge region 1 of the initial protection structure 104 is greater than that of the middle region 2 at the top of the initial protection structure 104. With the accumulation of etching time, the removal amount of the top edge region 1 of the initial protection structure 104 is greater than that of the initial protection structure 104. Removal of top middle zone 2. That is: after the isolation layer 105 is formed, the top surface of the formed protection structure 106 is convex.

After the isolation layer 105 is formed, a replacement gate structure is formed on the top surface of the protection structure 106 . Since the etchant makes the top surface of the protection structure 106 convex, the replacement gate structure formed on the protection structure 106 tends to fall to the depression at the top of the gate structure 106, so that the replacement gate structure The bottom surface of the fin portion 100 on both sides of the initial isolation layer 101 cannot cover the top surface of the first region A of the fin portion 100 .

A gate structure is subsequently formed across the first region A of the fin portion 100 . Using the gate structure and the replacement gate structure as a mask, an epitaxial layer is formed in the first region A of the fin portion 100 on both sides of the gate structure. The step of forming the epitaxial layer includes: using the gate structure and the replacement gate structure as a mask, forming source and drain openings in the first region A of the fin portion 100 on both sides of the gate structure; grow to form an epitaxial layer. Since the bottom surface of the replacement gate structure cannot cover the top surface of the first region A of the fin 100 on both sides of the initial isolation layer 101, using the gate structure and the replacement gate structure as a mask, the two sides of the gate structure The sidewalls of the source and drain openings formed in the first region A of the fin portion 100 expose the sidewalls of the initial isolation layer 101 in the opening, and the initial isolation layer 101 cannot provide a silicon source for the subsequent epitaxial growth to form an epitaxial layer, so that the formed The morphology of the epitaxial layer is poor, which is not conducive to improving the performance of semiconductor devices.

To solve the technical problem, the present invention provides a method for forming a semiconductor structure, by forming a protective structure on the initial isolation layer and the first region of the fin part on both sides of the initial isolation layer, the protective structure comprising: The first protective layer and the second protective layer positioned at the sidewall of the first protective layer, the first protective layer has dopant ions; in the etching process for forming the isolation layer, the removal rate of the first protective layer is less than The removal rate of the second protective layer. The method makes the subsequent replacement gate structure formed on the protection structure less prone to tipping.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

4 to 15 are structural schematic diagrams of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to FIG. 4 , an initial substrate 200 is provided, the initial substrate 200 has a first oxide layer 201 thereon, and the first oxide layer 201 has a first mask layer 202 thereon.

In this embodiment, the material of the initial substrate 200 is silicon. In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon-on-insulator, or germanium-on-insulator.

In this embodiment, the material of the first oxide layer 201 includes silicon oxide, and the formation process of the first oxide layer 201 includes: a fluid chemical vapor deposition process. The first oxide layer 201 is used as a buffer layer between the initial substrate 200 and the first mask layer subsequently formed on the first oxide layer 201 . In other embodiments, only the first masking layer is present on the initial substrate.

The material of the first mask layer 202 includes: silicon nitride, amorphous silicon or titanium nitride, and the first mask layer 202 is used as a mask for subsequent formation of the base and fins.

Please refer to FIG. 5 and FIG. 6, FIG. 6 is a schematic cross-sectional view of FIG. 5 along AA1, and FIG. 5 is a schematic cross-sectional view of FIG. 6 along line BB1, patterning the first mask layer 202; The layer 202 is a mask, and the initial substrate 200 is etched to form a substrate 203 and a fin 204 on the substrate 203. The fin 204 includes a plurality of first regions I and a first region I between adjacent first regions I. Second region II, the fin portion 204 has an opening 205 (not shown) that runs through the second region II; a second oxide layer is formed on the substrate 203, the sidewall and top surface of the fin portion 204, and the opening 205 223.

In this embodiment, the material of the initial substrate 200 is silicon. Correspondingly, the material of the base 203 is silicon, and the material of the fins 204 is silicon. In other embodiments, the material of the substrate includes: germanium substrate, silicon germanium substrate, silicon-on-insulator or germanium-on-insulator. The material of the fin includes: germanium substrate, silicon germanium substrate, silicon on insulator or germanium on insulator.

The base 203 has a plurality of fins 204 arranged along a direction perpendicular to the extension of the fins 204 . In this embodiment, the number of the fins 204 is: 4, and in other embodiments, the number of the fins is 1-3; or, the number of the fins is: 4 or more.

A gate structure across the first region I of the fin portion 204 is subsequently formed.

The opening 205 is used for subsequent accommodation of the initial isolation layer.

Subsequently, a replacement gate structure is formed on the initial isolation layer and the top surface of the first region I of the fin portion 204 on both sides of the initial isolation layer.

Along the extending direction of the fin portion 204 , the size of the opening 205 is 20 nm˜50 nm.

The top surface of the fin portion 204 has a portion of the first oxide layer 201 and a first mask layer 202 on the first oxide layer 201 .

The material of the second oxide layer 223 includes: silicon oxide, and the formation process of the second oxide layer 223 includes: a fluid chemical vapor deposition process.

The second oxide layer 223 is used to protect the base 203 and the fins 204 when an initial isolation material film is subsequently formed.

In other embodiments, the second oxide layer is not formed after the base and the fins are formed.

Referring to FIG. 7 , an initial isolation material film 206 is formed on the second oxide layer 223 .

It should be noted that FIG. 7 is a schematic structural diagram based on FIG. 6 .

The initial isolation material film 206 is used for subsequent formation of an isolation layer.

The initial isolation material film 206 is located on the base 203 , the sidewalls and top surfaces of the fins 204 and within the opening 205 (see FIG. 6 ).

In this embodiment, the material of the initial isolation material film 206 is silicon oxide. In other embodiments, the material of the initial isolation material film includes: silicon oxynitride.

In this embodiment, the forming process of the initial isolation material film 206 includes: a fluid chemical vapor deposition process.

The initial isolation material film 206 formed by the fluid chemical vapor deposition process has a strong ability to fill the opening 205 and the gap between adjacent fins 204 , and the formed initial isolation material film 206 has good isolation performance.

In the process of forming the initial isolation material film 206, the second oxide layer 223 protects the base 203 and the fins 204, so that the damage to the base 203 and the fins 204 is small, which is beneficial to improve the performance of the semiconductor device .

Referring to FIG. 8, part of the initial isolation material film 206, the second oxide layer 223 (see FIG. 7), the first mask layer 202 (see FIG. 7) and the first oxide layer 201 (see FIG. 7 ), until the top surface of the fin portion 204 is exposed, an initial isolation layer 207 is formed.

The process of removing part of the initial isolation material film 206 , the second oxide layer on the fin portion 204 , the first mask layer 202 and the first oxide layer 201 includes: a chemical mechanical polishing process.

The initial isolation layer 207 is used for subsequent formation of isolation layers.

In this embodiment, after the initial isolation layer 207 is formed, a third oxide layer is formed on the initial isolation layer 207 and the top surfaces of the fins 204 . Please refer to Figure 9 for details.

In other embodiments, the third oxide layer is not formed after the initial isolation layer is formed.

Referring to FIG. 9 , a third oxide layer 208 is formed on the initial isolation layer 207 and the top surfaces of the fins 204 .

The material of the third oxide layer 208 includes: silicon oxide, and the formation process of the third oxide layer 208 includes: a fluid chemical vapor deposition process.

The third oxide layer 208 serves as a buffer layer between the initial isolation layer 207 , the fin portion 204 and the subsequent mask layer formed on the initial isolation layer 207 and the fin portion 204 .

After forming the initial isolation layer 207, a protective structure is formed on the initial isolation layer 207 and the first region I of the fins 204 on both sides of the initial isolation layer 207. Before forming the protective structure, it also includes: A mask layer is formed on the trioxide layer 208 , please refer to FIG. 10 for details.

Referring to FIG. 10, a mask layer 209 is formed on the third oxide layer 208, the mask layer 209 has a mask opening 210, and the bottom of the mask opening 210 exposes the opening 205 (as shown in FIG. 6 ) the initial isolation layer 207 and the top surface of the third oxide layer 208 on the part of the first region I of the fin portion 204 adjacent to the initial isolation layer 207 on both sides of the opening 205 .

In this embodiment, the material of the mask layer 209 includes: silicon nitride. In other embodiments, the material of the mask layer includes: amorphous silicon or titanium nitride.

The mask opening 210 is used for subsequently accommodating protective structures.

The size of the mask opening 210 along the extending direction of the fin portion 204 is: 32 nm˜80 nm. The significance of selecting the size of the mask opening 210 along the extending direction of the fin portion 204 is: if the size of the mask opening 210 along the extending direction of the fin portion 204 is smaller than 32 nanometers, so that the subsequently formed mask opening 210 The size of the protective structure along the extending direction of the fin 204 is too small, so that the bottom of the protective structure covers the third oxide layer on the first region I of the fin 204 on both sides of the initial isolation layer 207 in the opening 205 along the extending direction of the fin 204 The size of 208 is too small, which is not conducive to the subsequent formation of an epitaxial layer with good morphology; The size in the extending direction of the fin portion 204 is too large, which is not conducive to improving the integration of the device.

The bottom of the mask opening 210 exposes the top surface of the third oxide layer 208 on the initial isolation layer 207 in the opening 205. layer 207, so that when part of the initial isolation layer 207 is subsequently removed, the protection structure can protect the initial isolation layer 207 in the opening 205 from being removed.

The bottom of the mask opening 210 exposes the top surface of the third mask layer 208 on part of the first region I of the fins 204 on both sides of the initial isolation layer 207 in the opening 205. The protection structure formed in 210 is also located on the first region I of the fin portion 204 on both sides of the initial isolation layer 207 in the opening 205, which is conducive to the subsequent formation of an epitaxial layer with good morphology.

Subsequently, a protective structure is formed in the mask opening 210 , the protective structure includes: a first protective layer and a second protective layer located on a sidewall of the first protective layer. Since the mask layer 209 needs to be removed after the protective structure is formed, the material of the mask layer 209 is different from that of the first protective layer, so that when the mask layer 209 is removed, the first protective layer are not removed. The first protection layer is used to slow down the difference between the removal rate of the top edge region of the protection structure and the removal rate of the middle region of the protection structure, so that after the subsequent formation of the isolation layer, the top surface of the protection structure is still flat, which is conducive to subsequent A replacement gate structure is formed on the protection structure.

Referring to FIG. 11 , a first protective film 211 is formed on the mask layer 209 , on the sidewall and bottom surface of the mask opening 210 .

In this implementation, the material of the mask layer 209 is silicon nitride, and when the material of the first protective film 211 is silicon oxide, the first protective film 211 can have a higher etching rate than the mask layer 209. Selectivity, so that when the mask layer 209 is subsequently removed, the first protection layer 211 is not removed. In other embodiments, the material of the mask layer includes: amorphous silicon or titanium nitride, and the material of the first protective film includes: silicon nitride, silicon oxynitride, silicon carbonitride, or silicon boride When , it is possible to make the first protective film have a higher etching selectivity ratio relative to the mask layer, so that when the mask layer is subsequently removed, the first protective layer will not be removed.

In this embodiment, the formation process of the first protective film 211 includes: a chemical vapor deposition process, the parameters of the chemical vapor deposition process include: the reactants include a silicon source and an oxygen source gas, and the silicon source includes ethyl orthosilicate Esters, the oxygen source gas includes oxygen, the flow rate of the oxygen source gas is 100 standard milliliters per minute to 8000 standard milliliters per minute, the temperature is 300 degrees Celsius to 500 degrees Celsius, the pressure is 3 Torr to 200 Torr, and the time is 20 seconds to 10000 Second.

In other embodiments, the formation process of the first protective film includes: an atomic layer deposition process; the parameters of the atomic layer deposition process include: reactants include: silicon precursors and oxygen precursors, and the temperature is 80 degrees Celsius to 300 degrees Celsius Celsius, the pressure is 5 mTorr to 20 Torr, and the number of cycles is 5 to 500 times.

The thickness of the first protection film 211 is: 2 nanometers to 30 nanometers. The significance of selecting the thickness of the first protective film 211 is: if the thickness of the first protective film 211 is less than 2 nanometers, the thickness of the first protective layer formed subsequently is less than 2 nanometers, so that when the isolation layer is formed subsequently, the first The ability of the protection layer to slow down the removal rate of the top edge region of the protection structure is insufficient, so that after the formation of the isolation layer, the top surface of the protection structure is still convex, and the subsequent formation of a replacement gate structure on the protection structure is prone to dumping; if The thickness of the first protection film 211 is greater than 30 nanometers. In order to prevent the top surface of the protection structure from being convex, it is necessary to increase the implantation energy of the subsequent ion implantation process, which increases the difficulty of the process.

Referring to FIG. 12 , an ion implantation process is performed on the surface of the first protection film 211 to form a first protection layer 212 with dopant ions in the first protection layer 212 .

In this embodiment, the parameters of the ion implantation process include: the dopant ions are silicon ions, the implantation energy is 1 keV to 20 keV, and the implantation dose is 1.0E14atm/cm ² to 1.0E20atm/cm ^2. The injection angle is from 0° to 45°.

The significance of selecting the implant dose is: if the implant dose is less than 1.0E14 atm/cm ² , in the subsequent process of forming the isolation layer, the first protective layer 212 is used to weaken the removal rate of the top edge region of the protective structure. The ability is weak, so that after the formation of the isolation layer, the top surface of the protection structure is convex, and the subsequent replacement gate structure formed on the protection structure is prone to dumping; if the implantation dose is greater than 1.0E20atm/cm ² , the In the subsequent process of forming the isolation layer, the removal rate of the first protection layer 212 along the extending direction of the fin 204 is too slow, so that after the isolation layer is formed, the top surface of the protection structure is still uneven, so that the subsequent protection structure on the protection structure The formed replacement gate structure is also prone to dumping.

In this embodiment, when the dopant ions are: silicon ions, the atomic percentage concentration of the dopant ions in the first protective layer 212 is: 34% to 50%. The significance of the atomic percentage concentration of hetero ions is: if the atomic percentage concentration of the dopant ions in the first protective layer 212 is less than 34%, the first protective layer 212 can reduce the top of the protective structure when the isolation layer is subsequently formed. The ability of the removal rate of the edge region is weak, so that the removal rate of the edge region of the top of the protection structure is still greater than the removal rate of the middle region of the top of the protection structure, so that after the isolation layer is formed, the top of the protection structure is convex, which is not conducive to subsequent A replacement gate structure is formed on the protection structure; if the atomic percent concentration of dopant ions in the first protection layer 212 is greater than 50%, it is difficult to dope ions in the first protection layer 212 .

In other embodiments, when the dopant ions are nitrogen ions, the atomic percentage concentration of the dopant ions in the first protection layer is: 10%˜25%.

In this embodiment, after the ion implantation process, an annealing process is performed on the first protective film 211 . In other embodiments, after the ion implantation process, the first protection film is not annealed.

In this embodiment, the meaning of annealing the first protective film 211 is to diffuse dopant ions into the first protective film 211 . The parameters of the annealing process include: the temperature is 800 degrees Celsius to 1100 degrees Celsius, and the time is 0 seconds to 100 seconds.

Subsequently, a second protection layer is formed on the sidewall of the first protection layer 212 . In this embodiment, the material of the second protective layer is silicon oxide, the material of the first protective layer 212 is silicon oxide, and the first protective layer 212 has dopant ions, so that the subsequent removal of part of the initial isolation layer When , the removal rate of the first protection layer 212 is smaller than the removal rate of the second protection layer. In other embodiments, the material of the second protective layer is silicon oxide, the material of the first protective film is silicon nitride, silicon oxynitride, silicon carbonitride or silicon boride, and then the removal part is initially When the isolation layer is used, the removal rate of the first protective film is lower than that of the second protective layer. Therefore, there is no need to perform an ion implantation process on the first protective film, and the first protective film is the first protective layer.

The first protection layer 212 and the subsequently formed second protection layer are used as protection structures.

Referring to FIG. 13 , a second protection film 213 is formed on the first protection layer 212 .

The material of the second protective film 213 includes silicon oxide.

In this embodiment, the formation process of the second protective film 213 includes: a fluid chemical vapor deposition process, the parameters of the fluid chemical vapor deposition process include: the reactants include a silicon source gas and an oxygen source gas, and the silicon source gas includes N(SIH ₃ ) ₃ , the oxygen source gas includes oxygen, the flow rate of the silicon source gas is 20 standard ml/min to 10,000 standard ml/min, the catalytic gas includes ammonia, the temperature is 30 degrees Celsius to 90 degrees Celsius, and the pressure is 0.01 Support ~ 10 support. In other embodiments, the forming process of the second protective film includes: a plasma chemical vapor deposition process.

The second protection film 213 is used for subsequent formation of a second protection layer.

Referring to FIG. 14, the second protective film 213 is planarized until the top surface of the mask layer 209 (see FIG. 13) is exposed, and a second protective layer 214 is formed in the mask opening 210 (see FIG. 10). After forming the second protective layer 214, remove the second mask layer 209, exposing the top surface of the third oxide layer 208 on the first region I of the fin portion 204 and the initial isolation layer 207.

The process of planarizing the second protection film 213 includes: a chemical mechanical polishing process.

During the process of forming the second protection layer 214 , both the first protection layer 212 and the second protection film 213 located on the top surface of the mask layer 209 are removed.

The process of removing the second mask layer 209 includes: a dry etching process or a wet etching process.

The protection structure includes: a first protection layer 212 located on the sidewall and bottom of the mask opening 210 (see FIG. 10 ), and a second protection layer 214 located on the first protection layer 212 .

The protection structure is used to protect the initial isolation layer 207 inside the opening 205 .

A replacement gate structure is subsequently formed on the protection structure.

Referring to FIG. 15 , the third oxide layer 208 on the first region I of the fin portion 204 and the initial isolation layer 207 is removed; after removing the third oxide layer 208 , part of the initial isolation layer 207 is removed to form an isolation layer 215 , The top surface of the isolation layer 215 is lower than the top surface of the fin 204 and covers part of the sidewall of the fin 204 .

The process of forming the isolation layer 215 includes: a wet etching process; the parameters of the wet etching process include: the etchant includes hydrofluoric acid solution, and the mass percentage concentration of the etchant is 0.1%˜1%.

During the formation of the isolation layer 215, part of the top of the protective structure is also removed by the etchant. The protection structure includes: a first protection layer 212 and a second protection layer 214 located on a sidewall of the first protection layer 212 .

In this embodiment, the material of the first protective layer 212 is silicon oxide, the material of the second protective layer 214 is silicon oxide, and the first protective layer 212 contains dopant ions, so that the first protective layer The atomic percentage concentration of oxygen in the layer 212 is less than the atomic percentage concentration of oxygen in the second protective layer 214, so that in the process of removing part of the initial isolation layer 207, the corrosion resistance of the first protective layer 212 is lower than that of the second protective layer 214. Strong corrosion resistance, that is, the first protection layer 212 and the second protection layer 214 have different etching selectivity ratios, and the removal rate of the first protection layer 212 is lower than the removal rate of the second protection layer 214 .

In this embodiment, during the process of forming the isolation layer 215 , the etching selectivity ratio between the first protection layer 212 and the second protection layer is: 10:1˜200:1.

The meaning of selecting the etching selectivity ratio of the first protection layer 212 and the second protection layer 214 is: if the etching selectivity ratio of the first protection layer 212 and the second protection layer is less than 10:1, so that when forming the isolation In the process of forming the isolation layer 215, the ability of the first protection layer 212 to weaken the removal rate of the top edge region of the protection structure is too small, so that in the process of forming the isolation layer 215, the removal rate of the top edge region of the protection structure is still Greater than the removal rate of the middle region of the protective structure, so that after the formation of the isolation layer 215, the top of the protective structure is convex, so that the subsequent formation of a replacement gate structure on the protective structure is prone to dumping; if the first protective layer 212 and the second The etch selectivity ratio of the protective layer is greater than 200:1, so that in the process of forming the isolation layer 215, the first protective layer 212 is more difficult to be removed, so that after the isolation layer 215 is formed, the top of the protective structure is still uneven, so that Subsequent formation of a replacement gate structure on the protection structure is prone to tipping.

The protective structure includes: a first protective layer 212 and a second protective layer 214 located on the sidewall of the first protective layer 212, therefore, during the process of removing part of the initial isolation layer 207, the sidewall of the first protective layer 212 and the top are etched, while only the top surface of the second protection layer 214 is etched. In the process of removing part of the initial isolation layer 207, since the removal rate of the first protection layer 212 is lower than the removal rate of the second protection layer 214, the first protection layer 212 can reduce the removal rate and protection of the top edge region 11 of the protection structure. The difference in the removal rate of the middle region 12 on the top of the structure makes the top surface of the protection structure relatively flat after the formation of the isolation layer 215 , so that the subsequent replacement gate structure formed on the protection structure is not prone to tipping.

After forming the isolation layer 215, it also includes: forming a replacement gate structure on the protection structure, the replacement gate structure is located in the initial isolation layer 207 in the opening 205 and the fins on both sides of the initial isolation layer 207 in the opening 205 Part 204 part of the first region I; form a gate structure across part of the first region I of the fin part 204; after forming the gate structure and the replacement gate structure, the fins on both sides of the gate structure An epitaxial layer is formed in the first region I of the portion 204, and the epitaxial layer covers part of the sidewall of the replacement gate structure.

The step of forming the epitaxial layer includes: using the gate structure and the replacement gate structure as a mask, forming source and drain openings in the first region I of the fin portion 204 on both sides of the gate structure; The epitaxial layer is formed in the drain opening.

The forming process of the epitaxial layer includes an epitaxial growth process.

When forming the epitaxial layer, the replacement gate structure is used to limit the growth space of the epitaxial layer and avoid bridging between adjacent epitaxial layers. Correspondingly, the present invention also provides a semiconductor structure formed by the above method.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above method, please refer to FIG. 15 , including:

A base 203 with a fin 204 on the base 203, the fin 204 includes several first regions I and second regions II located between adjacent first regions I, the second region II of the fin 204 There is an opening 205 inside (see Figure 6);

The opening 205 has an initial isolation layer 207 (see FIG. 8 ), and the initial isolation layer 207 has a protection structure on it, and the protection structure includes: a first protection layer 212 and a second protection layer located on the side wall of the first protection layer 212 protect 214;

An isolation layer 215 is formed on the base 203 . The top surface of the isolation layer 215 is lower than the top surface of the fin portion 204 and covers part of the sidewall of the fin portion 204 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and the second areas of the fin part are provided with openings;

forming an initial isolation layer on the substrate, on the side wall of the fin part and in the opening;

forming a protection structure on the initial isolation layer and the first areas of fin parts on two sides of the initial isolation layer, wherein the protection structure comprises: the first protective layer and the second protective layer are positioned on the side wall of the first protective layer; the first protective layer is positioned at the top edge area of the protective structure, and the second protective layer is positioned at the top middle area of the protective structure; the protection structure covers the opening and the junction of the opening and the fin part;

and removing part of the initial isolation layer by adopting an etching process to form an isolation layer, wherein the top surface of the isolation layer is lower than the top surface of the fin part and covers part of the side wall of the fin part, and the etching rate of the first protection layer is lower than the etching rate of the second protection layer in the process of removing part of the initial isolation layer by etching.

2. The method of forming a semiconductor structure of claim 1, wherein the material of the initial isolation layer comprises: and (3) silicon oxide.

3. The method of forming a semiconductor structure of claim 1, wherein a portion of the top of the guard structure is removed during etching to remove a portion of the initial isolation layer.

4. The method of forming a semiconductor structure of claim 2, wherein the process of forming the isolation layer comprises: wet etching process; the parameters of the wet etching process include: the etchant comprises hydrofluoric acid solution, and the mass percentage concentration of the etchant is 0.1% -1%.

5. The method of forming a semiconductor structure of claim 1, wherein in forming said isolation layer, an etch selectivity of the first protective layer and the second protective layer is: 10:1 to 200:1.

6. the method of forming a semiconductor structure of claim 1, wherein the first protective layer has a thickness of: 2 nm-30 nm.

7. The method of forming a semiconductor structure of claim 1, wherein the step of forming a protective structure comprises: forming a mask layer on the initial isolation layer and the fin part, wherein the mask layer is provided with a mask opening, and the bottoms of the mask openings expose the top surfaces of the first areas of the fin part parts on two sides of the initial isolation layer and the initial isolation layer; and forming the protection structure in the mask opening.

8. The method of claim 7, wherein the mask opening has a dimension along the fin extension of: 32 nm-80 nm.

9. The method of forming a semiconductor structure of claim 7, wherein the material of the mask layer comprises: amorphous silicon, titanium nitride or silicon nitride.

10. The method of forming a semiconductor structure of claim 9, wherein when the material of the mask layer comprises amorphous silicon or titanium nitride, the material of the first protective layer comprises: silicon nitride, silicon oxynitride, silicon carbonitride or silicon nitride boride; the material of the second protective layer includes: and (3) silicon oxide.

11. The method of claim 9, wherein when the mask layer is silicon nitride, the first protective layer comprises silicon oxide, and the first protective layer has doped ions therein, wherein the doped ions comprise silicon ions or nitrogen ions; the material of the second protective layer includes silicon oxide.

12. The method of claim 11, wherein when the dopant ions are silicon ions, the concentration of the dopant ions in the first protective layer in atomic percent is: 34% -50%.

13. The method of claim 11, wherein when the dopant ions are nitrogen ions, the concentration of the dopant ions in the first protective layer is: 10% -25%.

14. The method of claim 11, wherein the process of doping the dopant ions into the first protective layer comprises: and (5) an ion implantation process.

15. The method of forming a semiconductor structure of claim 14, wherein the parameters of the ion implantation process comprise: when the doped ion is silicon, the implantation energy is 1 kiloelectron volt-20 kiloelectron volts, and the implantation dosage is 1.0E14atm/cm ² ～1.0E20atm/cm ² The injection angle is 0-45 degrees.

16. The method of forming a semiconductor structure of claim 14, wherein during forming said first protective layer, after said ion implantation process, further comprising: and annealing the first protective layer.

17. The method of forming a semiconductor structure of claim 16, wherein the parameters of the annealing process comprise: the temperature is 800-1100 ℃ and the time is 0-100 seconds.

18. The method of forming a semiconductor structure of claim 1, further comprising, after forming the isolation layer: forming a replacement gate structure on the protection structure, wherein the replacement gate structure is positioned on the initial isolation layer and the first areas of the fin parts at two sides of the initial isolation layer; forming a grid structure crossing part of the first region of the fin part; after the gate structure and the replacement gate structure are formed, an epitaxial layer is formed in the first region of the fin portions on two sides of the gate structure, and the epitaxial layer covers part of the side wall of the replacement gate structure.

19. The method of forming a semiconductor structure of claim 18, wherein the step of forming an epitaxial layer comprises: forming source and drain openings in the first areas of the fin parts at two sides of the gate structure by taking the gate structure and the replacement gate structure as masks, wherein the side walls and the bottoms of the source and drain openings are exposed out of the substrate; forming the epitaxial layer in the source drain opening; the material of the substrate comprises: silicon; the epitaxial layer forming process comprises an epitaxial growth process.

20. A semiconductor structure formed by the method of any of claims 1 to 19, comprising:

the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and openings are formed in the second areas of the fin part;

the opening is internally provided with an initial isolation layer, the initial isolation layer is provided with a protection structure, and the protection structure comprises: the first protective layer and the second protective layer are positioned on the side wall of the first protective layer; the first protective layer is positioned at the top edge area of the protective structure, and the second protective layer is positioned at the top middle area of the protective structure; the protection structure covers the opening and the junction of the opening and the fin part;

the substrate is provided with an isolation layer, the top surface of the isolation layer is lower than the top surface of the fin portion, and part of the side wall of the fin portion is covered.

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