CN109148370B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN109148370B
CN109148370B CN201710442424.7A CN201710442424A CN109148370B CN 109148370 B CN109148370 B CN 109148370B CN 201710442424 A CN201710442424 A CN 201710442424A CN 109148370 B CN109148370 B CN 109148370B
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layer
forming
fin
isolation layer
protection
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CN109148370A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and openings are formed in the second areas of the fin part; forming an initial isolation layer on the substrate, on the side wall of the fin part and in the opening; forming a protection structure on the initial isolation layer and the first areas of the fin parts on two sides of the initial isolation layer, wherein the protection structure comprises: a first protective layer and a second protective layer positioned on the side wall of the first protective layer; and removing part of the initial isolation layer by adopting an etching process to form an isolation layer, wherein the surface of the isolation layer is lower than the top of the fin part and covers part of the side wall of the fin part, and the etching rate of the first protection layer is lower than that of the second protection layer in the process of etching and removing part of the initial isolation layer. The performance of the formed device is better.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the increase in the integration level of semiconductor devices, the critical dimensions of transistors are continually shrinking. However, as the transistor size is rapidly reduced, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gates of Fin Field effect transistors (Fin Field-Effect Transistor, finFETs) are in a fork-like 3D architecture resembling a fish Fin. The channel of the FinFET protrudes out of the surface of the substrate to form a fin portion, and the grid electrode covers the top surface and the side wall of the fin portion, so that inversion layers are formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin portion.
To further increase the integration of the semiconductor device, one approach is to form isolation structures within the fin, and subsequently form replacement gate structures over the isolation structures.
However, the difficulty of forming the replacement gate structure is greater.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure to reduce the difficulty of forming a replacement gate structure.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and an opening is formed in the second areas of the fin part; forming an initial isolation layer on the substrate, on the side wall of the fin part and in the opening; forming a protection structure on the initial isolation layer and the first areas of fin parts at two sides of the initial isolation layer, wherein the protection structure comprises: the first protective layer and the second protective layer are positioned on the side wall of the first protective layer; and removing part of the initial isolation layer by adopting an etching process to form an isolation layer, wherein the top surface of the isolation layer is lower than the top surface of the fin part and covers part of the side wall of the fin part, and the etching rate of the first protection layer is lower than the etching rate of the second protection layer in the process of removing part of the initial isolation layer by etching.
Optionally, the material of the initial isolation layer includes: and (3) silicon oxide.
Optionally, the top of a portion of the protective structure is also removed during the formation of the isolation layer.
Optionally, the process of forming the isolation layer includes: wet etching process; the parameters of the wet etching process include: the etchant comprises hydrofluoric acid solution, and the mass percentage concentration of the etchant is 0.1% -1%.
Optionally, in the process of forming the isolation layer, an etching selection ratio of the first protection layer to the second protection layer is: 10:1 to 200:1.
optionally, the thickness of the first protective layer is: 2 nm-30 nm.
Optionally, the step of forming the protection structure includes: forming a mask layer on the top surfaces of the initial isolation layer and the fin part, wherein the mask layer is provided with a mask opening, and the bottom of the mask opening exposes the top surfaces of the initial isolation layer and the first areas of the fin part on two sides of the initial isolation layer; and forming the protection structure in the mask opening.
Optionally, in the extending direction of the fin portion, the size of the mask opening is: 32 nm-80 nm.
Optionally, the material of the mask layer includes: amorphous silicon, titanium nitride or silicon nitride.
Optionally, when the material of the mask layer includes amorphous silicon or titanium nitride, the material of the first protection layer includes: silicon nitride, silicon oxynitride, silicon carbonitride or silicon nitride boride; the material of the second protective layer includes: and (3) silicon oxide.
Optionally, when the material of the mask layer is silicon nitride, the material of the first protection layer includes silicon oxide, and the first protection layer has doped ions therein, where the doped ions include silicon ions or nitrogen ions; the material of the second protective layer includes silicon oxide.
Optionally, when the doped ion is a silicon ion, the concentration of the doped ion in the first protection layer by atomic percentage is: 34% -50%.
Optionally, when the doping ion is a nitrogen ion, the concentration of the doping ion in the first protection layer in atomic percentage is: 10% -25%.
Optionally, the process of doping the doping ions into the first protection layer includes: and (5) an ion implantation process.
Optionally, the parameters of the ion implantation process include: when the doped ion is silicon, the implantation energy is 1 kiloelectron volt-20 kiloelectron volts, and the implantation dosage is 1.0E14atm/cm 2 ～1.0E20atm/cm 2 The injection angle is 0-45 degrees.
Optionally, in the process of forming the first protection layer, after the ion implantation process, the method further includes: and annealing the first protective layer.
Optionally, the parameters of the annealing process include: the temperature is 800-1100 ℃ and the time is 0-100 seconds.
Optionally, after forming the isolation layer, the method further includes: forming a replacement gate structure over the protection structure; forming a grid structure crossing part of the first region of the fin part; after the gate structure and the replacement gate structure are formed, an epitaxial layer is formed in the fin first region adjacent to two sides of the gate structure, and the epitaxial layer covers part of the side wall of the replacement gate structure.
Optionally, the step of forming the epitaxial layer includes: forming source and drain openings in the first areas of the fin parts at two sides of the gate structure by taking the gate structure and the replacement gate structure as masks, wherein the side walls and the bottoms of the source and drain openings are exposed out of the substrate; forming the epitaxial layer in the source drain opening; the material of the substrate comprises: the process of forming the epitaxial layer of silicon comprises an epitaxial growth process.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method, which comprises the following steps: the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and openings are formed in the second areas of the fin part; the opening is internally provided with an initial isolation layer, the initial isolation layer is provided with a protection structure, and the protection structure comprises: a first protective layer and a second protective layer on the side wall of the first protective layer; the substrate is provided with an isolation layer, the top surface of the isolation layer is lower than the top surface of the fin portion, and part of the side wall of the fin portion is covered.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, part of the initial isolation layer is removed, and the isolation layer is formed. During the removal of a portion of the initial isolation layer, a portion of the top of the protective structure is also removed. Since the protection structure includes: the first protective layer and the second protective layer are positioned on the side wall of the first protective layer, so that in the process of removing part of the initial isolation layer, the top and part of the side wall of the first protective layer are etched, and only the top surface of the second protective layer is etched. In the process of removing part of the initial isolation layer, the removal rate of the first protection layer is smaller than that of the second protection layer, so that the difference between the removal rate of the top edge area of the protection structure and the removal rate of the middle area of the protection structure can be reduced by the first protection layer, the top surface of the protection structure is relatively flat after the isolation layer is formed, and the replacement gate structure formed on the protection structure is difficult to topple.
Further, a replacement gate structure is located on the initial isolation layer and the fin portion first region on both sides of the initial isolation layer. And when the epitaxial layer is formed in the first areas of the fin parts at the two sides of the gate structure, the replacement gate structure is used for limiting the growth space of the epitaxial layer and avoiding bridging of adjacent epitaxial layers.
Drawings
Fig. 1-3 are schematic diagrams of a semiconductor structure formation process;
fig. 4 to 15 are schematic structural views of a process of forming a semiconductor structure in the first embodiment of the present invention.
Detailed Description
Methods of forming semiconductor structures have a number of problems, such as: the difficulty of forming the replacement gate structure is greater.
Now, in conjunction with a method for forming a semiconductor structure, the reason why the difficulty of forming a replacement gate structure formed by the method is relatively high is analyzed:
fig. 1 to 3 are schematic structural views illustrating steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate (not shown) is provided, the substrate has a fin portion 100 thereon, the fin portion 100 includes a plurality of first regions a and a second region B located between adjacent first regions a, and an opening (not shown) is formed in the second region B of the fin portion 100; forming an initial isolation layer 101 in the substrate, the side wall of the fin portion 100 and the opening, wherein the top surface of the initial isolation layer 101 exposes the top surface of the fin portion 100; a mask layer 102 is formed on the initial isolation layer 101, the mask layer 102 has a mask opening 103, and the bottom of the mask opening 103 exposes the initial isolation layer 101 and the top surfaces of the first regions a of the fin portions 100 on two sides of the initial isolation layer 101.
Referring to fig. 2, an initial protection structure 104 is formed in the mask opening 103 (see fig. 1); after the initial protection structure 104 is formed, the mask layer 102 is removed, exposing a portion of the top surface of the first region a of the fin 100 and a portion of the top surface of the initial isolation layer 101.
Referring to fig. 3, after removing the mask layer 102, a portion of the initial isolation layer 101 is removed to form an isolation layer 105, where a top surface of the isolation layer 105 is lower than a top surface of the fin 100 and covers a portion of a sidewall of the fin 100.
However, the semiconductor device manufactured by the above method is inferior in performance because:
in the above method, the material of the initial isolation layer 101 includes: silicon oxide, the process of forming the isolation layer 105 includes: the wet etching process comprises the following parameters: the etchant comprises a hydrofluoric acid solution. Since the materials of the protective structure 104 include: silicon oxide, and thus, during the process of removing part of the initial isolation layer 101 by using the wet etching process, part of the top of the initial protection structure 104 is also removed.
Specifically, in the process of removing a portion of the initial isolation layer 101, the portion of the initial protection structure 104 from which the top is removed includes: a top edge region 1 of the initial protective structure 104 and a top intermediate region 2 of the initial protective structure 104. The removal rate of the top edge region 1 of the initial protection structure 104 includes: the first etch rate of the sidewalls of the top edge region 1 of the initial protection structure 104 and the second etch rate of the top edge region 1 of the initial protection structure 104, while the top middle region 2 of the initial protection structure 104 has only the third etch rate. Since the initial protection structure 104 is a single-layer structure, the materials of the initial protection structure 104 include: the silicon oxide, and therefore the first etch rate, the second etch rate, and the third etch rate are all the same, so that the etch rate of the top edge region 1 of the initial protection structure 104 is greater than the removal of the top middle region 2 of the initial protection structure 104, and the removal of the top edge region 1 of the initial protection structure 104 is greater than the removal of the top middle region 2 of the initial protection structure 104 as etching time is accumulated. Namely: after the isolation layer 105 is formed, the top surface of the formed protection structure 106 is convex.
After the spacer 105 is formed, a replacement gate structure is formed on the top surface of the protective structure 106. Since the etchant makes the top surface of the protection structure 106 be convex, the replacement gate structure formed on the protection structure 106 is prone to toppling over in the recess at the top of the gate structure 106, so that the bottom surface of the replacement gate structure cannot cover the top surface of the first region a of the fin portion 100 on both sides of the initial isolation layer 101.
A gate structure is subsequently formed across the first region a of the fin 100. And forming an epitaxial layer in the first region A of the fin part 100 at two sides of the gate structure by taking the gate structure and the replacement gate structure as masks. The epitaxial layer forming step comprises the following steps: forming source and drain openings in the first region A of the fin portion 100 at two sides of the gate structure by taking the gate structure and the replacement gate structure as masks; and epitaxially growing an epitaxial layer in the source drain opening. Because the bottom surface of the replacement gate structure cannot cover the top surface of the first region a of the fin portion 100 at two sides of the initial isolation layer 101, the sidewalls of the source-drain openings formed in the first region a of the fin portion 100 at two sides of the gate structure are exposed from the sidewalls of the initial isolation layer 101 in the openings by using the gate structure and the replacement gate structure as masks, and the initial isolation layer 101 cannot provide a silicon source for the subsequent epitaxial growth to form an epitaxial layer, so that the formed epitaxial layer has poor morphology and is unfavorable for improving the performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a protection structure on the initial isolation layer and a first area of fin parts at two sides of the initial isolation layer, wherein the protection structure comprises: the semiconductor device comprises a first protective layer and a second protective layer positioned on the side wall of the first protective layer, wherein doping ions are arranged in the first protective layer; and in the etching process of forming the isolation layer, the removal rate of the first protection layer is smaller than that of the second protection layer. The method makes the replacement gate structure formed on the protection structure in the following process difficult to topple.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 15 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, an initial substrate 200 is provided, wherein the initial substrate 200 has a first oxide layer 201 thereon, and the first oxide layer 201 has a first mask layer 202 thereon.
In this embodiment, the material of the initial substrate 200 is silicon. In other embodiments, the material of the initial substrate comprises: germanium, silicon-on-insulator, or germanium-on-insulator.
In this embodiment, the materials of the first oxide layer 201 include: the process for forming the first oxide layer 201 includes: a fluid chemical vapor deposition process. The first oxide layer 201 is used as a buffer layer between the initial substrate 200 and a first mask layer formed subsequently on the first oxide layer 201. In other embodiments, the initial substrate has only the first mask layer thereon.
The materials of the first mask layer 202 include: silicon nitride, amorphous silicon, or titanium nitride, the first mask layer 202 is used as a mask in subsequent formation of the substrate and fin.
Referring to fig. 5 and 6, fig. 6 is a schematic cross-sectional view along line AA1 of fig. 5, and fig. 5 is a schematic cross-sectional view along line BB1 of fig. 6, in which the first mask layer 202 is patterned; etching the initial substrate 200 by using the patterned first mask layer 202 as a mask to form a substrate 203 and a fin 204 located on the substrate 203, wherein the fin 204 includes a plurality of first regions i and second regions ii located between adjacent first regions i, and openings 205 (not shown) penetrating through the second regions ii are formed in the fin 204; a second oxide layer 223 is formed on the substrate 203, on the sidewalls and top surfaces of the fins 204, and within the opening 205.
In this embodiment, the material of the initial substrate 200 is silicon. Correspondingly, the material of the substrate 203 is silicon, and the material of the fin 204 is silicon. In other embodiments, the material of the substrate comprises: a germanium substrate, a silicon-on-insulator, or a germanium-on-insulator. The fin material includes: a germanium substrate, a silicon-on-insulator, or a germanium-on-insulator.
The substrate 203 has a plurality of fins 204 thereon, and the plurality of fins 204 are arranged along a direction perpendicular to the extending direction of the fins 204. In this embodiment, the number of fin portions 204 is: 4, in other embodiments, the number of fin portions is 1-3; or, the number of the fin parts is as follows: more than 4.
A gate structure is subsequently formed across the first region i of the fin 204.
The opening 205 is used to subsequently receive an initial isolation layer.
A replacement gate structure is then formed on the initial isolation layer and the top surface of the fin 204 portion of the first region i on both sides of the initial isolation layer.
The dimensions of the opening 205 along the extension direction of the fin 204 are: 20-50 nm.
The top surface of the fin 204 has a portion of the first oxide layer 201 and a first mask layer 202 on the first oxide layer 201.
The materials of the second oxide layer 223 include: the process for forming the second oxide layer 223 includes: a fluid chemical vapor deposition process.
The second oxide layer 223 is used for protecting the substrate 203 and the fin 204 when the initial isolation material film is formed later.
In other embodiments, the second oxide layer is not formed after the substrate and the fin are formed.
Referring to fig. 7, an initial isolation material film 206 is formed on the second oxide layer 223.
Fig. 7 is a schematic view of the structure based on fig. 6.
The initial isolation material film 206 is used for subsequent isolation layer formation.
The initial isolation material film 206 is located on the substrate 203, in the sidewalls and top surfaces of the fins 204, and in the openings 205 (see fig. 6).
In this embodiment, the material of the initial isolation material film 206 is silicon oxide. In other embodiments, the material of the initial barrier material film comprises: silicon oxynitride.
In this embodiment, the forming process of the initial isolation material film 206 includes: a fluid chemical vapor deposition process.
The initial isolation material film 206 formed by the fluid chemical vapor deposition process has strong filling capability to the openings 205 and gaps between adjacent fins 204, and the formed initial isolation material film 206 has good isolation performance.
In the process of forming the initial isolation material film 206, the second oxide layer 223 protects the substrate 203 and the fin 204, so that the substrate 203 and the fin 204 are less damaged, which is beneficial to improving the performance of the semiconductor device.
Referring to fig. 8, a portion of the initial isolation material film 206, and the second oxide layer 223 (see fig. 7), the first mask layer 202 (see fig. 7), and the first oxide layer 201 (see fig. 7) on the fin 204 are removed until the top surface of the fin 204 is exposed, thereby forming an initial isolation layer 207.
The process of removing a portion of the initial isolation material film 206, and the second oxide layer, the first mask layer 202, and the first oxide layer 201 on the fin 204 includes: chemical mechanical polishing process.
The initial isolation layer 207 is used for the subsequent formation of isolation layers.
In this embodiment, after the initial isolation layer 207 is formed, a third oxide layer is formed on the initial isolation layer 207 and the top surface of the fin 204. Please refer to fig. 9 in detail.
In other embodiments, the third oxide layer is not formed after the initial isolation layer is formed.
Referring to fig. 9, a third oxide layer 208 is formed on the initial isolation layer 207 and the top surface of the fin 204.
The materials of the third oxide layer 208 include: the process for forming the third oxide layer 208 includes: a fluid chemical vapor deposition process.
The third oxide layer 208 serves as an initial isolation layer 207 and a buffer layer between the fin 204 and a mask layer subsequently formed over the initial isolation layer 207 and the fin 204.
After the initial isolation layer 207 is formed, a protection structure is formed on the initial isolation layer 207 and the first region i of the fin 204 at two sides of the initial isolation layer 207, and before the protection structure is formed, the method further includes: a mask layer is formed on the third oxide layer 208, as shown in fig. 10.
Referring to fig. 10, a mask layer 209 is formed on the third oxide layer 208, where the mask layer 209 has a mask opening 210, and a bottom of the mask opening 210 exposes the initial isolation layer 207 in the opening 205 (as shown in fig. 6) and a top surface of the third oxide layer 208 on a portion of the first region i of the fin 204 adjacent to both sides of the initial isolation layer 207 in the opening 205.
In this embodiment, the mask layer 209 includes: silicon nitride. In other embodiments, the mask layer comprises a material comprising: amorphous silicon or titanium nitride.
The mask opening 210 is used to subsequently accommodate a protective structure.
The dimensions of the mask opening 210 along the extending direction of the fin 204 are: 32 nm-80 nm. The dimensions of the mask opening 210 along the extension direction of the fin 204 are selected as follows: if the dimension of the mask opening 210 along the extending direction of the fin 204 is smaller than 32 nm, the dimension of the protection structure formed in the mask opening 210 along the extending direction of the fin 204 is too small, so that the dimension of the third oxide layer 208 on the first region i of the fin 204 at the bottom of the protection structure along the extending direction of the fin 204, which covers both sides of the initial isolation layer 207 in the opening 205, is too small, which is not beneficial for forming an epitaxial layer with good morphology in the following steps; if the dimension of the mask opening 210 along the extending direction of the fin 204 is greater than 80 nm, the dimension of the protection structure formed in the mask opening 210 along the extending direction of the fin 204 is too large, which is not beneficial to improving the integration of the device.
The bottom of the mask opening 210 exposes the top surface of the third oxide layer 208 on the initial isolation layer 207 within the opening 205: the protective structure subsequently formed in the mask opening 210 is located on the initial isolation layer 207 in the opening 205, so that the protective structure can protect the initial isolation layer 207 in the opening 205 from being removed when a portion of the initial isolation layer 207 is subsequently removed.
The bottom of the mask opening 210 exposes the top surface of the third mask layer 208 on the first region i of the fin portions 204 at both sides of the initial isolation layer 207 in the opening 205, which is as follows: the protection structure formed in the mask opening 210 is further located on the first region i of the fin 204 at two sides of the initial isolation layer 207 in the opening 205, which is beneficial to forming an epitaxial layer with good morphology.
A protective structure is subsequently formed within the mask opening 210, the protective structure comprising: the first protective layer and the second protective layer located on the side wall of the first protective layer. Since the mask layer 209 needs to be removed after the protective structure is formed, the material of the mask layer 209 is different from that of the first protective layer, so as to ensure that the first protective layer is not removed when the mask layer 209 is removed. The first protection layer is used for reducing the difference between the removal rate of the top edge area of the protection structure and the removal rate of the middle area of the protection structure, so that after the isolation layer is formed subsequently, the top surface of the protection structure is still flat, and the replacement gate structure is formed on the protection structure subsequently.
Referring to fig. 11, a first protection film 211 is formed on the mask layer 209 and on the sidewall and bottom surfaces of the mask opening 210.
In this embodiment, the material of the mask layer 209 is silicon nitride, and when the material of the first protection film 211 is silicon oxide, the first protection film 211 can have a higher etching selectivity with respect to the mask layer 209, so that the first protection film 211 is not removed when the mask layer 209 is subsequently removed. In other embodiments, the mask layer comprises a material comprising: amorphous silicon or titanium nitride, and the material of the first protective film comprises: when the silicon nitride, the silicon oxynitride, the silicon carbonitride or the silicon nitride boride is used, the first protective film can have a higher etching selectivity relative to the mask layer, so that the first protective layer is not removed when the mask layer is removed later.
In this embodiment, the forming process of the first protective film 211 includes: a chemical vapor deposition process, the parameters of the chemical vapor deposition process comprising: the reactant comprises a silicon source and an oxygen source gas, the silicon source comprises tetraethoxysilane, the oxygen source gas comprises oxygen, the flow rate of the oxygen source gas is 100 to 8000 standard milliliters per minute, the temperature is 300 to 500 ℃, the pressure is 3 to 200 torr, and the time is 20 to 10000 seconds.
In other embodiments, the forming process of the first protective film includes: an atomic layer deposition process; the parameters of the atomic layer deposition process include: the reactants include: the temperature of the silicon precursor and the oxygen precursor is 80-300 ℃, the pressure is 5 millitorr-20 torr, and the circulation time is 5-500 times.
The thickness of the first protective film 211 is: 2 nm-30 nm. The meaning of selecting the thickness of the first protective film 211 is that: if the thickness of the first protection film 211 is less than 2 nm, so that the thickness of the first protection layer formed subsequently is less than 2 nm, the capability of the first protection layer for slowing down the removal rate of the top edge region of the protection structure is insufficient when the isolation layer is formed subsequently, so that the top surface of the protection structure is still convex after the isolation layer is formed, and the replacement gate structure is easy to topple over when the replacement gate structure is formed on the protection structure subsequently; if the thickness of the first protection film 211 is greater than 30 nm, the implantation energy of the subsequent ion implantation process needs to be increased to avoid the top surface of the protection structure being convex, thereby increasing the process difficulty.
Referring to fig. 12, an ion implantation process is performed on the surface of the first protection film 211 to form a first protection layer 212, where the first protection layer 212 has doped ions.
In this embodiment, the parameters of the ion implantation process include: the doped ion is silicon ion, the implantation energy is 1 kiloelectron volt-20 kiloelectron volts, and the implantation dosage is 1.0E14atm/cm 2 ～1.0E20atm/cm 2 The injection angle is 0-45 degrees.
The significance of selecting the implant dose is that: if the implantation dose is less than 1.0E14atm/cm 2 Such that the first protective layer 212 is less capable of reducing the removal rate of the top edge region of the protective structure during subsequent formation of the isolation layer, such that after formation of the isolation layer,convex shapes appear on the top surface of the protection structure, and the replacement gate structure formed on the protection structure is easy to topple; if the implantation dose is greater than 1.0E20atm/cm 2 In the subsequent process of forming the isolation layer, the removal rate of the first protection layer 212 along the extending direction of the fin 204 is too slow, so that after the isolation layer is formed, the top surface of the protection structure is still not flat, and the replacement gate structure formed on the subsequent protection structure is easy to topple.
In this embodiment, the doping ions are: in the case of silicon ions, the concentration of the doped ions in the first protective layer 212 is as follows: 34% -50%, the meaning of selecting the atomic percentage concentration of the doping ions in the first protection layer 212 is that: if the atomic percentage concentration of the doping ions in the first protection layer 212 is less than 34%, the first protection layer 212 has weak capability of reducing the removal rate of the top edge region of the protection structure when the isolation layer is formed later, so that the removal rate of the top edge region of the protection structure is still greater than the removal rate of the middle region of the top of the protection structure, and the top of the protection structure is convex after the isolation layer is formed, which is not beneficial to forming a replacement gate structure on the protection structure later; if the atomic percentage concentration of the doping ions in the first protection layer 212 is greater than 50%, the difficulty of doping ions in the first protection layer is greater.
In other embodiments, when the dopant ion is a nitrogen ion, the concentration of the dopant ion in the first protection layer in atomic percentage is: 10% -25%.
In this embodiment, after the ion implantation process, an annealing process is performed on the first protection film 211. In other embodiments, the first protective film is not annealed after the ion implantation process.
In this embodiment, the annealing process is performed on the first protection film 211 in such a manner that the doping ions are diffused into the first protection film 211. The parameters of the annealing process include: the temperature is 800-1100 ℃ and the time is 0-100 seconds.
A second protective layer is then formed on the sidewalls of the first protective layer 212. In this embodiment, the material of the second protection layer is silicon oxide, the material of the first protection layer 212 is silicon oxide, and the first protection layer 212 has doping ions therein, so that the removal rate of the first protection layer 212 is smaller than the removal rate of the second protection layer when part of the initial isolation layer is removed later. In other embodiments, the material of the second protection layer is silicon oxide, and the material of the first protection film is silicon nitride, silicon oxynitride, silicon carbonitride or silicon nitride boride, and then when part of the initial isolation layer is removed, the removal rate of the first protection film is smaller than that of the second protection layer, so that an ion implantation process is not required for the first protection film, and the first protection film is the first protection layer.
The first protective layer 212 and a second protective layer formed later are used as a protective structure.
Referring to fig. 13, a second protective film 213 is formed on the first protective layer 212.
The second protective film 213 includes: and (3) silicon oxide.
In this embodiment, the forming process of the second protective film 213 includes: a fluid chemical vapor deposition process, the parameters of the fluid chemical vapor deposition process comprising: the reactant includes a silicon source gas and an oxygen source gas, the silicon source gas including N (SIH 3 ) 3 The oxygen source gas comprises oxygen, the flow of the silicon source gas is 20-10000 standard milliliters per minute, the catalytic gas comprises ammonia, the temperature is 30-90 ℃, and the pressure is 0.01-10 torr. In other embodiments, the forming process of the second protective film includes: a plasma chemical vapor deposition process.
The second protective film 213 is used for forming a second protective layer later.
Referring to fig. 14, the second protective film 213 is planarized until the top surface of the mask layer 209 (see fig. 13) is exposed, and a second protective layer 214 is formed in the mask opening 210 (see fig. 10); after the second protection layer 214 is formed, the second mask layer 209 is removed, so as to expose the first region i of the fin 204 and the top surface of the third oxide layer 208 on the initial isolation layer 207.
The process of planarizing the second protective film 213 includes: chemical mechanical polishing process.
In the process of forming the second protective layer 214, both the first protective layer 212 and the second protective film 213 located on the top surface of the mask layer 209 are removed.
The process of removing the second mask layer 209 includes: a dry etching process or a wet etching process.
The protection structure comprises: a first protective layer 212 located on the sidewalls and bottom of the mask opening 210 (see fig. 10) and a second protective layer 214 located on the first protective layer 212.
The protective structure serves to protect the initial isolation layer 207 within the opening 205.
A replacement gate structure is subsequently formed over the guard structure.
Referring to fig. 15, the third oxide layer 208 on the first region i of the fin 204 and the initial isolation layer 207 is removed; after removing the third oxide layer 208, removing a portion of the initial isolation layer 207, and forming an isolation layer 215, where a top surface of the isolation layer 215 is lower than a top surface of the fin 204 and covers a portion of a sidewall of the fin 204.
The process of forming the isolation layer 215 includes: wet etching process; the parameters of the wet etching process include: the etchant comprises hydrofluoric acid solution, and the mass percentage concentration of the etchant is 0.1% -1%.
Part of the top of the protective structure is also removed by the etchant during the formation of the isolation layer 215. The protection structure comprises: a first protective layer 212 and a second protective layer 214 on the sidewalls of the first protective layer 212.
In this embodiment, the material of the first protection layer 212 is silicon oxide, the material of the second protection layer 214 is silicon oxide, and the first protection layer 212 has doping ions, so that the atomic percentage concentration of oxygen in the first protection layer 212 is less than the atomic percentage concentration of oxygen in the second protection layer 214, so that in the process of removing part of the initial isolation layer 207, the corrosion resistance of the first protection layer 212 is stronger than that of the second protection layer 214, namely: the first protection layer 212 and the second protection layer 214 have different etching selectivity, and the removal rate of the first protection layer 212 is smaller than that of the second protection layer 214.
In this embodiment, in the process of forming the isolation layer 215, the etching selectivity of the first protection layer 212 and the second protection layer is: 10:1 to 200:1.
the significance of selecting the etching selectivity of the first protection layer 212 and the second protection layer 214 is that: if the etching selectivity of the first protective layer 212 and the second protective layer is smaller than 10:1, the first protection layer 212 is used for weakening the removal rate of the top edge area of the protection structure in the process of forming the isolation layer 215, so that the removal rate of the top edge area of the protection structure is still greater than the removal rate of the middle area of the protection structure in the process of forming the isolation layer 215, and after the isolation layer 215 is formed, the top of the protection structure is convex, so that the replacement gate structure formed on the protection structure is easy to topple; if the etching selectivity of the first protection layer 212 and the second protection layer is greater than 200:1, the difficulty of removing the first protection layer 212 is relatively high in the process of forming the isolation layer 215, so that after the isolation layer 215 is formed, the top of the protection structure is still uneven, and the replacement gate structure is easy to topple over in the subsequent protection structure.
The protection structure comprises: a first protection layer 212 and a second protection layer 214 located at the side wall of the first protection layer 212, so that during the removal of part of the initial isolation layer 207, both the side wall and the top of the first protection layer 212 are etched, and only the top surface of the second protection layer 214 is etched. In the process of removing part of the initial isolation layer 207, since the removal rate of the first protection layer 212 is smaller than that of the second protection layer 214, the first protection layer 212 can reduce the difference between the removal rate of the top edge region 11 of the protection structure and the removal rate of the top middle region 12 of the protection structure, so that after the isolation layer 215 is formed, the top surface of the protection structure is relatively flat, and the replacement gate structure formed on the protection structure is not easy to topple.
After forming the isolation layer 215, further comprising: forming a replacement gate structure on the protection structure, wherein the replacement gate structure is positioned in the opening 205 and on the initial isolation layer 207 and the first region I of the fin 204 adjacent to two sides of the initial isolation layer 207 in the opening 205; forming a gate structure crossing a portion of the first region i of the fin 204; after the gate structure and the replacement gate structure are formed, an epitaxial layer is formed in the first region i of the fin 204 on both sides of the gate structure, and the epitaxial layer covers a portion of the sidewalls of the replacement gate structure.
The epitaxial layer forming step comprises the following steps: forming source and drain openings in the first region I of the fin 204 at two sides of the gate structure by taking the gate structure and the replacement gate structure as masks; and forming the epitaxial layer in the source drain opening.
The epitaxial layer forming process comprises an epitaxial growth process.
When the epitaxial layer is formed, the replacement gate structure is used for limiting the growth space of the epitaxial layer and avoiding bridging of adjacent epitaxial layers. Correspondingly, the invention also provides a semiconductor structure formed by adopting the method.
Correspondingly, the embodiment of the invention also provides a semiconductor structure formed by adopting the method, referring to fig. 15, comprising:
a substrate 203, wherein a fin 204 is provided on the substrate 203, the fin 204 includes a plurality of first regions i and a second region ii located between adjacent first regions i, and an opening 205 is provided in the second region ii of the fin 204 (see fig. 6);
the opening 205 has an initial isolation layer 207 (see fig. 8), and the initial isolation layer 207 has a protection structure thereon, and the protection structure includes: a first protective layer 212 and a second protective layer 214 on sidewalls of the first protective layer 212;
the substrate 203 has an isolation layer 215 thereon, and the top surface of the isolation layer 215 is lower than the top surface of the fin 204 and covers a portion of the sidewall of the fin 204.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and the second areas of the fin part are provided with openings;
forming an initial isolation layer on the substrate, on the side wall of the fin part and in the opening;
forming a protection structure on the initial isolation layer and the first areas of fin parts on two sides of the initial isolation layer, wherein the protection structure comprises: the first protective layer and the second protective layer are positioned on the side wall of the first protective layer; the first protective layer is positioned at the top edge area of the protective structure, and the second protective layer is positioned at the top middle area of the protective structure; the protection structure covers the opening and the junction of the opening and the fin part;
and removing part of the initial isolation layer by adopting an etching process to form an isolation layer, wherein the top surface of the isolation layer is lower than the top surface of the fin part and covers part of the side wall of the fin part, and the etching rate of the first protection layer is lower than the etching rate of the second protection layer in the process of removing part of the initial isolation layer by etching.
2. The method of forming a semiconductor structure of claim 1, wherein the material of the initial isolation layer comprises: and (3) silicon oxide.
3. The method of forming a semiconductor structure of claim 1, wherein a portion of the top of the guard structure is removed during etching to remove a portion of the initial isolation layer.
4. The method of forming a semiconductor structure of claim 2, wherein the process of forming the isolation layer comprises: wet etching process; the parameters of the wet etching process include: the etchant comprises hydrofluoric acid solution, and the mass percentage concentration of the etchant is 0.1% -1%.
5. The method of forming a semiconductor structure of claim 1, wherein in forming said isolation layer, an etch selectivity of the first protective layer and the second protective layer is: 10:1 to 200:1.
6. the method of forming a semiconductor structure of claim 1, wherein the first protective layer has a thickness of: 2 nm-30 nm.
7. The method of forming a semiconductor structure of claim 1, wherein the step of forming a protective structure comprises: forming a mask layer on the initial isolation layer and the fin part, wherein the mask layer is provided with a mask opening, and the bottoms of the mask openings expose the top surfaces of the first areas of the fin part parts on two sides of the initial isolation layer and the initial isolation layer; and forming the protection structure in the mask opening.
8. The method of claim 7, wherein the mask opening has a dimension along the fin extension of: 32 nm-80 nm.
9. The method of forming a semiconductor structure of claim 7, wherein the material of the mask layer comprises: amorphous silicon, titanium nitride or silicon nitride.
10. The method of forming a semiconductor structure of claim 9, wherein when the material of the mask layer comprises amorphous silicon or titanium nitride, the material of the first protective layer comprises: silicon nitride, silicon oxynitride, silicon carbonitride or silicon nitride boride; the material of the second protective layer includes: and (3) silicon oxide.
11. The method of claim 9, wherein when the mask layer is silicon nitride, the first protective layer comprises silicon oxide, and the first protective layer has doped ions therein, wherein the doped ions comprise silicon ions or nitrogen ions; the material of the second protective layer includes silicon oxide.
12. The method of claim 11, wherein when the dopant ions are silicon ions, the concentration of the dopant ions in the first protective layer in atomic percent is: 34% -50%.
13. The method of claim 11, wherein when the dopant ions are nitrogen ions, the concentration of the dopant ions in the first protective layer is: 10% -25%.
14. The method of claim 11, wherein the process of doping the dopant ions into the first protective layer comprises: and (5) an ion implantation process.
15. The method of forming a semiconductor structure of claim 14, wherein the parameters of the ion implantation process comprise: when the doped ion is silicon, the implantation energy is 1 kiloelectron volt-20 kiloelectron volts, and the implantation dosage is 1.0E14atm/cm 2 ～1.0E20atm/cm 2 The injection angle is 0-45 degrees.
16. The method of forming a semiconductor structure of claim 14, wherein during forming said first protective layer, after said ion implantation process, further comprising: and annealing the first protective layer.
17. The method of forming a semiconductor structure of claim 16, wherein the parameters of the annealing process comprise: the temperature is 800-1100 ℃ and the time is 0-100 seconds.
18. The method of forming a semiconductor structure of claim 1, further comprising, after forming the isolation layer: forming a replacement gate structure on the protection structure, wherein the replacement gate structure is positioned on the initial isolation layer and the first areas of the fin parts at two sides of the initial isolation layer; forming a grid structure crossing part of the first region of the fin part; after the gate structure and the replacement gate structure are formed, an epitaxial layer is formed in the first region of the fin portions on two sides of the gate structure, and the epitaxial layer covers part of the side wall of the replacement gate structure.
19. The method of forming a semiconductor structure of claim 18, wherein the step of forming an epitaxial layer comprises: forming source and drain openings in the first areas of the fin parts at two sides of the gate structure by taking the gate structure and the replacement gate structure as masks, wherein the side walls and the bottoms of the source and drain openings are exposed out of the substrate; forming the epitaxial layer in the source drain opening; the material of the substrate comprises: silicon; the epitaxial layer forming process comprises an epitaxial growth process.
20. A semiconductor structure formed by the method of any of claims 1 to 19, comprising:
the substrate is provided with a fin part, the fin part comprises a plurality of first areas and second areas positioned between the adjacent first areas, and openings are formed in the second areas of the fin part;
the opening is internally provided with an initial isolation layer, the initial isolation layer is provided with a protection structure, and the protection structure comprises: the first protective layer and the second protective layer are positioned on the side wall of the first protective layer; the first protective layer is positioned at the top edge area of the protective structure, and the second protective layer is positioned at the top middle area of the protective structure; the protection structure covers the opening and the junction of the opening and the fin part;
the substrate is provided with an isolation layer, the top surface of the isolation layer is lower than the top surface of the fin portion, and part of the side wall of the fin portion is covered.
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