CN109148370A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN109148370A CN109148370A CN201710442424.7A CN201710442424A CN109148370A CN 109148370 A CN109148370 A CN 109148370A CN 201710442424 A CN201710442424 A CN 201710442424A CN 109148370 A CN109148370 A CN 109148370A
- Authority
- CN
- China
- Prior art keywords
- fin
- protective layer
- layer
- seal coat
- forming method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 79
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000010410 layer Substances 0.000 claims abstract description 171
- 239000011241 protective layer Substances 0.000 claims abstract description 132
- 238000000926 separation method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 61
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 44
- 150000002500 ions Chemical class 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 11
- -1 silicon ion Chemical class 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 239000003795 chemical substances by application Substances 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 3
- 241000208340 Araliaceae Species 0.000 claims 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 claims 2
- 235000003140 Panax quinquefolius Nutrition 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 2
- 235000008434 ginseng Nutrition 0.000 claims 2
- TZHYBRCGYCPGBQ-UHFFFAOYSA-N [B].[N] Chemical compound [B].[N] TZHYBRCGYCPGBQ-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 230000001681 protective effect Effects 0.000 description 27
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000012530 fluid Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000012071 phase Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes: offer substrate, has fin in substrate, and fin includes several firstth areas and the secondth area between adjacent firstth area, has in the secondth area of fin and is open；Initial seal coat is formed in substrate, in fin side wall and opening；Protection structure is formed in the firstth area of fin part of initial seal coat and initial seal coat two sides, protection structure includes: the first protective layer and positioned at the second protective layer in the first protective layer side wall；Part initial seal coat is removed using etching technics; separation layer is formed, the surface of separation layer is lower than the top of fin, and covers the partial sidewall of fin; during etching removes part initial seal coat, the rate of the first protective layer of etching is less than the rate of the second protective layer of etching.It is preferable to be formed by device performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the raising of semiconductor devices integrated level, the critical size of transistor constantly reduces.However, with transistor ruler
Very little strongly reduces, and gate dielectric layer thickness corresponding cannot change the difficulty for making to inhibit short-channel effect to operating voltage and increase, and makes
The channel leakage stream of transistor increases.
The grid of fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) is at similar fin
Forked 3D framework.The channel protrusion substrate surface of FinFET forms fin, and grid covers top surface and the side wall of fin, to make
Inversion layer is formed on each side of channel, can be in the connecting and disconnecting of the two sides control circuit of fin.
In order to further increase the integrated level of semiconductor devices, a kind of method is that isolation structure is formed in fin, subsequent
Replacement gate structure is formed on the isolation structure.
However, the difficulty for forming the replacement gate structure is larger.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of forming methods of semiconductor structure, form replacement gate to reduce
The difficulty of structure.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, comprising: provide
Substrate has fin in the substrate, and the fin includes several firstth areas and the secondth area between adjacent firstth area, institute
Stating has opening in the secondth area of fin；On the substrate, initial seal coat is formed in the side wall of fin and opening；Described first
Protection structure is formed in the firstth area of beginning separation layer and initial seal coat two sides fin part, the protection structure includes: the first guarantor
Sheath and the second protective layer positioned at the first protective layer side wall；Part initial seal coat is removed using etching technics, forms isolation
Layer, the top surface of the separation layer is lower than the top surface of fin, and covers the partial sidewall of fin, removes in the etching
During the initial seal coat of part, the rate of the first protective layer of etching is less than the rate of the second protective layer of etching.
Optionally, the material of the initial seal coat includes: silica.
Optionally, during forming the separation layer, part protects the top of structure to be also removed.
Optionally, the technique for forming separation layer includes: wet-etching technology；The parameter of the wet-etching technology includes:
Etching agent includes hydrofluoric acid solution, and the mass percent concentration of etching agent is 0.1%~1%.
Optionally, during forming the separation layer, the etching selection ratio of the first protective layer and the second protective layer are as follows:
10:1~200:1.
Optionally, first protective layer thickness are as follows: 2 nanometers~30 nanometers.
Optionally, the forming step of the protection structure includes: the top surface shape in the initial seal coat and fin
At mask layer, the mask layer have mask open, the bottom-exposed of the mask open go out initial seal coat and with initially every
The top surface in the firstth area of fin part of absciss layer two sides；The protection structure is formed in the mask open.
Optionally, along fin extending direction, the size of the mask open are as follows: 32 nanometers~80 nanometers.
Optionally, the material of the mask layer includes: amorphous silicon, titanium nitride or silicon nitride.
Optionally, when the material of the mask layer includes amorphous silicon or titanium nitride, the material packet of first protective layer
It includes: silicon nitride, silicon oxynitride, carbonitride of silicium or nitrogen silicon boride；The material of second protective layer includes: silica.
Optionally, when the material of the mask layer is silicon nitride, the material of first protective layer includes silica, described
There are Doped ions, the Doped ions include silicon ion or Nitrogen ion in first protective layer；The material of second protective layer
Material includes silica.
Optionally, when the Doped ions are silicon ion, the atomic percent of Doped ions is dense in first protective layer
Degree are as follows: 34%~50%.
Optionally, when the Doped ions are Nitrogen ion, the atomic percent of Doped ions is dense in first protective layer
Degree are as follows: 10%~25%.
Optionally, the technique of the Doped ions is mixed in first protective layer includes: ion implantation technology.
Optionally, the parameter of the ion implantation technology include: the Doped ions be silicon when, Implantation Energy be 1,000 electricity
~20 kiloelectron-volts of son volt, implantation dosage 1.0E14atm/cm2~1.0E20atm/cm2, implant angle is 0 degree~45 degree.
Optionally, during forming first protective layer, after the ion implantation technology, further includes: to described
First protective layer is made annealing treatment.
Optionally, it is 800 degrees Celsius~1100 degrees Celsius that the parameter of the annealing treating process, which includes: temperature, the time 0
Second~100 seconds.
Optionally, it is formed after the separation layer, further includes: replacement gate structure is formed in the protection structure；Shape
At the gate structure across part firstth area of fin；It is formed after the gate structure and replacement gate structure, described
Gate structure two sides form epitaxial layer, the side of the epitaxial layer covering part replacement gate structure in adjacent the firstth area of fin
Wall.
Optionally, the forming step of the epitaxial layer include: using the gate structure and replacement gate structure as exposure mask,
Source and drain opening is formed in the firstth area of fin of the gate structure two sides, the side wall of the source and drain opening and bottom expose base
Bottom；The epitaxial layer is formed in the source and drain is open；The material of the substrate includes: the formation process packet of epitaxial layer described in silicon
Include epitaxial growth technology.
Correspondingly, the present invention also provides a kind of a kind of semiconductor structures formed using the above method, comprising: substrate, institute
Stating has fin in substrate, the fin includes several firstth areas and the secondth area between adjacent firstth area, the fin
The secondth area in have opening；There is initial seal coat in the opening, there is protection structure on the initial seal coat, it is described
Protection structure includes: the first protective layer and the second protection positioned at the first protective layer side wall；There is separation layer, institute in the substrate
The top surface for stating separation layer is lower than the top surface of fin, and covers the partial sidewall of fin.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the forming method for the semiconductor structure that technical solution of the present invention provides, part initial seal coat is removed, forms institute
State separation layer.During removing part initial seal coat, the top of the part protection structure is also removed.Due to described
Protection structure includes: the first protective layer and the second protective layer positioned at the first protective layer side wall, therefore, at the beginning of removal part is described
During beginning separation layer, the top of first protective layer and partial sidewall are etched, and second protective layer only pushes up
Portion surface is etched.During removing part initial seal coat, since the removal rate of the first protective layer is protected less than second
The removal rate of sheath, therefore, the first protective layer can reduce the removal rate of protection structural top fringe region and protection is tied
The difference of the removal rate of structure intermediate region, so that being formed after the separation layer, the top surface of the protection structure is opposite
It is smooth, so that subsequent be not susceptible to topple in the structrural build up replacement gate structure of protection.
Further, replacement gate structure is located in the firstth area of fin part of initial seal coat and initial seal coat two sides.
It is subsequent when forming the epitaxial layer in the firstth area of fin of gate structure two sides, the replacement gate structure is described for limiting
The growing space of epitaxial layer, avoids adjacent epitaxial layer from bridging.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of the forming process of semiconductor structure；
Fig. 4 to Figure 15 is the structural schematic diagram of the forming process of semiconductor structure in first embodiment of the invention.
Specific embodiment
There are problems for the forming method of semiconductor structure, such as: the difficulty for forming replacement gate structure is larger.
Now in conjunction with a kind of forming method of semiconductor structure, the formation replacement gate structure that the forming method is formed is analyzed
The larger reason of difficulty:
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure.
Referring to FIG. 1, providing substrate (not shown), there is fin 100 in the substrate, the fin 100 includes
There is opening (in figure not in several firstth area A and the second area B between adjacent firstth area A, the 100 second area B of fin
It marks)；Initial seal coat 101, the top of the initial seal coat 101 are formed in the substrate, the side wall of fin 100 and opening
Portion surface exposes the top surface of fin 100；Mask layer 102, the mask layer are formed on the initial seal coat 101
102 have mask open 103, and the bottom-exposed of the mask open 103 goes out initial seal coat 101 and 101 liang of initial seal coat
The top surface of the firstth area of part A in lateral fin portion 100.
Referring to FIG. 2, forming initial protection structure 104 in the mask open 103 (see Fig. 1)；Form initial protection
After structure 104, mask layer 102 is removed, top surface and the part for exposing 100 part of fin the firstth area A are described initial
The top surface of separation layer 101.
Referring to FIG. 3, removing part initial seal coat 101 after removing the mask layer 102, separation layer 105 is formed,
The top surface of the separation layer 105 is lower than the top surface of fin 100, and covers the partial sidewall of fin 100.
However, poor using the performance of the semiconductor devices of above method preparation, reason is:
In the above method, the material of the initial seal coat 101 includes: silica, the formation process of the separation layer 105
It include: wet-etching technology, the parameter of the wet-etching technology includes: that etching agent includes hydrofluoric acid solution.Due to the guarantor
The material of protection structure 104 includes: silica, therefore, using the process of wet-etching technology removal part initial seal coat 101
In, the atop part of the initial protection structure 104 is also removed.
Specifically, being removed at the top of the initial protection structure 104 during removing part initial seal coat 101
Part include: the top edge region 1 of initial protection structure 104 and the top center region 2 of initial protection structure 104.Institute
The removal rate for stating the top edge region 1 of initial protection structure 104 includes: initial protection 104 top edge region of structure, 1 side
Second etch rate of the first etch rate of wall and initial 1 top of protection 104 top edge region of structure, and the initial guarantor
The top center region 2 of protection structure 104 only has third etch rate.Since the initial protection structure 104 is single layer structure,
The material of the initial protection structure 104 includes: silica, therefore, the first etch rate, the second etch rate and third etching
Rate is all the same, so that the etch rate of initial protection 104 top edge region 1 of structure is greater than initial protection structure 104
The intermediate region 2 at top, with the accumulation of etch period, so that the initially removal amount of the top edge region 1 of protection structure 104
Greater than the removal amount in the top center region 2 of initial protection structure 104.That is: it is formed after the separation layer 105, is formed by
The top surface for protecting structure 106 is in convex.
It is formed after the separation layer 105, forms replacement gate structure in the top surface of protection structure 106.By institute
Etching agent is stated to protect the top surface of structure 106 in convex, therefore, the replacement gate knot formed in protection structure 106
Structure is easily toppled over to the recess at 106 top of gate structure, so that the bottom surface of the replacement gate structure can not cover
The top surface of 100 part of fin the firstth area A of 101 two sides of initial seal coat.
It is subsequently formed the gate structure across 100 first area A of fin.Using gate structure and replacement gate structure as exposure mask,
Epitaxial layer is formed in the 100 first area A of fin of gate structure two sides.The forming step of the epitaxial layer includes: with grid knot
Structure and replacement gate structure are exposure mask, and source and drain opening is formed in the 100 first area A of fin of gate structure two sides；In the source
Epitaxial layer is epitaxially-formed in leakage opening.Since the bottom surface of replacement gate structure can not cover 101 liang of initial seal coat
The top surface of 100 part of fin the firstth area A of side, so that using gate structure and replacement gate structure as exposure mask, in grid knot
The side wall of the source and drain opening formed in the 100 first area A of fin of structure two sides exposes the side of the initial seal coat 101 in opening
Wall, the initial seal coat 101 cannot form epitaxial layer for subsequently epitaxial growing and provide silicon source, so that being formed by epitaxial layer
Pattern is poor, is unfavorable for improving the performance of semiconductor devices.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, by described first
Protection structure is formed in the firstth area of fin part of beginning separation layer and initial seal coat two sides, the protection structure includes: first
Protective layer and the second protective layer positioned at the first protective layer side wall have Doped ions in first protective layer；Forming institute
It states in the etching process of separation layer, the removal rate of the removal rate of the first protective layer less than the second protective layer.The method makes
Subsequent structrural build up replacement gate structure must protected to be not susceptible to topple over.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 4 to Figure 15 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 4, providing initial substrate 200, there is the first oxide layer 201 on the initial substrate 200, described first
There is the first mask layer 202 in oxide layer 201.
In the present embodiment, the material of the initial substrate 200 is silicon.In other embodiments, the initial substrate
Material includes: germanium, SiGe, silicon-on-insulator or germanium on insulator.
In the present embodiment, the material of first oxide layer 201 includes: silica, the shape of first oxide layer 201
It include: fluid chemistry gas-phase deposition at technique.First oxide layer 201 be used for as initial substrate 200 and it is subsequent
The buffer layer between the first mask layer formed in first oxide layer 201.In other embodiments, only have on the initial substrate
There is the first mask layer.
The material of first mask layer 202 includes: silicon nitride, amorphous silicon or titanium nitride, first mask layer 202
As exposure mask when for being subsequently formed substrate and fin.
Fig. 5 and Fig. 6 are please referred to, Fig. 6 is the schematic diagram of the section structure of the Fig. 5 along AA1, and Fig. 5 is that Fig. 6 shows along the section of BB1 line
It is intended to, graphical first mask layer 202；It is exposure mask with graphical first mask layer 202, etches the initial substrate 200,
Substrate 203 and the fin 204 in substrate 203 are formed, the fin 204 is including several firstth areas I and positioned at adjacent first
The second area II between area I, interior 205 (not shown) of opening having through the second area II of the fin 204；In substrate
The second oxide layer 223 is formed on 203, in the side wall of fin 204 and top surface and opening 205.
In the present embodiment, the material of the initial substrate 200 is silicon.Correspondingly, the material of the substrate 203 is silicon,
The material of the fin 204 is silicon.In other embodiments, the material of the substrate includes: germanium substrate, silicon-Germanium base, insulation
Silicon or germanium on insulator on body.The material of the fin includes: germanium substrate, silicon-Germanium base, silicon-on-insulator or germanium on insulator.
There are multiple fins 204, multiple fins 204 are along the direction extended perpendicular to the fin 204 in the substrate 203
Upper arrangement.In the present embodiment, the number of the fin 204 are as follows: 4, in other embodiments, the number of the fin is 1
It is a~3；Alternatively, the number of the fin are as follows: 4 or more.
It is subsequently formed the gate structure across 204 first area I of fin.
The opening 205 is used for subsequent receiving initial seal coat.
The top surface formation in subsequent the firstth area of 204 part of fin I in initial seal coat and initial seal coat two sides is replaced
For gate structure.
Along 204 extending direction of fin, the size of the opening 205 are as follows: 20 nanometers~50 nanometers.
The top surface of the fin 204 have the first oxide layer of part 201 and in the first oxide layer 201 first
Mask layer 202.
The material of second oxide layer 223 includes: silica, and the formation process of second oxide layer 223 includes: stream
Body chemical vapor phase growing technique.
Second oxide layer 223 is for protecting the substrate 203 and fin when being subsequently formed initial isolated material film
204。
In other embodiments, it is formed after the substrate and fin, does not form the second oxide layer.
Referring to FIG. 7, forming initial isolated material film 206 in second oxide layer 223.
It should be noted that Fig. 7 is the structural schematic diagram on the basis of Fig. 6.
The initial isolated material film 206 is for being subsequently formed separation layer.
The initial isolated material film 206 is located in substrate 203, the side wall of fin 204 and top surface and opening 205
In (see Fig. 6).
In the present embodiment, the material of the initial isolated material film 206 is silica.In other embodiments, described
The material of initial isolated material film includes: silicon oxynitride.
In the present embodiment, the formation process of the initial isolated material film 206 includes: fluid chemistry vapor deposition work
Skill.
206 pairs of the initial isolated material film openings 205 formed using fluid chemistry gas-phase deposition and adjacent fin
The filling capacity in the gap between 204 is stronger, and the isolation performance of the initial isolated material film 206 of formation is good.
During forming initial isolated material film 206, second oxide layer 223 protects the substrate 203 and fin
Portion 204 is conducive to the performance for improving semiconductor devices so that the damage that the substrate 203 and fin 204 are subject to is smaller.
Referring to FIG. 8, the initial isolated material film 206 in removal part and the second oxide layer 223 on fin 204
(see Fig. 7), the first mask layer 202 (see Fig. 7) and the first oxide layer 201 (see Fig. 7), until exposing the top of fin 204
Surface forms initial seal coat 207.
The initial isolated material film 206 in removal part and the second oxide layer on fin 204, the first mask layer 202
And first the technique of oxide layer 201 include: chemical mechanical milling tech.
The initial seal coat 207 is for being subsequently formed separation layer.
In the present embodiment, it is formed after the initial seal coat 207, in the initial seal coat 207 and fin 204
Top surface forms third oxide layer.Specifically please refer to Fig. 9.
In other embodiments, it is formed after the initial seal coat, does not form the third oxide layer.
Referring to FIG. 9, forming third oxide layer 208 in the top surface of the initial seal coat 207 and fin 204.
The material of the third oxide layer 208 includes: silica, and the formation process of the third oxide layer 208 includes: stream
Body chemical vapor phase growing technique.
The third oxide layer 208 as initial seal coat 207 and fin 204 and it is subsequent in initial seal coat 207 and
The buffer layer between mask layer formed on fin 204.
It is formed after the initial seal coat 207, in 207 two sides fin of the initial seal coat 207 and initial seal coat
Protection structure is formed on 204 the firstth area of parts I, is formed before the protection structure, further includes: in the third oxide layer 208
Upper formation mask layer, specifically please refers to Figure 10.
Referring to FIG. 10, forming mask layer 209 in the third oxide layer 208, the mask layer 209 is opened with exposure mask
Mouth 210, the bottom-exposed of the mask open 210 go out in the interior initial seal coat 207 of 205 (as shown in Figure 6) that are open and opening 205
The top surface of third oxide layer 208 in the firstth area of part I of the adjacent fin 204 in 207 two sides of initial seal coat.
In the present embodiment, the material of the mask layer 209 includes: silicon nitride.In other embodiments, the mask layer
Material include: amorphous silicon or titanium nitride.
The mask open 210 protects structure for subsequent receiving.
Size of the mask open 210 on 204 extending direction of fin are as follows: 32 nanometers~80 nanometers.It is covered described in selection
The meaning of size of the film opening 210 on 204 extending direction of fin is: if the mask open 210 is along 204 side of extension of fin
Upward size is less than 32 nanometers, so that the subsequent protection structure formed in mask open 210 is along 204 extending direction of fin
It is undersized so that protection structural base cover along 204 extending direction of fin be open 205 in 207 two sides of initial seal coat
The firstth area of 204 part of fin I on third oxide layer 208 it is undersized, be unfavorable for being subsequently formed the good extension of pattern
Layer；If size of the mask open 210 on 204 extending direction of fin is greater than 80 nanometers, so that subsequent in mask open 210
The protection structure of interior formation is oversized on 204 extending direction of fin, is unfavorable for improving the integrated level of device.
The bottom-exposed of the mask open 210 goes out the third oxide layer 208 in opening 205 on initial seal coat 207
The meaning of top surface is: so that the subsequent protection structure formed in mask open 210 be located at opening 205 in it is initial every
On absciss layer 207, so that protection structure can protect the initial isolation in opening 205 when subsequent removal part initial seal coat 207
Layer 207 is not removed.
And the bottom-exposed of the mask open 210 goes out the part of 207 two sides fin 204 of initial seal coat in opening 205
The meaning of the top surface of third mask layer 208 in first area I is: so that the subsequent guarantor formed in mask open 210
Protection structure is also located in opening 205 in the firstth area of 207 two sides fin of initial seal coat, 204 part I, is conducive to be subsequently formed pattern
Good epitaxial layer.
Subsequent to form protection structure in mask open 210, the protection structure includes: the first protective layer and positioned at first
Second protective layer of protective layer side wall.After forming the protection structure, mask layer 209 need to be removed, therefore, the exposure mask
The material and the first protective layer of layer 209 be not identical, and when guaranteeing to remove the mask layer 209, first protective layer is not gone
It removes.Described first protective layer used goes in the removal rate for slowing down protection structural top fringe region with structure intermediate region is protected
The difference of removal rates is conducive to subsequent so that the top surface of the protection structure is still smooth after being subsequently formed separation layer
Replacement gate structure is formed in protection structure.
Figure 11 is please referred to, on the mask layer 209, the side wall of mask open 210 and bottom surface, forms the first protection
Film 211.
In this embodiment, the material of the mask layer 209 is silicon nitride, and 211 material of the first protective film is silica
When, the first protective film 211 can be made relative to the Etch selectivity with higher of mask layer 209, so that subsequent removal mask layer
When 209, the first protective layer 211 is not removed.In other embodiments, the material of the mask layer includes: amorphous silicon or nitrogen
Change titanium, when the material of first protective film includes: silicon nitride, silicon oxynitride, carbonitride of silicium or nitrogen silicon boride, the can be made
One protective film is relative to mask layer etching selection ratio with higher so that when subsequent removal mask layer, the first protective layer not by
Removal.
In the present embodiment, the formation process of first protective film 211 includes: chemical vapor deposition process, describedization
It includes silicon source and oxygen source gas that the parameter for learning gas-phase deposition, which includes: reactant, and silicon source includes ethyl orthosilicate, oxygen source gas
Including oxygen, the flow of oxygen source gas is 100 standard milliliters/per minute~8000 standard milliliters/per minute, and temperature is 300 to take the photograph
Family name degree~500 degree Celsius, pressure are 3 supports~200 supports, and the time is 20 seconds~10000 seconds.
In other embodiments, the formation process of first protective film includes: atom layer deposition process；The atomic layer
The parameter of depositing operation includes: that reactant includes: silicon precursor and oxygen presoma, and temperature is 80 degrees Celsius~300 degrees Celsius, pressure
It is by force 5 millitorrs~20 supports, cycle-index is 5 times~500 times.
First protective film, 211 thickness are as follows: 2 nanometers~30 nanometers.Select the meaning of the thickness of first protective film 211
Justice is: if the thickness of first protective film 211 less than 2 nanometers so that the first protective layer thickness being subsequently formed is received less than 2
Rice, when so that being subsequently formed separation layer, the first protective layer used energy in the removal rate for slowing down protection structural top fringe region
Power is inadequate, so that being formed after the separation layer, protecting the top surface of structure is still in convex, subsequent to be formed in protection structure
Replacement gate structure is easily toppled over；If the thickness of first protective film 211 is greater than 30 nanometers, subsequent in order to avoid protection knot
The top surface of structure is in convex, need to increase the Implantation Energy of subsequent ion injection technology, increases technology difficulty.
Figure 12 is please referred to, ion implantation technology is carried out to 211 surface of the first protective film, forms the first protective layer 212,
There are Doped ions in first protective layer 212.
In the present embodiment, it is silicon ion, Implantation Energy that the parameter of the ion implantation technology, which includes: the Doped ions,
It is 1 kiloelectron-volt~20 kiloelectron-volts, implantation dosage 1.0E14atm/cm2~1.0E20atm/cm2, implant angle be 0 degree~
45 degree.
The meaning of the implantation dosage is selected to be: if the implantation dosage is less than 1.0E14atm/cm2, so that subsequent
During forming separation layer, first protective layer 212 is used to weaken the removal rate of protection structural top fringe region
Ability is weaker, so that being formed after the separation layer, the top surface of structure is protected convex, the subsequent shape in protection structure occur
At replacement gate structure easily topple over；If the implantation dosage is greater than 1.0E20atm/cm2, so that being subsequently formed isolation
During layer, removal rate of first protective layer 212 on the extending direction of fin 204 is excessively slow, so that forming isolation
After layer, the top surface still out-of-flatness of structure is protected, so that subsequent protecting structrural build up replacement gate structure also easily to send out
Phenomenon is toppled in life.
In the present embodiment, the Doped ions are as follows: when silicon ion, the original of Doped ions in first protective layer 212
Sub- percent concentration are as follows: 34%~50%, select the meaning of the atom percentage concentration of Doped ions in first protective layer 212
Justice is: if the atom percentage concentration of Doped ions is less than 34% in first protective layer 212 so that it is subsequent formed every
When absciss layer, the ability that first protective layer 212 can reduce the removal rate of protection structural top fringe region is weaker, so that
The removal rate of the protection structural top fringe region is still greater than the removal rate of protection structural top intermediate region, so that shape
After separation layer, protects the top of structure in convex, be unfavorable for the subsequent formation replacement gate structure in protection structure；If institute
The atom percentage concentration for stating Doped ions in the first protective layer 212 is greater than 50%, so that the Doped ions in the first protective layer
Difficulty it is larger.
In other embodiments, when the Doped ions are Nitrogen ion, the atom of Doped ions in first protective layer
Percent concentration are as follows: 10%~25%.
In the present embodiment, after the ion implantation technology, first protective film 211 is carried out at annealing process
Reason.In other embodiments, after the ion implantation technology, the first protective film is not made annealing treatment.
In the present embodiment, to first protective film 211 carry out annealing process processing meaning be so that adulterate from
Son diffuses in the first protective film 211.The parameter of the annealing process includes: that temperature is 800 degrees Celsius~1100 degrees Celsius, when
Between be 0 second~100 seconds.
The subsequent side wall in the first protective layer 212 forms the second protective layer.In the present embodiment, second protective layer
Material is silica, and the material of the first protective layer 212 is silica, has Doped ions in first protective layer 212, so that
It is subsequent when removing part initial seal coat, the removal rate of the removal rate of the first protective layer 212 less than the second protective layer.?
In other embodiments, the material of second protective layer is silica, and the material of first protective film is silicon nitride, nitrogen oxidation
Silicon, carbonitride of silicium or nitrogen silicon boride, subsequent when removing part initial seal coat, the removal rate of the first protective film is less than
The removal rate of two protective layers, it is therefore not necessary to carry out ion implantation technology to the first protective film, first protective film is the
One protective layer.
It first protective layer 212 and is subsequently formed second protective layer used in as protection structure.
Figure 13 is please referred to, forms the second protective film 213 on first protective layer 212.
The material of second protective film 213 includes: silica.
In the present embodiment, the formation process of second protective film 213 includes: fluid chemistry gas-phase deposition, institute
It includes silicon source gas and oxygen source gas that the parameter for stating fluid chemistry gas-phase deposition, which includes: reactant, and silicon source gas includes N
(SIH3)3, oxygen source gas includes oxygen, and the flow of silicon source gas is 20 standard milliliters/per minute~10000 standard milliliters/every point
Clock, catalyzed gas include ammonia, and temperature is 30 degrees Celsius~90 degrees Celsius, and pressure is 0.01 support~10 supports.In other embodiments
In, the formation process of second protective film includes: plasma activated chemical vapour deposition technique.
Second protective film 213 is for being subsequently formed the second protective layer.
Figure 14 is please referred to, second protective film 213 is planarized, until exposing the top of mask layer 209 (see Figure 13)
Surface forms the second protective layer 214 in the mask open 210 (see Figure 10)；It is formed after second protective layer 214,
The second mask layer 209 is removed, the top in fin 204 first area I and the third oxide layer 208 on initial seal coat 207 is exposed
Surface.
The technique of planarization second protective film 213 includes: chemical mechanical milling tech.
During forming the second protective layer 214, positioned at the first protective layer 212 and second of 209 top surface of mask layer
Protective film 213 is removed.
The technique for removing the second mask layer 209 includes: dry etch process or wet-etching technology.
The protection structure include: the first protective layer 212 positioned at (see Figure 10) side wall of mask open 210 and bottom and
The second protective layer 214 on the first protective layer 212.
The protection structure is used to protect the initial seal coat 207 in opening 205.
It is subsequent to form replacement gate structure in protection structure.
Figure 15 is please referred to, the third oxide layer 208 on 204 first area I of fin and initial seal coat 207 is removed；Removal institute
After stating third oxide layer 208, the part initial seal coat 207 is removed, forms separation layer 215, the top of the separation layer 215
Portion surface is lower than the top surface of fin 204, and covers the partial sidewall of fin 204.
The technique for forming separation layer 215 includes: wet-etching technology；The parameter of the wet-etching technology includes: etching
Agent includes hydrofluoric acid solution, and the mass percent concentration of etching agent is 0.1%~1%.
During forming separation layer 215, the atop part of structure is protected also to be removed by the etching agent.The protection
Structure includes: the first protective layer 212 and the second protective layer 214 positioned at 212 side wall of the first protective layer.
In the present embodiment, the material of first protective layer 212 is silica, the material of second protective layer 214
For silica, and there are Doped ions in first protective layer 212 so that in the first protective layer 212 oxygen atomic percent
Concentration is few compared with the atom percentage concentration of oxygen in the second protective layer 214, so that in the process of removal part initial seal coat 207
In, the corrosion resistance of the first protective layer 212 is strong compared with the corrosion resistance of the second protective layer 214, it may be assumed that first protective layer, 212 He
Second protective layer 214 has different etching selection ratios, and the removal rate of first protective layer 212 is less than the second protective layer
214 removal rate.
In the present embodiment, during forming separation layer 215, first protective layer 212 and the second protective layer
Etching selection ratio are as follows: 10:1~200:1.
The meaning of the etching selection ratio of first protective layer 212 and the second protective layer 214 is selected to be: if described first
The etching selection ratio of protective layer 212 and the second protective layer is less than 10:1, so that during forming separation layer 215, described the
The ability that one protective layer 212 is used to weaken the removal rate of protection structural top fringe region is too small, so that forming separation layer
During 215, the removal rate of the protection structural top fringe region is still greater than the removal speed of protection structure intermediate region
Rate protects the top of structure in convex so that being formed after separation layer 215, so that subsequent form alternative gate in protection structure
Pole structure is easily toppled over；If the etching selection ratio of first protective layer 212 and the second protective layer is greater than 200:1, so that
During forming separation layer 215, the difficulty that the first protective layer 212 is removed is larger, so that being formed after separation layer 215, protects
The top of protection structure still out-of-flatness, so that the subsequent formation replacement gate structure in protection structure is easily toppled over.
The protection structure includes: the first protective layer 212 and the second protective layer 214 positioned at 212 side wall of the first protective layer,
Therefore, during removing part initial seal coat 207, the side wall of first protective layer 212 and top are etched, and
Only top surface is etched second protective layer 214.During removing part initial seal coat 207, due to the first guarantor
The removal rate of sheath 212 is less than the removal rate of the second protective layer 214, and therefore, the first protective layer 212 can reduce protection knot
The difference of the removal rate of the removal rate and protection structural top intermediate region 12 of structure top edge region 11, so that forming institute
After stating separation layer 215, the top surface of the protection structure is opposed flattened, so that subsequent structrural build up in the protection
Replacement gate structure is not susceptible to topple over.
It is formed after the separation layer 215, further includes: replacement gate structure is formed in the protection structure, it is described to replace
It is located at the fin 204 that initial seal coat 207 is adjacent with 207 two sides of initial seal coat in opening 205 in opening 205 for gate structure
In the firstth area of part I；It is developed across the gate structure in part 204 first area I of fin；Form the gate structure and substitution
After gate structure, epitaxial layer, the epitaxial layer covering part are formed in 204 first area I of fin of the gate structure two sides
Divide the side wall of replacement gate structure.
The forming step of the epitaxial layer includes: using the gate structure and replacement gate structure as exposure mask, in the grid
Source and drain opening is formed in 204 first area I of fin of pole structure two sides；The epitaxial layer is formed in the source and drain is open
The formation process of the epitaxial layer includes epitaxial growth technology.
When forming epitaxial layer, the replacement gate structure is used to limit the growing space of the epitaxial layer, avoids adjacent
Epitaxial layer bridge joint.Correspondingly, being formed by semiconductor structure using the above method the present invention also provides a kind of.
Correspondingly, the embodiment of the present invention also provide it is a kind of semiconductor structure is formed by using the above method, please refer to figure
15, comprising:
Substrate 203, has fin 204 in the substrate 203, and the fin 204 includes several firstth areas I and is located at adjacent
Second area II in the second area II between the first area I, the fin 204 is interior with 205 (see Fig. 6) of opening；
There is initial seal coat 207 (see Fig. 8) in the opening 205, there is protection knot on the initial seal coat 207
Structure, the protection structure include: the first protective layer 212 and protect 214 positioned at the second of 212 side wall of the first protective layer；
There is separation layer 215, the top surface of the separation layer 215 is lower than the top table of fin 204 in the substrate 203
Face, and cover the partial sidewall of fin 204.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, there is in the substrate fin, the fin includes several firstth areas and between adjacent firstth area
Secondth area has opening in the secondth area of the fin；
On the substrate, initial seal coat is formed in the side wall of fin and opening；
Protection structure, the protection knot are formed in the firstth area of fin part of the initial seal coat and initial seal coat two sides
Structure includes: the first protective layer and the second protective layer positioned at the first protective layer side wall；
Part initial seal coat is removed using etching technics, forms separation layer, the top surface of the separation layer is lower than the fin
The top surface in portion, and the partial sidewall of fin is covered, during the etching removes part initial seal coat, etch the
The rate of one protective layer is less than the rate of the second protective layer of etching.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material packet of the initial seal coat
It includes: silica.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the initial isolation in etching removal part
During layer, it is removed at the top of the protection structure of part.
4. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the technique for forming separation layer includes:
Wet-etching technology；The parameter of the wet-etching technology includes: that etching agent includes hydrofluoric acid solution, the quality percentage of etching agent
Specific concentration is 0.1%~1%.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the process for forming the separation layer
In, the etching selection ratio of the first protective layer and the second protective layer are as follows: 10:1~200:1.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that first protective layer thickness are as follows: 2
Nanometer~30 nanometers.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step of the protection structure
It include: that mask layer is formed on the initial seal coat and fin, the mask layer has mask open, the mask open
Bottom-exposed goes out the top surface in the firstth area of fin part of initial seal coat and initial seal coat two sides；In the mask open
It is interior to form the protection structure.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that described along fin extending direction
The size of mask open are as follows: 32 nanometers~80 nanometers.
9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the material of the mask layer includes:
Amorphous silicon, titanium nitride or silicon nitride.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the mask layer includes
Amorphous silicon perhaps titanium nitride when first protective layer material include: silicon nitride, silicon oxynitride, carbonitride of silicium or nitrogen boron
SiClx；The material of second protective layer includes: silica.
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the mask layer is nitrogen
When SiClx, the material of first protective layer includes silica, in first protective layer have Doped ions, it is described adulterate from
Attached bag includes silicon ion or Nitrogen ion；The material of second protective layer includes silica.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the Doped ions are silicon ion
When, the atom percentage concentration of Doped ions in first protective layer are as follows: 34%~50%.
13. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the Doped ions are Nitrogen ion
When, the atom percentage concentration of Doped ions in first protective layer are as follows: 10%~25%.
14. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that mixed in first protective layer
The technique of the Doped ions includes: ion implantation technology.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the ginseng of the ion implantation technology
Number includes: the Doped ions when being silicon, and Implantation Energy is 1 kiloelectron-volt~20 kiloelectron-volts, and implantation dosage is
1.0E14atm/cm2~1.0E20atm/cm2, implant angle is 0 degree~45 degree.
16. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that form first protective layer
In the process, after the ion implantation technology, further includes: made annealing treatment to first protective layer.
17. the forming method of semiconductor structure as claimed in claim 16, which is characterized in that the ginseng of the annealing treating process
Number includes: that temperature is 800 degrees Celsius~1100 degrees Celsius, and the time is 0 second~100 seconds.
18. the forming method of semiconductor structure as described in claim 1, which is characterized in that formed after the separation layer, also
Include: in the protection structure formation replacement gate structure, the replacement gate structure be located at initial seal coat and initially every
In the firstth area of fin part of absciss layer two sides；It is developed across the gate structure in part firstth area of fin；Form the grid
After structure and replacement gate structure, epitaxial layer, the epitaxial layer are formed in the firstth area of fin of the gate structure two sides
The side wall of covering part replacement gate structure.
19. the forming method of semiconductor structure as claimed in claim 18, which is characterized in that the forming step of the epitaxial layer
It include: to be formed in the firstth area of fin of the gate structure two sides using the gate structure and replacement gate structure as exposure mask
Source and drain opening, the side wall of the source and drain opening and bottom expose substrate；The epitaxial layer is formed in the source and drain is open；
The material of the substrate includes: silicon；The formation process of the epitaxial layer includes epitaxial growth technology.
20. a kind of be formed by semiconductor structure using such as any one of claim 1 to 19 method characterized by comprising
Substrate, has fin in the substrate, the fin include several firstth areas and between adjacent firstth area second
Area has opening in the secondth area of the fin；
There is in the opening initial seal coat, there is protection structure on the initial seal coat, the protection structure includes: the
One protective layer and positioned at the first protective layer side wall second protection；
There is separation layer, the top surface of the separation layer is lower than the top surface of fin, and covers fin in the substrate
Partial sidewall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710442424.7A CN109148370B (en) | 2017-06-13 | 2017-06-13 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710442424.7A CN109148370B (en) | 2017-06-13 | 2017-06-13 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109148370A true CN109148370A (en) | 2019-01-04 |
| CN109148370B CN109148370B (en) | 2023-05-26 |
Family
ID=64829904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710442424.7A Active CN109148370B (en) | 2017-06-13 | 2017-06-13 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109148370B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491876A (en) * | 2019-08-23 | 2019-11-22 | 福建省晋华集成电路有限公司 | The manufacturing method of semiconductor memory component and the element |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140231924A1 (en) * | 2013-02-21 | 2014-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd | Method For Fabricating A Multi-Gate Device |
| CN104347717A (en) * | 2013-08-07 | 2015-02-11 | 三星电子株式会社 | Semiconductor device and method for fabricating same |
| US9564369B1 (en) * | 2015-10-21 | 2017-02-07 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices including device isolation processes |
| US20170133379A1 (en) * | 2015-10-06 | 2017-05-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
-
2017
- 2017-06-13 CN CN201710442424.7A patent/CN109148370B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140231924A1 (en) * | 2013-02-21 | 2014-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd | Method For Fabricating A Multi-Gate Device |
| CN104347717A (en) * | 2013-08-07 | 2015-02-11 | 三星电子株式会社 | Semiconductor device and method for fabricating same |
| US20170133379A1 (en) * | 2015-10-06 | 2017-05-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US9564369B1 (en) * | 2015-10-21 | 2017-02-07 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices including device isolation processes |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491876A (en) * | 2019-08-23 | 2019-11-22 | 福建省晋华集成电路有限公司 | The manufacturing method of semiconductor memory component and the element |
| CN110491876B (en) * | 2019-08-23 | 2024-04-05 | 福建省晋华集成电路有限公司 | Method for manufacturing semiconductor memory element and semiconductor memory element |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109148370B (en) | 2023-05-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103177950B (en) | Manufacture structure and the method for fin device | |
| CN105470132B (en) | The forming method of fin field effect pipe | |
| CN107919327A (en) | Semiconductor structure and forming method thereof | |
| CN105448914B (en) | Semiconductor structure and forming method thereof | |
| CN106486350B (en) | The forming method of semiconductor structure | |
| CN106816382A (en) | The fin structure and its manufacture method and the manufacture method of active region of semiconductor devices | |
| CN110517989A (en) | Semiconductor structure and forming method thereof | |
| CN106158747A (en) | Semiconductor structure and forming method thereof | |
| CN107591362A (en) | Semiconductor structure and forming method thereof | |
| US20160233105A1 (en) | Method of forming a trench in a semiconductor device | |
| CN109994547A (en) | Semiconductor devices and forming method thereof | |
| CN105261566B (en) | The forming method of semiconductor structure | |
| CN105448736B (en) | The forming method of transistor | |
| CN106449404B (en) | Semiconductor structure and forming method thereof | |
| CN106158637B (en) | Fin formula field effect transistor and forming method thereof | |
| CN106158638B (en) | Fin formula field effect transistor and forming method thereof | |
| CN109686702A (en) | Semiconductor structure and forming method thereof | |
| CN109148296A (en) | Semiconductor structure and forming method thereof | |
| CN109087861A (en) | Semiconductor devices and forming method thereof | |
| TWI596708B (en) | Coms structure and fabrication method thereof | |
| CN109148370A (en) | Semiconductor structure and forming method thereof | |
| CN106856208B (en) | Nanowire semiconductor device and forming method thereof | |
| CN103187286B (en) | The manufacture method of fin formula field effect transistor | |
| CN108122762B (en) | Semiconductor structure and forming method thereof | |
| CN109980003A (en) | Semiconductor devices and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |