CN106158638B - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN106158638B CN106158638B CN201510152381.XA CN201510152381A CN106158638B CN 106158638 B CN106158638 B CN 106158638B CN 201510152381 A CN201510152381 A CN 201510152381A CN 106158638 B CN106158638 B CN 106158638B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of fin formula field effect transistor and forming method thereof, the forming method of the fin formula field effect transistor includes: offer semiconductor substrate；Form hard mask layer；It is developed across the pseudo- grid structure of the hard mask layer, the side wall including dummy grid and positioned at dummy grid two sides；The dielectric layer that surface is flushed with pseudo- grid structure surface is formed on a semiconductor substrate, and dielectric layer covers hard mask layer and pseudo- grid structure side wall；Dummy grid is removed, the first groove is formed；Using the hard mask layer as semiconductor substrate described in mask etching, the first sub- fin is formed；The first metal-gate structures are formed in first groove；Side wall is removed, the second groove for being located at the first metal-gate structures two sides is formed；Using hard mask layer as semiconductor substrate described in mask etching, the second sub- fin is formed；The second metal-gate structures are formed in second groove.The performance for the fin formula field effect transistor to be formed can be improved in the above method.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of fin formula field effect transistor and forming method thereof.
Background technique
With the continuous development of semiconductor process technique, process node is gradually reduced, and rear grid (gate-last) technique obtains
It is widely applied, to obtain ideal threshold voltage, improves device performance.But when the characteristic size of device further declines
When, even if the structure of conventional metal-oxide-semiconductor field effect transistor also can no longer meet the demand to device performance, fin using rear grid technique
Formula field effect transistor (Fin FET) has obtained extensive concern as a kind of multi-gate device.
Fig. 1 shows a kind of schematic perspective view of fin formula field effect transistor of the prior art.
As shown in Figure 1, comprising: semiconductor substrate 10 is formed with the fin 20 of protrusion, fin in the semiconductor substrate 10
20 after etching to semiconductor substrate 10 generally by obtaining；Dielectric layer 30, cover the surface of the semiconductor substrate 10 with
And a part of the side wall of fin 20；Gate structure, across on the fin 20, cover the fin 20 atop part and
Side wall, gate structure include gate dielectric layer 41 and the grid 42 on gate dielectric layer.For fin formula field effect transistor, fin
The part that 20 top and the side wall of two sides are in contact with gate structure all becomes channel region, that is, has multiple grid, be conducive to
Increase driving current, improves device performance.The gate structure can be simultaneously across one or more fin.
The performance for the fin formula field effect transistor that the prior art is formed need further to improve.
Summary of the invention
Problems solved by the invention is to provide a kind of fin formula field effect transistor and forming method thereof, improves the fin of formation
The performance of field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: a kind of fin
The forming method of field effect transistor characterized by comprising semiconductor substrate is provided；Form covering part semiconductor substrate
The hard mask layer on surface；It is developed across the pseudo- grid structure of the hard mask layer, dummy gate structure covering part hard mask layer
Top and side wall, including dummy grid and the side wall for being located at dummy grid two sides；On the semiconductor substrate formed surface with
The dielectric layer that pseudo- grid structure surface flushes, the dielectric layer covering hard mask layer and pseudo- grid structure side wall；Dummy grid is removed, is formed
First groove exposes part semiconductor substrate and hard mask layer surface；Using the hard mask layer partly to be led described in mask etching
Body substrate forms the first sub- fin；The first metal-gate structures are formed in first groove；Side wall is removed, is formed and is located at the
Second groove of one metal-gate structures two sides, exposes part semiconductor substrate and hard mask layer surface；With the hard mask layer
For semiconductor substrate described in mask etching, the second sub- fin is formed；The second metal-gate structures are formed in second groove.
Optionally, the forming method of dummy gate structure includes: and is formed to cover hard exposure mask in the semiconductor substrate surface
After the dummy grid material layer of layer, the dummy grid material layer is patterned, the dummy grid of hard mask layer is developed across；?
Spacer material layer is formed in semiconductor substrate, and etches the spacer material layer, and formation is located at dummy grid two sides side wall table
The side wall in face.
Optionally, the material of the hard mask layer is silicon nitride, silica, titanium nitride or tantalum nitride.
Optionally, the material of the dummy grid is photoresist, polysilicon, amorphous silicon, silicon oxide carbide or amorphous carbon.
Optionally, the dummy grid material layer is formed using spin coating proceeding.
Optionally, the material of the side wall is silicon nitride or silica.
Optionally, more than two discrete and arranged in parallel hard mask layers are formed.
Optionally, the method for forming the dielectric layer include: the semiconductor substrate surface formed mask film covering layer with
And the layer of dielectric material of pseudo- grid structure；Using dummy gate structure as stop-layer, the layer of dielectric material is planarized, shape
At dielectric layer, flush the surface of the dielectric layer with pseudo- grid structure surface.
Optionally, the material of the dielectric layer is silica, silicon oxide carbide or silicon oxynitride.
Optionally, further includes: after forming dummy gate structure, to the semiconductor substrates of dummy gate structure two sides into
Row source and drain ion implanting forms source-drain electrode in the semiconductor substrate of pseudo- grid structure two sides.
Optionally, first metal-gate structures include the first gate dielectric layer and positioned at the first of first grid dielectric layer surface
Metal gates；Second metal-gate structures include the second gate dielectric layer and the second metal gate positioned at second gate dielectric layer surface
Pole.
Optionally, the material of first gate dielectric layer is hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide；
The material of second gate dielectric layer is hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide.
Optionally, different metal materials is respectively adopted in first metal gates, the second metal gates.
Optionally, the material of first metal gates is gold, silver, aluminium, tungsten or titanium；The material of second metal gates
For gold, silver, aluminium, tungsten or titanium.
Optionally, the dummy grid is removed using wet-etching technology or cineration technics.
Optionally, the side wall is removed using wet-etching technology.
Optionally, the method for removing the side wall includes: to carry out H to the side wall2Or He injection, wet process is then used again
Etching technics removes the side wall, and the etching solution that the wet-etching technology uses is hydrofluoric acid solution.
Optionally, H is carried out to the side wall using capacitive coupling ion implantation technology2Or He injection, bias supply power
For 0W~500W, pressure is 25mTorr~80mTorr, and the mass concentration of the hydrofluoric acid solution is 0.5%~2%.
Optionally, further includes: using semiconductor substrate as stop-layer, to the dielectric layer, the first metal-gate structures, second
Metal-gate structures and hard mask layer carry out planarization process, and removal is located at the dielectric layer of semiconductor substrate, part first
Metal-gate structures, the second metal-gate structures of part and hard mask layer expose semiconductor substrate, the first sub- fin and the second sub- fin
The top surface in portion.
To solve the above problems, technical solution of the present invention also provides a kind of fin field effect formed using the above method
Transistor, comprising: semiconductor substrate, the fin in semiconductor substrate；At the top of covering part semiconductor substrate and fin
The hard mask layer on surface；Across the metal-gate structures of the hard mask layer and fin, the metal-gate structures covering fin side wall,
The top of part hard mask layer and side wall, including the first metal-gate structures, the second metal positioned at the first metal-gate structures two sides
Grid structure；The dielectric layer flushed positioned at the semiconductor substrate surface with metal-gate structures surface, the dielectric layer covering are covered firmly
Film layer and metal-gate structures side wall.
Compared with prior art, technical solution of the present invention has the advantage that
In fin formula field effect transistor provided by technical solution of the present invention, hard exposure mask is formed on a semiconductor substrate
Layer, is then developed across the pseudo- grid structure of hard mask layer, dummy gate structure includes dummy grid, positioned at the side of dummy grid two sides
Wall；Then the dielectric layer that surface is flushed with pseudo- grid structure surface is formed on a semiconductor substrate；Then it removes dummy grid, forms the
Etch semiconductor substrates form the first sub- fin after one groove, and the first metal-gate structures are formed in the first groove；Side wall is removed,
Etch semiconductor substrates form the second sub- fin after forming the second groove, and the second metal-gate structures are formed in the second groove.On
The metal gate structure for stating the fin formula field effect transistor of method formation includes the first metal-gate structures, the second metal-gate structures,
Metal-gate structures can be improved for the control ability in the fin channel region of lower section, so that the fin field effect for improving formation is brilliant
The performance of body pipe.
Further, first metal-gate structures include the first gate dielectric layer and positioned at the first of first grid dielectric layer surface
Metal gates；Second metal-gate structures include the second gate dielectric layer and the second metal gate positioned at second gate dielectric layer surface
Pole.Different metal materials is respectively adopted in first metal gates, the second metal gates.It can make different metal gate knots
Structure has different work functions, and the control ability to channel region can be improved, and reduces Punchthrough electric current, also, can also
Improve the high-frequency work performance of fin formula field effect transistor.
Further, the method for removing the side wall includes: to carry out H to the side wall2Or He injection, wet process is then used again
Etching technics removes the side wall, and the etching solution that the wet-etching technology uses is hydrofluoric acid solution.To the side wall into
The above-mentioned H of row2Or the N-H quantity in the side wall can be improved in He ion implanting, and it is disconnected that the Si-N key in side wall is occurred
It splits, so that the etch rate of the side wall in a solution of hydrofluoric acid is improved, so as to use hydrofluoric acid solution to the side wall
Wet etching is carried out, and avoids etching using phosphoric acid solution, it can be to avoid the particle contamination and behaviour that phosphoric acid solution is easy to cause
Make safety problem.
Further, technical solution of the present invention provides a kind of fin formula field effect transistor, comprising: semiconductor substrate is located at
Fin in semiconductor substrate；The hard mask layer of covering part semiconductor substrate and fin top surface；It is covered firmly across described
The metal-gate structures of film layer and fin, the metal-gate structures covering fin side wall, the top of part hard mask layer and side wall, packet
Include the first metal-gate structures, the second metal-gate structures positioned at the first metal-gate structures two sides；Positioned at the semiconductor substrate table
The dielectric layer that face is flushed with metal-gate structures surface, the dielectric layer covering hard mask layer and metal-gate structures side wall.The gold
Metal gate structure includes the first metal-gate structures, the second metal-gate structures, and metal-gate structures can be improved for the fin ditch of lower section
The control ability in road region, to improve the performance of the fin formula field effect transistor of formation.
Further, first metal-gate structures include the first gate dielectric layer and positioned at the first of first grid dielectric layer surface
Metal gates；Second metal-gate structures include the second gate dielectric layer and the second metal gate positioned at second gate dielectric layer surface
Pole.Different metal materials is respectively adopted in first metal gates, the second metal gates.It can make different metal gate knots
Structure has different work functions, and the control ability to channel region can be improved, and reduces Punchthrough electric current, also, can also
Improve the high-frequency work performance of fin formula field effect transistor.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for the fin formula field effect transistor that the prior art of the invention is formed；
Fig. 2 to Figure 22 is the structural schematic diagram of the forming process of fin formula field effect transistor of the invention.
Specific embodiment
The usual gate dielectric layer 41 (please referring to Fig. 1) of gate structure for the fin formula field effect transistor that the prior art is formed and position
In the grid 42 (please referring to Fig. 1) on gate dielectric layer, wherein gate dielectric layer 41 generallys use high K dielectric material, such as hafnium oxide,
Zirconium oxide, lanthana or aluminium oxide etc.；And grid 42 is generally using metal material, such as tungsten, gold, aluminium or silver etc..The prior art
Grid 42 generally formed using a kind of metal material, work function is more single, leads to control of the gate structure to channel region
Power is inadequate, and the fin field effect crystal often will appear Punchthrough current leakage, and fin formula field effect transistor
High-frequency work performance need further to improve.
In the embodiment of the present invention, being formed has the fin field effect of the first metal-gate structures, the second metal-gate structures brilliant
Metal-gate structures can be improved for the control ability in the fin channel region of lower section in body pipe, to improve the fin field of formation
The performance of effect transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to FIG. 2, providing semiconductor substrate 100, the hard mask layer on 100 surface of covering part semiconductor substrate is formed
101。
The material of the semiconductor substrate 100 includes the semiconductor materials such as silicon, germanium, SiGe, GaAs, the semiconductor
Substrate 100 can be body material and be also possible to composite construction such as silicon-on-insulator.Those skilled in the art can be according to partly leading
The semiconductor devices formed in body substrate 100 selects the type of the semiconductor substrate 100, therefore the semiconductor substrate 100
Type should not limit the scope of the invention.In the present embodiment, the semiconductor substrate 100 is monocrystalline substrate.
The material of the hard mask layer 101 can be the dielectrics mask material such as silicon nitride or silica, can also be
The metal masks material such as titanium nitride or tantalum nitride.The method for forming the hard mask layer 101 includes: in the semiconductor substrate
100 surfaces are formed after hardmask material, photoresist layer are formed in the hard mask material layer surface, to the photoresist layer
It is exposed development, forms graphical photoresist layer；Using the graphical photoresist layer as hard mask material described in mask etching
Layer, forms the hard mask layer 101；Remove the graphical photoresist layer.The hard mask layer 101 is strip, described hard
The width of mask layer 101 is corresponding with the fin width for the fin formula field effect transistor being subsequently formed.The hard mask layer 101 has
Certain thickness, it is subsequent after forming fin, it can be to playing enough protective effects at the top of fin.In the present embodiment,
The hard mask layer 101 with a thickness of 10nm~100nm.
In the present embodiment, to form two hard mask layers 101 arranged in parallel as an example, in other implementations of the invention
In example, one or more discrete and arranged in parallel hard mask layer 101 can also be only formed.
Fig. 3 and Fig. 4 are please referred to, the pseudo- grid structure 200 of the hard mask layer 101 is developed across, dummy gate structure 200 is covered
The top of cover hard mask layer 101 and side wall, including dummy grid 201 and the side wall 202 for being located at 201 two sides of dummy grid.
Wherein, Fig. 3 is the schematic perspective view to form dummy gate structure 200, and Fig. 4 is the cross-sectional side view of the secant AA ' along Fig. 3
Figure.Secant AA ' is parallel to the length direction of hard mask layer 101, between adjacent hard mask layer 101.
The forming method of dummy gate structure 200 includes: to form covering hard mask layer on 100 surface of semiconductor substrate
After 101 dummy grid material layer, the dummy grid material layer is patterned, is developed across the pseudo- grid of hard mask layer 101
Pole 201；Spacer material layer is formed on a semiconductor substrate 100, and etches the spacer material layer, and formation is located at dummy grid
The side wall 202 of 201 two sides sidewall surfaces.
The material of the dummy grid 201 is photoresist, polysilicon, amorphous silicon, silicon oxide carbide or amorphous carbon.It can use
Spin coating proceeding forms the dummy grid material layer.The material of the dummy grid material layer is different from the material of hard mask layer 101, makes
Must be subsequent when being patterned to dummy grid material layer, there are larger between the dummy grid material layer and hard mask layer 101
Etching selection ratio, avoid that hard mask layer 101 is caused to damage.In the present embodiment, the material of the dummy grid 201 is oxidation of coal
Silicon.In other embodiments of the invention, the dummy grid material layer can also be formed using chemical vapor deposition process.
The dummy grid material layer can be patterned using dry etch process, to form the dummy grid 201.
The dry etch process can be using including CF4、C2F3、NF3Or SF6Equal fluoro-gas are as etching gas.Of the invention
In other embodiments, the material of the dummy grid material layer is photoresist, can directly be exposed to the dummy grid material layer
Photodevelopment forms the dummy grid 201.The dummy grid 201 is subsequent to be substituted by the first metal-gate structures, so the dummy grid
201 size is consistent with the first metal-gate structures size to be formed.
The material of the side wall 202 is silicon nitride or silica.The material of the side wall 202 and the material of hard mask layer 101
Material is different, so that it is subsequent when the opposite side walling bed of material is patterned, exist between the spacer material layer and hard mask layer 101
Biggish etching selection ratio avoids causing to damage to hard mask layer 101.The side wall 202 is subsequent to be replaced by the second metal-gate structures
Generation, so the size of the side wall 202 is consistent with the size of the second metal-gate structures to be formed.
The width of the dummy grid 201 is 1~3 times of 202 width of side wall, so that the first metal gate being subsequently formed
The width of structure is 1~3 times of the second metal-gate structures width.It in other embodiments of the invention, can be according to device
It can need, the width ratio of adjustment dummy grid 201, side wall 202.It, can be with by changing the dummy grid 201,202 width of side wall
The first metal-gate structures being subsequently formed, the second metal-gate structures are adjusted to the control ability of the channel region of respective lower section, with
And work function value.
It in other embodiments of the invention, can also be to dummy gate structure after forming dummy gate structure 200
The semiconductor substrate of two sides carries out source and drain ion implanting, forms source-drain electrode in the semiconductor substrate of pseudo- grid structure two sides, described
The Doped ions of source and drain ion implanting can be N-type or p-type Doped ions, the type with fin formula field effect transistor to be formed
Unanimously.
Fig. 5 to Fig. 6 is please referred to, forms Jie that surface is flushed with 200 surface of pseudo- grid structure in the semiconductor substrate 100
Matter layer 300, the dielectric layer 300 cover hard mask layer 101 (please referring to Fig. 3) and 200 side wall of pseudo- grid structure.Fig. 5 is forms
The stereoscopic schematic diagram after dielectric layer 300 is stated, Fig. 6 is the diagrammatic cross-sectional side elevation of the secant AA ' along Fig. 5.
The method for forming the dielectric layer 300 includes: to form mask film covering layer 101 on 100 surface of semiconductor substrate
And the layer of dielectric material of pseudo- grid structure 200；Using dummy gate structure 200 as stop-layer, the layer of dielectric material is carried out
Planarization forms dielectric layer 300, flushes the surface of the dielectric layer 300 with 200 surface of pseudo- grid structure.
The material of the layer of dielectric material is silica, silicon oxide carbide or silicon oxynitride, can use spin coating or chemical gas
Phase depositing operation forms the layer of dielectric material.In the present embodiment, the material of the layer of dielectric material is silica, using chemistry
Gas-phase deposition forms the layer of dielectric material.The surface of the layer of dielectric material is higher than the surface of pseudo- grid structure 200.It can be with
The layer of dielectric material is planarized using chemical mechanical milling tech, makes 300 surface of dielectric layer to be formed and pseudo- grid knot
200 surface of structure flushes, and exposes the top surface of dummy grid 201, side wall 202, convenient for the subsequent removal dummy grid 201, side
Wall 202.
Fig. 7 to Fig. 9 is please referred to, is removed dummy grid 201 (please referring to Fig. 5), the first groove 301 is formed, exposes part half
101 surface of conductor substrate 100 and hard mask layer.Fig. 8 is the stereoscopic schematic diagram after the removal dummy grid 201, and Fig. 8 is along figure
The diagrammatic cross-sectional side elevation of secant AA ' in 7, Fig. 9 are the schematic top plan view after the removal dummy grid 201.
The dummy grid 201 can be removed using wet-etching technology or cineration technics, it can be to avoid using dry etching
During removing dummy grid 201, plasma causes to damage to semiconductor substrate 100 and hard mask layer 101.The wet process
Etching technics selection has more highly selective etching solution to dummy grid 201, avoids in etching process to dielectric layer 300, side
Wall 202 and semiconductor substrate 100, hard mask layer 101 cause to damage.
After removing the dummy grid 201, the first groove 301 is formed between side wall 202, first groove 301 is sudden and violent
The surface of exposed portion hard mask layer 101, and the surface of part semiconductor substrate 100 not covered by hard mask layer 101.
Figure 10 to Figure 11 is please referred to, is semiconductor substrate 100 described in mask etching with the hard mask layer 101, forms the
One sub- fin 102a.Figure 11 is the diagrammatic cross-sectional side elevation of the secant AA ' along Figure 10.
The semiconductor that 301 bottom of the first groove is not covered by hard mask layer 101 is etched using dry etch process to serve as a contrast
Bottom 100 forms the first sub- fin 102a for being located at 101 lower section of hard mask layer.In the present embodiment, the dry etch process is etc.
Plasma etching technique, the etching gas that the plasma etch process uses is HBr and Cl2Mixed gas as etching
Gas, O2As buffer gas, wherein the flow of HBr is 50sccm~1000sccm, Cl2Flow be 50sccm~
1000sccm, O2Flow be 5sccm~20sccm, pressure be 5mTorr~50mTorr, power be 400W~750W, O2Gas
Body flow is 5sccm~20sccm, and temperature is 40 DEG C~80 DEG C, and bias voltage is 100V~250V.Above-mentioned plasma etching
Technique can carry out anisotropy quarter to the semiconductor substrate 100 to the Etch selectivity with higher of semiconductor substrate 100
Erosion.During etching semiconductor substrate 100 of 301 bottom of the first groove, the side wall 202 and dielectric layer 300
The semiconductor substrate 100 in other regions is protected, so that the first sub- fin 102a is only formed below the first groove 301,
So that the depth of the first groove 301 increases.
The width of the first sub- fin 102a is determined by the width of hard mask layer 101, in the present embodiment, the first of formation
The side wall of sub- fin 102a is vertical with 100 surface of semiconductor substrate, in other embodiments of the invention, the first sub- fin
102a can also have sloped sidewall, so that the bottom width of the first sub- fin 102a is less than top width.
Figure 12 to Figure 13 is please referred to, forms the first metal-gate structures in first groove 301 (please referring to Figure 10)
401.Figure 12 is the schematic perspective view to be formed after the first metal-gate structures 401, and Figure 13 is that secant AA ' is cutd open along Figure 12
Face schematic side view.
First metal-gate structures 401 fill full first groove 301, the hard exposure mask in first groove 301
Layer 101 and the first sub- fin 102a, cover the side wall of the first sub- fin 102a and side wall and the top of hard mask layer 101.
First metal-gate structures 401 include the first gate dielectric layer and the first metal positioned at first grid dielectric layer surface
Grid.The material of first gate dielectric layer is the high K dielectrics materials such as hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide
Material.The material of first metal gates is the metal gate materials such as gold, silver, aluminium, tungsten or titanium.In the present embodiment, described first
The material of gate dielectric layer is hafnium oxide, and the material of first metal gates is silver.
The forming method of first metal-gate structures 401 includes: in 301 inner wall surface of the first groove, side wall 202
And 300 surface of dielectric layer forms first grid layer of dielectric material；Filling full the is formed in the first grid dielectric material layer surface
First metal gate material layer of one groove 301；Using the dielectric layer 300 as stop-layer, to the first metal gates material
The bed of material and first grid layer of dielectric material carry out planarization process, form the first metal-gate structures being located in the first groove 301
401, the surface of first metal-gate structures 401 is flushed with the surface of dielectric layer 300.
In the present embodiment, first metal-gate structures 401 cover the simultaneously across two the first sub- fin 102a
The side wall of one sub- fin 102a, part channel of the sidewall surfaces of the first sub- fin 102a as fin formula field effect transistor
Region, by the control of the first metal-gate structures 401, the channel region positioned at the described first sub- fin 102a sidewall surfaces is opened
Opening the properties such as the work function by first metal-gate structures 401 such as threshold voltage and switching frequency is influenced.
Figure 14 to Figure 15 is please referred to, is removed side wall 202 (please referring to Figure 12), the second groove 302 is formed, exposes part half
The surface of conductor substrate 100 and hard mask layer 101.
The side wall 202 can be removed using wet-etching technology, it can be to avoid using dry etching removal side wall 202
In the process, plasma causes to damage to semiconductor substrate 100 and hard mask layer 101.
The wet-etching technology selection has more highly selective etching solution to side wall 202, avoids in etching process
Dielectric layer 300, semiconductor substrate 100, hard mask layer 101 are caused to damage.In the present embodiment, the material of the side wall 202 is
Silicon nitride, the wet-etching technology can be using phosphoric acid solutions as etching solution.
It in other embodiments of the invention, can be in the guarantor for forming blanket dielectric layer 300, the first metal-gate structures 401
After sheath, H is carried out to the side wall 2022Or He ion implanting, the side wall is then removed using wet-etching technology again
202, the etching solution that the wet-etching technology uses is hydrofluoric acid solution.
Specifically, H can be carried out to the side wall 202 using capacitive coupling ion implantation technology2Or He injection, biased electrical
Source power is 0W~500W, and pressure is 25mTorr~80mTorr.During the wet etching, the matter of the hydrofluoric acid solution
Measuring concentration is 0.5%~2%.
Above-mentioned H is carried out to the side wall 2022Or the N-H quantity in the side wall 202 can be improved in He ion implanting, and
And the Si-N key in side wall 202 is broken, so that the etch rate of the side wall 202 in a solution of hydrofluoric acid is improved,
To carry out H in the side wall 2022Or after He ion implanting, can using hydrofluoric acid solution to the side wall 202 into
Row wet etching, and avoid removing the side wall 202 using phosphoric acid solution etching.Due to carrying out wet process quarter using phosphoric acid solution
Erosion, it will usually lead to particle contamination problems, and phosphoric acid solution usually requires 140 DEG C~180 DEG C or so in etching process
High temperature is easy to cause operating safety.So carrying out above-mentioned H to side wall 202 using the above method2Or He ion implanting it
Afterwards, then using hydrofluoric acid solution side wall 202 is removed, it can be to avoid using problem caused by phosphoric acid solution.
After removing the side wall 202, the second groove is formed between dielectric layer 300 and the first metal-gate structures 401
302, second groove 302 exposes the surface of part hard mask layer 101, and the part not covered by hard mask layer 101
The surface of semiconductor substrate 100.
Figure 16 to Figure 17 is please referred to, is semiconductor substrate 100 described in mask etching with the hard mask layer 101, forms the
Two sub- fin 102b.Figure 17 is the diagrammatic cross-sectional side elevation of the secant AA ' along Figure 16.
The semiconductor that 302 bottom of the second groove is not covered by hard mask layer 101 is etched using dry etch process to serve as a contrast
Bottom 100 forms the second sub- fin 102b for being located at 101 lower section of hard mask layer.In the present embodiment, the dry etch process is etc.
Plasma etching technique, the etching gas that the plasma etch process uses is HBr and Cl2Mixed gas as etching
Gas, O2As buffer gas, wherein the flow of HBr is 50sccm~1000sccm, Cl2Flow be 50sccm~
1000sccm, O2Flow be 5sccm~20sccm, pressure be 5mTorr~50mTorr, power be 400W~750W, O2Gas
Body flow is 5sccm~20sccm, and temperature is 40 DEG C~80 DEG C, and bias voltage is 100V~250V.Above-mentioned plasma etching
Technique can carry out anisotropy quarter to the semiconductor substrate 100 to the Etch selectivity with higher of semiconductor substrate 100
Erosion.During etching semiconductor substrate 100 of 302 bottom of the second groove, first metal-gate structures 401, with
And dielectric layer 300 protects the semiconductor substrate 100 in other regions, to only form second below the second groove 302
Sub- fin 102b, so that the depth of the second groove 302 increases.
The width of the second sub- fin 102b is determined by the width of hard mask layer 101, in the present embodiment, the second of formation
The side wall of sub- fin 102b is vertical with 100 surface of semiconductor substrate, in other embodiments of the invention, the second sub- fin
102b can also have sloped sidewall, so that the bottom width of the second sub- fin 102b is less than top width.
Figure 18 to Figure 20 is please referred to, forms the second metal-gate structures in second groove 302 (please referring to Figure 16)
402.Figure 19 is the diagrammatic cross-sectional side elevation of the secant AA ' along Figure 18, and Figure 20 is the diagrammatic cross-section of the secant BB ' along Figure 18,
Secant BB ' is parallel to the length direction of hard mask layer 101, is located at 101 position of hard mask layer.
Second metal-gate structures 402 fill full second groove 302, the hard exposure mask in second groove 302
Layer 101 and the second sub- fin 102b, cover the side wall of the second sub- fin 102b and side wall and the top of hard mask layer 101.
Second metal-gate structures 402 include the second gate dielectric layer and the second metal positioned at second gate dielectric layer surface
Grid.The material of second gate dielectric layer is the high K dielectrics materials such as hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide
Material.The material of second metal gates is the metal gate materials such as gold, silver, aluminium, tungsten or titanium.In the present embodiment, described second
The material of gate dielectric layer is hafnium oxide, and the material of second metal gates is gold.
The forming method of second metal-gate structures 402 includes: in 302 inner wall surface of the second groove, the first gold medal
Metal gate structure 401 and 300 surface of dielectric layer form second gate layer of dielectric material；In the second gate dielectric material layer surface
Form the second metal gate material layer for filling full second groove 302；Using the dielectric layer 300 as stop-layer, to described
Two metal gate material layers and second gate layer of dielectric material carry out planarization process, form second be located in the second groove 302
The surface of metal-gate structures 402, second metal-gate structures 402 is flushed with the surface of dielectric layer 300.
In the present embodiment, second metal-gate structures 402 cover the simultaneously across two the second sub- fin 102b
The side wall of two sub- fin 102b, part channel of the sidewall surfaces of the second sub- fin 102b as fin formula field effect transistor
Region, by the control of the second metal-gate structures 402, the channel region positioned at the described second sub- fin 102b sidewall surfaces is opened
Opening the properties such as the work function by the second metal-gate structures 402b such as threshold voltage and switching frequency is influenced.
In the present embodiment, the second metal gate material of second metal-gate structures 402 and the first metal-gate structures 401
The first metal gates material it is different, so, second metal-gate structures 402 and the first metal-gate structures 401 are not with
Same work function has different control abilities to the channel region of respective lower section.It can be adjusted according to the performance requirement of device
The material of second metal gates, the first metal gates in second metal-gate structures 402 and the first metal-gate structures 401.
In the present embodiment, the material of the first metal gates of the first metal-gate structures 401 and the second metal-gate structures 402
Second metal gate material is different, so, first metal-gate structures 401, the second metal-gate structures 402 have different function
Function has different control abilities to the channel region of respective lower section.Described the can be adjusted according to the performance requirement of device
The material of second metal gates, the first metal gates in two metal-gate structures 402 and the first metal-gate structures 401.
The first sub- fin 102a, the second sub- fin 102b constitute the fin of fin formula field effect transistor, and described the
One metal-gate structures 401, the second metal-gate structures 402 constitute the metal-gate structures of fin formula field effect transistor, also, described the
One metal-gate structures 401, the second metal-gate structures 402 are covered each by the side wall of the first sub- fin 102a, the second sub- fin 102b,
The channel region of the sidewall surfaces of the first sub- fin 102a, the second sub- fin 102b is controlled respectively.First metal
Different metal materials is respectively adopted as metal gate material in grid structure 401, the second metal-gate structures 402, can make not
Same metal-gate structures have different work functions, and the control ability to channel region can be improved, and reduce Punchthrough electric current,
Also, the high-frequency work performance of fin formula field effect transistor can also be improved.
Figure 21 to 22 is please referred to, using 100 surface of semiconductor substrate as stop-layer, (figure is please referred to the dielectric layer 300
20), the first metal-gate structures 401, the second metal-gate structures 402 and hard mask layer 101 (please referring to Figure 20) are planarized
Processing, removal are located at dielectric layer 300, the first metal-gate structures of part 401, the second metal of part of 100 top of semiconductor substrate
Grid structure 402 and hard mask layer 101 expose the top of semiconductor substrate 100, the first sub- fin 102a, the second sub- fin 102b
Portion surface.Figure 22 is the diagrammatic cross-sectional side elevation of the secant AA ' along Figure 21.Divide the first sub- fin with dotted line in Figure 21
The sub- fin 102b of 102a and second.
Positioned at the first sub- fin 102a, the second sub- fin 102b and the first metal-gate structures 401, the second metal gate knot
Source-drain electrode of the semiconductor substrate 100 of 402 two sides of structure as fin formula field effect transistor.
Above-mentioned planarization process can be carried out by chemical machinery masking process, expose the 100, first son of semiconductor substrate
The top surface of fin 102a, the second sub- fin 102b, convenient for subsequent in the source-drain electrode and metal gate structure surface shape
At metal interconnection structure.
It in other embodiments of the invention, can also be without above-mentioned planarization process.
In the embodiment of the present invention, a kind of fin formula field effect transistor formed using the above method is also provided.
Figure 18 to 20 is please referred to, is the structural schematic diagram of the fin formula field effect transistor, wherein Figure 19 is along Figure 18
The diagrammatic cross-sectional side elevation of secant AA ', Figure 20 are the diagrammatic cross-section of the secant BB ' along Figure 18.
The fin formula field effect transistor includes: semiconductor substrate 100, the fin in semiconductor substrate 100；Covering
The hard mask layer 101 of part semiconductor substrate 100 and fin top surface；Across the gold of the hard mask layer 101 and fin
Metal gate structure, the metal-gate structures covering fin side wall, the top of part hard mask layer 101 and side wall, including the first metal
Grid structure 401, the second metal-gate structures 402 positioned at 401 two sides of the first metal-gate structures；Positioned at the semiconductor substrate 100
The dielectric layer 300 that surface is flushed with metal-gate structures surface, the dielectric layer 300 cover hard mask layer 101 and metal-gate structures
Side wall.
The fin includes the first sub- fin 102a, the second sub- fin 102b, first metal-gate structures 401 covering the
The side wall of one sub- fin 102a, the second metal-gate structures 402 cover the side wall of the second sub- fin 102b.
First metal-gate structures 401 include the first gate dielectric layer and the first metal positioned at first grid dielectric layer surface
Grid.The material of first gate dielectric layer is the high K dielectrics materials such as hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide
Material.The material of first metal gates is the metal gate materials such as gold, silver, aluminium, tungsten or titanium.In the present embodiment, described first
The material of gate dielectric layer is hafnium oxide, and the material of first metal gates is silver.
Second metal-gate structures 402 include the second gate dielectric layer and the second metal positioned at second gate dielectric layer surface
Grid.The material of second gate dielectric layer is the high K dielectrics materials such as hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide
Material.The material of second metal gates is the metal gate materials such as gold, silver, aluminium, tungsten or titanium.In the present embodiment, described second
The material of gate dielectric layer is hafnium oxide, and the material of second metal gates is gold.
The material of the hard mask layer 101 is silicon nitride, silica, titanium nitride or tantalum nitride.The hard mask layer 101 is
Strip.
The material of the dielectric layer 300 is silica, silicon oxide carbide or silicon oxynitride.
The fin formula field effect transistor further includes the source and drain in the semiconductor substrate 100 of metal-gate structures two sides
Pole.
In the metal-gate structures of the fin formula field effect transistor, first metal-gate structures 401, the second metal gate knot
Different metal materials is respectively adopted as metal gate material in structure 402, and different metal-gate structures can be made to have difference
Work function, can be improved the control ability to channel region, reduce Punchthrough electric current, also, fin field can also be improved
The high-frequency work performance of effect transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Semiconductor substrate is provided；
Form the hard mask layer of covering part semiconductor substrate surface；
It is developed across the pseudo- grid structure of the hard mask layer, the top of dummy gate structure covering part hard mask layer and side wall,
Including dummy grid and the side wall for being located at dummy grid two sides；
The dielectric layer that surface is flushed with pseudo- grid structure surface is formed on the semiconductor substrate, and the dielectric layer covers hard exposure mask
Layer and pseudo- grid structure side wall；
Dummy grid is removed, the first groove is formed, exposes part semiconductor substrate and hard mask layer surface；
Using the hard mask layer as semiconductor substrate described in mask etching, the first sub- fin is formed；
The first metal-gate structures are formed in first groove；
Side wall is removed, the second groove for being located at the first metal-gate structures two sides is formed, part semiconductor substrate is exposed and covers firmly
Film surface；
Using the hard mask layer as semiconductor substrate described in mask etching, the second sub- fin is formed；
The second metal-gate structures are formed in second groove.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that dummy gate structure
Forming method includes: after the dummy grid material layer that the semiconductor substrate surface forms covering hard mask layer, to the puppet
Gate material layers are patterned, and are developed across the dummy grid of hard mask layer；Spacer material layer is formed on a semiconductor substrate, and
The spacer material layer is etched, the side wall for being located at dummy grid two sides sidewall surfaces is formed.
3. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the hard mask layer
Material is silicon nitride, silica, titanium nitride or tantalum nitride.
4. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the material of the dummy grid
Material is photoresist, polysilicon, amorphous silicon, silicon oxide carbide or amorphous carbon.
5. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that use spin coating proceeding shape
At the dummy grid material layer.
6. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the material of the side wall
For silicon nitride or silica.
7. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that form more than two points
Vertical and hard mask layer arranged in parallel.
8. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that form the dielectric layer
Method include: to form the layer of dielectric material of mask film covering layer and pseudo- grid structure in the semiconductor substrate surface；With described
Pseudo- grid structure planarizes the layer of dielectric material as stop-layer, forms dielectric layer, make the surface of the dielectric layer with
Pseudo- grid structure surface flushes.
9. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the material of the dielectric layer
Material is silica, silicon oxide carbide or silicon oxynitride.
10. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that further include: it is being formed
After dummy gate structure, source and drain ion implanting is carried out to the semiconductor substrate of dummy gate structure two sides, in pseudo- grid structure two
Source-drain electrode is formed in the semiconductor substrate of side.
11. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first metal
Grid structure includes the first gate dielectric layer and the first metal gates positioned at first grid dielectric layer surface；Second metal-gate structures
Including the second gate dielectric layer and positioned at the second metal gates of second gate dielectric layer surface.
12. the forming method of fin formula field effect transistor according to claim 11, which is characterized in that the first grid is situated between
The material of matter layer is hafnium oxide, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide；The material of second gate dielectric layer is oxygen
Change hafnium, zirconium oxide, lanthana, aluminium oxide or silicon hafnium oxide.
13. the forming method of fin formula field effect transistor according to claim 11, which is characterized in that first metal
Different metal materials is respectively adopted in grid, the second metal gates.
14. the forming method of fin formula field effect transistor according to claim 13, which is characterized in that first metal
The material of grid is gold, silver, aluminium, tungsten or titanium；The material of second metal gates is gold, silver, aluminium, tungsten or titanium.
15. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that use wet etching
Technique or cineration technics remove the dummy grid.
16. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that use wet etching
Technique removes the side wall.
17. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that remove the side wall
Method include: to the side wall carry out H2Or He injection, the side wall is then removed using wet-etching technology again, it is described wet
The etching solution that method etching technics uses is hydrofluoric acid solution.
18. the forming method of fin formula field effect transistor according to claim 17, which is characterized in that use capacitive coupling
Ion implantation technology carries out H to the side wall2Or He injection, bias supply power be 0W~500W, pressure be 25mTorr~
80mTorr, the mass concentration of the hydrofluoric acid solution are 0.5%~2%.
19. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that further include: partly to lead
Body substrate carries out the dielectric layer, the first metal-gate structures, the second metal-gate structures and hard mask layer flat as stop-layer
Smoothization processing, removal are located at dielectric layer, the first metal-gate structures of part, the second metal-gate structures of part of semiconductor substrate
And hard mask layer, expose the top surface of semiconductor substrate, the first sub- fin and the second sub- fin.
20. it is a kind of according to claim 1 to the fin formula field effect transistor that any claim the method in 19 is formed, it is special
Sign is, comprising:
Semiconductor substrate, the fin in semiconductor substrate；
The hard mask layer of covering part semiconductor substrate and fin top surface；
Across the metal-gate structures of the hard mask layer and fin, the metal-gate structures cover fin side wall, the hard exposure mask in part
The top of layer and side wall, including the first metal-gate structures, the second metal-gate structures positioned at the first metal-gate structures two sides；
The dielectric layer flushed positioned at the semiconductor substrate surface with metal-gate structures surface, the dielectric layer cover hard mask layer
With metal-gate structures side wall.
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| CN111640665B (en) * | 2019-03-01 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111863592B (en) * | 2019-04-29 | 2023-11-10 | 中芯国际集成电路制造(上海)有限公司 | Post-polish cleaning method and method for forming semiconductor structure |
| CN112750702B (en) * | 2019-10-31 | 2024-04-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN112507491B (en) * | 2020-12-14 | 2022-12-30 | 泉芯集成电路制造(济南)有限公司 | Parameterized unit of fin field effect transistor and implementation method thereof |
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| CN103972177A (en) * | 2013-01-25 | 2014-08-06 | 瑞萨电子株式会社 | Manufacturing method of semiconductor device |
| CN104425279A (en) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor, forming method of fin type field effect transistor and semiconductor device |
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