CN104425279A - Fin type field effect transistor, forming method of fin type field effect transistor and semiconductor device - Google Patents
Fin type field effect transistor, forming method of fin type field effect transistor and semiconductor device Download PDFInfo
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- 239000000463 material Substances 0.000 claims description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 51
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a fin type field effect transistor, a forming method of the fin type field effect transistor and a semiconductor device, wherein the forming method of the fin type field effect transistor comprises the following steps that a substrate is provided, a pseudo grate electrode is formed on the substrate, a source electrode and a drain electrode are formed in the substrate formed at the two sides of the pseudo grate electrode, an interlayer medium layer is formed on the substrate, and the upper surface of the interlayer medium layer is aligned with the upper surface of the pseudo grate electrode; the pseudo grate electrode is removed for forming a pseudo grate groove in the interlayer medium layer; the substrate part of the bottom of the pseudo grate groove is subjected to graphical processing, a fin part is formed between the source electrode and the drain electrode, and the two ends of the fin part are respectively connected with the source electrode and the drain electrode; a grate electrode and a high-K grade medium layer transversely spanning across the pin part are formed in the pseudo grate groove. According to the technical scheme, the pseudo grate electrode is firstly formed, then, the fin part is formed, the influence of the height of the fin part on the height of the grate electrode in the pseudo grate electrode forming process is avoided, the goal of accurately positioning the grate electrode height is achieved, the grate electrode height basically conforms to the predefined height, and the signal transmission in the fin type field effect transistor is reliable.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of fin formula field effect transistor and forming method thereof, semiconductor device.
Background technology
In technical field of semiconductors, along with the characteristic size of integrated circuit constantly reduces, and the requirement to the higher signal transmission speed of integrated circuit, transistor needs while size reduces gradually, have higher drive current.For complying with this requirement, prior art proposes fin formula field effect transistor.
Fin formula field effect transistor (FinFET) comprising: be positioned at suprabasil fin; Across the grid of fin; Be arranged in the source electrode of grid both sides fin, drain electrode, be spaced from each other between source electrode and grid, between drain electrode and grid.Compared to CMOS transistor, fin formula field effect transistor is for being positioned at suprabasil similar stereochemical structure, and its characteristic size is less, more can meet the requirement of high integration.And, the grid of fin formula field effect transistor is relative with the upper surface of fin, and the sidewall surfaces that grid is relative with two of fin is also relative, then operationally, the sidewall surfaces relative with two with the upper surface of the fin of gate contact all can form channel region, which improves the mobility of charge carrier.
Due to the plurality of advantages of fin formula field effect transistor, more and more research is also obtained to its formation method.
Below, the existing formation method with the fin formula field effect transistor of metal gates is simply introduced:
With reference to Fig. 1, provide substrate 10, be formed with insulating barrier 20 on the substrate 10, insulating barrier 20 is formed fin 30, insulating barrier 20 plays insulation buffer action;
With reference to Fig. 2, insulating barrier 20 forms polysilicon layer 40, be positioned at polysilicon layer 40 upper surface on insulating barrier 20 higher than fin 30 upper surface;
With reference to Fig. 3, cmp (Chemical Mechanical Planarization, CMP) polysilicon layer 40, make polysilicon layer 40 upper surface smooth, smooth, CMP is carried out also for regulating the height of polysilicon layer 40 to polysilicon layer 40, accordingly, the adjustment to metal gates height is realized;
With reference to Fig. 4, to polysilicon layer 40(with reference to Fig. 3) carry out graphical, form polysilicon layer across fin 30 as dummy grid 41, afterwards, in the fin of dummy grid 41 both sides, carry out ion doping respectively, form source electrode, drain electrode (not shown) at fin two ends respectively;
With reference to Fig. 5, insulating barrier 20 is formed interlayer dielectric layer 50, and interlayer dielectric layer 50 upper surface and dummy grid upper surface remain basically stable; Afterwards, remove dummy grid and form pseudo-gate groove, in pseudo-gate groove, fill metal gates 42.
But the performance of the fin formula field effect transistor using prior art to be formed is not good.
Summary of the invention
The problem that the present invention solves is, the performance of the fin formula field effect transistor using prior art to be formed is not good.
For solving the problem, the invention provides a kind of formation method of fin formula field effect transistor, the formation method of this fin formula field effect transistor comprises:
Substrate is provided, is formed with dummy grid on the substrate;
Source electrode, drain electrode is formed in the substrate of described dummy grid both sides;
Form interlayer dielectric layer on the substrate, described interlayer dielectric layer upper surface and dummy grid upper surface maintain an equal level;
Remove described dummy grid, in described interlayer dielectric layer, form pseudo-gate groove;
Carry out graphically to the base part bottom described pseudo-gate groove, between described source electrode and drain electrode, form fin, described fin two ends connect source electrode, drain electrode respectively;
The high-K gate dielectric layer across fin and the grid be positioned on high-K gate dielectric layer is formed in described pseudo-gate groove.
Alternatively, the formation method of described dummy grid comprises:
Form dummy grid material layer on the substrate;
Carry out graphically, forming dummy grid on the substrate to described dummy grid material layer.
Alternatively, the material of described dummy grid is polysilicon or amorphous carbon.
Alternatively, before the described dummy grid of formation, form mask lines on the substrate, described mask lines covers the base part of source electrode, drain locations, and covers the base part between source electrode, drain electrode, and described dummy grid is across mask lines.
Alternatively, described substrate is silicon-on-insulator substrate, the top silicon layer that described silicon-on-insulator substrate comprises bottom silicon layer, is positioned at the insulating barrier on described bottom silicon layer and is positioned on described insulating barrier;
Described source electrode, drain electrode are arranged in the top silicon layer under the mask lines of described dummy grid both sides;
Carry out patterned method to the base part bottom described pseudo-gate groove to comprise: with described interlayer dielectric layer and mask lines for mask, etch the top silicon layer part that bottom pseudo-gate groove, not masked line covers, to exposing insulating barrier, the residue top silicon layer bottom pseudo-gate groove under mask lines is as fin.
Alternatively, after the described fin of formation, use hydrogen plasma, or use hydrogen plasma and nitrogen plasma etching fin sidewall, remove the protuberance of described fin sidewall, described protuberance is formed in the top silicon layer process etching the not masked line covering bottom pseudo-gate groove.
Alternatively, plasmarized formation hydrogen plasma is carried out to hydrogen;
Carrying out plasmarized power bracket to hydrogen is 1W ~ 500W; In etching fin sidewall process, radio frequency range is 2MHz ~ 100MHz; The range of flow of hydrogen is 10sccm ~ 500sccm.
Alternatively, before the described source electrode of formation, drain electrode, the first side wall is formed in described dummy grid both sides.
Alternatively, after the described fin of formation, the base side wall under described first side wall forms the second side wall.
Alternatively, described fin formula field effect transistor is P type fin formula field effect transistor, before the described high-K gate dielectric layer of formation and grid, with described second side wall for mask, at described fin portion surface epitaxial growth Ge silicon layer.
Alternatively, the method forming high-K gate dielectric layer and grid in described pseudo-gate groove comprises:
Form high K dielectric material layer, described high K dielectric layer of material covers interlayer dielectric layer and pseudo-gate groove, described high K dielectric material layer forms gate material layers, and described gate material layers fills full pseudo-gate groove;
Remove the high K dielectric material layer and the gate material layers that exceed described interlayer dielectric layer upper surface, residue high K dielectric material layer is as high-K gate dielectric layer, and residue gate material layers is as grid.
Alternatively, described substrate comprises the firstth district and the secondth district, and the fin formula field effect transistor formed in described firstth district is P type fin formula field effect transistor, and the fin formula field effect transistor formed in described secondth district is N-type fin formula field effect transistor;
The described fin of P type fin formula field effect transistor and the fin of N-type fin formula field effect transistor are synchronously formed.
Alternatively, the material of the grid of described P type fin formula field effect transistor is different from the material of the grid of N-type fin formula field effect transistor.
The present invention also provides a kind of fin formula field effect transistor, and this fin formula field effect transistor comprises:
Substrate;
Be positioned at described suprabasil interlayer dielectric layer;
Be arranged in the pseudo-gate groove of described interlayer dielectric layer;
Be arranged in the source electrode of described pseudo-gate groove both sides substrate, drain electrode;
Be positioned at the fin bottom described pseudo-gate groove, described fin two ends connect source electrode, drain electrode respectively;
Be arranged in described pseudo-gate groove across the high-K gate dielectric layer of fin be positioned at grid on high-K gate dielectric layer.
Alternatively, the mask lines, described interlayer dielectric layer and the high-K gate dielectric layer coverage mask line that are positioned at source electrode, drain electrode and fin upper surface is also comprised.
Alternatively, in described pseudo-gate groove, grid both sides have the first side wall.
Alternatively, the base side wall under described first side wall has the second side wall.
Alternatively, described fin formula field effect transistor is P type fin formula field effect transistor, has germanium silicon layer in described fin portion surface.
The present invention also provides a kind of semiconductor device, and this semiconductor device comprises:
Substrate, described substrate comprise the firstth district and and the secondth district;
Be positioned at above-mentioned arbitrary described fin formula field effect transistor in the firstth district, the described fin formula field effect transistor in the firstth district is P type fin formula field effect transistor;
Be positioned at above-mentioned arbitrary described fin formula field effect transistor in the secondth district, the described fin formula field effect transistor in the secondth district is n type field effect transistor.
Alternatively, the material of the grid of described P type fin formula field effect transistor is different from the material of the grid of N-type fin formula field effect transistor.
Compared with prior art, technical scheme of the present invention has the following advantages:
After formation dummy grid, form interlayer dielectric layer; Afterwards, remove dummy grid and form pseudo-gate groove; The fin connecting source electrode and drain electrode is formed bottom pseudo-gate groove.With the first formation fin of the fin formula field effect transistor of prior art, then form dummy grid and compare, the technical program for first to form dummy grid, then forms fin.Like this, avoid and form fin height in dummy grid process to the impact of dummy grid height, and avoid the impact on gate height further, gate height can accurately be located, gate height conforms to substantially with predefine height, then the signal transmission in fin formula field effect transistor is reliable, stable.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the perspective view of fin formula field effect transistor in forming process of prior art;
Fig. 6 is the cross-sectional view of fin formula field effect transistor in forming process of the first embodiment;
Fig. 7 is the schematic top plan view of fin formula field effect transistor in forming process of the first embodiment;
Fig. 8 is the cross-sectional view of the tangent line AA place cutting plane along Fig. 7;
The schematic top plan view of fin formula field effect transistor in forming process of Fig. 9 first embodiment;
Figure 10 is the cross-sectional view of the tangent line BB place cutting plane along Fig. 9;
Figure 11 is the schematic top plan view of fin formula field effect transistor in forming process of the first embodiment;
Figure 12 is the cross-sectional view of the tangent line CC place cutting plane along Figure 11;
Figure 13 is the schematic top plan view of fin formula field effect transistor in forming process of the first embodiment;
Figure 14 is the cross-sectional view of the tangent line DD place cutting plane along Figure 13;
Figure 15 is the schematic top plan view of fin formula field effect transistor in forming process of the first embodiment;
Figure 16 is the cross-sectional view of the tangent line EE place cutting plane along Figure 15;
Figure 17 is the cross-sectional view of the tangent line FF place cutting plane along Figure 15;
Figure 18 is the schematic top plan view of fin formula field effect transistor in forming process of the first embodiment;
Figure 19 is the cross-sectional view of the tangent line GG place cutting plane along Figure 18;
Figure 20 is the cross-sectional view of the tangent line HH place cutting plane along Figure 18;
Figure 21 is the schematic top plan view of fin formula field effect transistor in forming process of the first embodiment;
Figure 22 is the cross-sectional view of the tangent line JJ place cutting plane along Figure 21;
Figure 23 is the cross-sectional view of the tangent line KK place cutting plane along Figure 21;
Figure 24 ~ Figure 28 is the schematic top plan view of fin formula field effect transistor in forming process of the second embodiment.
Embodiment
Analyze discovery after deliberation, with reference to Fig. 2, because fin 30 exceeds insulating barrier 20 upper surface, polysilicon layer 40 upper surface that deposition is formed is uneven, and the polysilicon layer on fin 30 will apparently higher than the polysilicon layer on insulating barrier 20.In conjunction with reference Fig. 3, CMP process is being carried out to polysilicon layer 40, because polysilicon layer 40 upper surface is uneven, undulate, when grinding " protruding surface ", also a small amount of grinding " sunk surface ", time smooth to polysilicon layer 40 upper surface, the thickness of the polysilicon layer determining to be polished is difficult to.
When determining the thickness of the polysilicon layer be polished, the thickness of remaining polysilicon layer also can not be determined, accordingly, the height of dummy grid be can not determine, is also difficult to accurately be located thus to the height of metal gates.If the thickness of the polysilicon layer be polished is comparatively large, the height of the corresponding metal gates formed can lower than predefine height; If the thickness of the polysilicon layer be polished is less, the height of the corresponding metal gates formed is higher than predefine height.Like this, height and the predefined height of the metal gates finally obtained are not inconsistent.Consider the high integration of integrated circuit, the slight variations of gate height, just may impact the reliability of the signal transmission in grid, cause the signal transmission in fin formula field effect transistor unreliable, cause the performance of fin formula field effect transistor not good.
For solving the problem, technical solution of the present invention proposes a kind of formation method of new fin formula field effect transistor.Use the method for the technical program, fin is formed after removal dummy grid, and the height avoiding fin affects the pin-point accuracy location of metal gates.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First embodiment
With reference to Fig. 6, provide substrate 100, described substrate 100 is silicon-on-insulator substrate, the top silicon layer 103 that described substrate 100 comprises bottom silicon layer 101, is positioned at the insulating barrier 102 on bottom silicon layer 101 and is positioned on insulating barrier 102.
In a particular embodiment, the material of described insulating barrier 102 is silica, plays insulation buffer action.
With reference to Fig. 7, Fig. 8, Fig. 7 is schematic top plan view, Fig. 8 is the cross-sectional view of the tangent line AA place cutting plane along Fig. 7, described substrate 100 forms mask lines 104, mask lines 104 is positioned on top silicon layer 103, mask lines 104 covers the base part of source electrode, drain locations, and covers the base part of the fin position between source electrode and drain electrode.
In a particular embodiment, the method forming mask lines 104 comprises:
Top silicon layer 103 forms layer of mask material, and mask material is silica, chemical vapour deposition (CVD) or thermal oxide growth method can be used to form layer of mask material, or mask material is silicon nitride, chemical vapour deposition technique can be used to form layer of mask material;
Carry out graphically to layer of mask material, etch mask material layer forms mask lines 104.
Continue with reference to Fig. 7, Fig. 8, substrate 100 is formed the dummy grid 110 across mask lines 104, and in dummy grid 110 both sides, sidewall forms the first side wall 111, and dummy grid 110, first side wall 111 is positioned on top silicon layer 103.
In a particular embodiment, the method described substrate 100 forming dummy grid 110 and the first side wall 111 comprises:
Described substrate 100 forms dummy grid material layer, dummy grid material is polysilicon or amorphous carbon, in the present embodiment, dummy grid material is amorphous carbon, amorphous carbon has good mobility, uses spin coating (spin-on) technique to form dummy grid material layer, in other embodiments, when dummy grid material is polysilicon, chemical vapour deposition (CVD) is used to form dummy grid material layer;
Because the thickness of mask lines 104 is very little, therefore the impact of thickness on dummy grid material layer upper surface flatness of mask lines 104 is very little, the upper surface of dummy grid material layer is smooth substantially, when using cmp dummy grid material layer to regulate dummy grid height, the thickness of the dummy grid material layer ground away is controlled;
Carry out graphically to described dummy grid material layer, dry etching dummy grid material layer, described substrate 100 forms dummy grid 110, the height of dummy grid 110 meets expection definition height;
After formation dummy grid 110, deposition spacer material layer, described spacer material layer covers top silicon layer 103, mask lines 104 and dummy grid 110;
Return etching spacer material layer, remove on top silicon layer 103, spacer material layer in dummy grid 110 upper surface and mask lines 104, the spacer material layer of residue dummy grid 110 both sides sidewall is as the first side wall 111.
With reference to Fig. 9, Figure 10, Fig. 9 is schematic top plan view, and Figure 10 is the cross-sectional view of the tangent line BB place cutting plane along Fig. 9, forms source electrode 105, drain electrode 106 in the top silicon layer 103 under the mask lines of dummy grid 110 both sides.
In a particular embodiment, formed in the top silicon layer 103 of dummy grid 110 both sides source electrode 105, drain electrode 106 method be:
Described substrate 100 forms patterned photoresist layer, and the window of patterned photoresist layer exposes the position of mask lines 104;
With patterned photoresist layer and the first side wall 111 for mask, ion implantation is carried out to mask lines 104, ion diffuses to top silicon layer through mask lines 104, form ion heavy doping in top silicon layer under mask lines 104, dummy grid 110 both sides have the heavily doped top silicon layer of ion respectively as source electrode 105, drain electrode 106.
In a particular embodiment, the doping type in source electrode 105, drain electrode 106 is relevant with the type of fin formula field effect transistor to be formed.In the present embodiment, fin formula field effect transistor to be formed is P type fin formula field effect transistor, and the doping type in source electrode 105, drain electrode 106 is the doping of P type.In other embodiments, if fin formula field effect transistor to be formed is N-type fin formula field effect transistor, then the doping type in source electrode, drain electrode is N-type doping.
With reference to Figure 11, Figure 12, Figure 11 is schematic top plan view, Figure 12 is the cross-sectional view of the tangent line CC place cutting plane along Figure 11, described substrate 100 forms interlayer dielectric layer 107, and described interlayer dielectric layer 107 upper surface and dummy grid 110 upper surface and the first side wall 111 upper surface remain basically stable.
In a particular embodiment, the material of interlayer dielectric layer 107 is silica.The method forming interlayer dielectric layer 107 comprises: chemical vapour deposition (CVD) silicon oxide layer, and silicon oxide layer covers top silicon layer 103, mask lines 104, dummy grid 110 and the first side wall 111; Remove the silicon oxide layer exceeding dummy grid 110 upper surface, specifically can use cmp or return etching, residual silicon oxide layer is as interlayer dielectric layer 107.
With reference to Figure 13, Figure 14, Figure 13 is schematic top plan view, Figure 14 is the cross-sectional view of the tangent line DD place cutting plane along Figure 13, remove dummy grid 110(with reference to Figure 11, Figure 12), in interlayer dielectric layer 107, form pseudo-gate groove 108, be top silicon layer 103 and mask lines 104 bottom pseudo-gate groove 108.Particularly, pseudo-gate groove 108 is between two relative the first side walls 111.
In a particular embodiment, removing the method for dummy grid is: with interlayer dielectric layer 107 and mask lines 104 for mask, etching removes dummy grid, to exposed tops silicon layer 103 and mask lines 104.The method that etching removes dummy grid is dry etching or wet etching.If use dry etching, after dry etching removes dummy grid, also can remove residue by wet etching further, this residue is removed in dummy grid process at dry etching and is produced.
Reference Figure 15 ~ Figure 17, Figure 15 are schematic top plan view, and Figure 16 is the cross-sectional view of the tangent line EE place cutting plane along Figure 15, and Figure 17 is the cross-sectional view of the tangent line FF place cutting plane along Figure 15, and wherein tangent line EE is mutually vertical with tangent line FF.
Carry out graphically to the base part bottom pseudo-gate groove 108, remove the top silicon layer part that not masked line 104 covers, the top silicon layer part under residue mask lines is as fin 109, and described fin 109 two ends connect source electrode 105, drain electrode 106 respectively.
In a particular embodiment, carry out patterned method to the base part bottom pseudo-gate groove 108 to comprise: with interlayer dielectric layer 107 and mask lines 104 for mask, etch the top silicon layer part that not masked line 104 covers, to exposing insulating barrier 102, the residue top silicon layer under pseudo-gate groove 108 is as fin 109.
In a particular embodiment, after formation fin 109, can choice for use hydrogen plasma, or use hydrogen plasma and nitrogen plasma etching fin 109 sidewall, remove the protuberance (not shown) of fin 109 sidewall, protuberance is formed in the top silicon layer process etching not masked line 104 covering bottom pseudo-gate groove 108, makes fin 109 sidewall smooth.
After deliberation, compared to use hydrogen plasma and nitrogen plasma etching fin 109 sidewall, only use hydrogen plasma etching fin 109 sidewall can obtain larger etch rate.Therefore, can select according to sidewall portion distribution scenario, when protuberance size is larger and densely distributed, only can use hydrogen plasma etching fin sidewall, can fully remove fin sidewall portion within a short period of time like this; When protuberance is small-sized or distribute sparse, hydrogen plasma and nitrogen plasma etching fin sidewall can be used, prevent from causing too much etching to fin sidewall.
In the present embodiment, hydrogen plasma etching fin sidewall is used.Carry out plasmarized formation hydrogen plasma to hydrogen, carrying out plasmarized power bracket to hydrogen is 1W ~ 500W; In the top silicon layer process that the not masked line of etching covers, radio frequency range is 2MHz ~ 100MHz; The range of flow of hydrogen is 10sccm ~ 500sccm.
In the present embodiment, fin formula field effect transistor to be formed is P type fin formula field effect transistor.Reference Figure 18 ~ Figure 20, Figure 18 are schematic top plan view, and Figure 19 is the cross-sectional view of the tangent line GG place cutting plane along Figure 18, and Figure 20 is the cross-sectional view of the tangent line HH place cutting plane along Figure 18, and wherein tangent line GG is mutually vertical with tangent line HH.
Top silicon layer 103 both sides sidewall under the first side wall 111 forms the second side wall 112; With the second side wall 112, mask lines 104 and interlayer dielectric layer 107 for mask, at fin 109 sidewall epitaxial growth Ge silicon layer 113, the insulating barrier 102 wherein exposed in pseudo-gate groove 108 also plays mask effect.
Germanium silicon has higher carrier mobility compared to silicon, and follow-up germanium silicon layer can be used as the channel region of fin formula field effect transistor, and the carrier mobility in channel region is higher, significantly promotes signal transmission speed in P type fin formula field effect transistor.In addition, before growth germanium silicon layer, the protuberance of fin 109 sidewall is removed, make fin 109 sidewall surfaces smooth, reduce fin 109 sidewall line edge roughness (LineEdge Roughness, LER), avoid larger LER on the impact of the nearly band gap width of germanium, guarantee that germanium silicon layer 113 has larger carrier mobility.
With reference to Figure 21 ~ Figure 23, Figure 21 is schematic top plan view, Figure 22 is the cross-sectional view of the tangent line JJ place cutting plane along Figure 21, Figure 23 is the cross-sectional view of the tangent line KK place cutting plane along Figure 21, at pseudo-gate groove 108(with reference to Figure 18, Figure 19) the middle grid 114 forming high-K gate dielectric layer (not shown) and be positioned on high-K gate dielectric layer.
In a particular embodiment, the method forming high-K gate dielectric layer and grid 114 in pseudo-gate groove comprises:
Form high K dielectric material layer, the material that high K dielectric material is well known to those skilled in the art, high K dielectric layer of material covers interlayer dielectric layer and groove;
High K dielectric material layer forms gate material layers, and in the present embodiment, grid material is metal, sputtering technology is used to form gate material layers, in other embodiments, grid material also can be other viable material, and gate material layers covers high K dielectric material layer, fills full pseudo-gate groove;
Remove the high K dielectric material layer and the gate material layers that exceed interlayer dielectric layer 107 upper surface, concrete use cmp or time etching high K dielectric material layer and gate material layers, residue high K dielectric material layer in pseudo-gate groove is as high-K gate dielectric layer, residue gate material layers is as grid 114, in the present embodiment, grid 114 is metal gates.
In the present embodiment, high-K gate dielectric layer is formed after the pseudo-gate groove of formation.In other embodiments, can also be: before formation dummy grid, deposition high K dielectric material layer, the substrate of high K dielectric layer of material covers and mask lines; Carry out graphically to high K dielectric material layer afterwards, form high-K gate dielectric layer in corresponding dummy grid position.
In conjunction with reference Fig. 5, the source electrode of existing fin formula field effect transistor, drain electrode are arranged in the fin of grid both sides, by source electrode, drain be connected with other device architectures respectively by conductive plunger time, because fin live width is less, may exceed fin portion surface bottom conductive plunger, this can increase the resistance between conductive plunger in conductive plunger on source electrode and source electrode, drain electrode and drain electrode.Use the fin formula field effect transistor that the present embodiment is formed, fin is only distributed in grid 114 times, and source electrode, drain electrode is in the top silicon layer of fin both sides, the surface size of top silicon layer much larger than fin portion surface size, like this, the conductive plunger be positioned in source electrode, drain electrode can be formed effectively contact with source electrode, drain surface, reduces the resistance between conductive plunger and source electrode, drain surface.
Second embodiment
In a second embodiment, form P type fin formula field effect transistor and N-type fin formula field effect transistor on the same base simultaneously.Described P type fin formula field effect transistor and N-type fin formula field effect transistor form an inverter or other semiconductor device.
With reference to the scheme of the first embodiment, the method for the formation fin formula field effect transistor of the second embodiment comprises:
With reference to Figure 24, substrate 300 comprises the first district I and the second district II, will form P type fin formula field effect transistor at the first district I, will form N-type fin formula field effect transistor at the second district II;
With reference to Figure 24, form the first mask lines 314 at the first district I and form the second mask lines 324 at the second district I, first mask lines 314 and the second mask lines 324 are synchronously formed, first mask lines 314 defines the first source electrode, first drain electrode and the position of the first fin of P type fin formula field effect transistor, and the second mask lines 324 defines the position of the second source electrode of N-type fin formula field effect transistor, the second drain electrode and the second fin;
With reference to Figure 24, substrate 300 is formed dummy grid 310, and in dummy grid 310 both sides, sidewall forms the first side wall 311 respectively, and dummy grid 310 and the first side wall 311 are across the first mask lines 314 and the second mask lines 324;
The first source electrode, the first drain electrode (not shown) is formed in substrate under the first mask lines 314 of dummy grid 310 both sides, the second source electrode, the second drain electrode (not shown) is formed in substrate under the second mask lines 324 of dummy grid 310 both sides, doping type in first source electrode, the first drain electrode is the doping of P type, doping type in second source electrode, the second drain electrode is N-type doping, and the forming step of the first source electrode, the first drain electrode and the second source electrode, the second forming step drained complete respectively;
With reference to Figure 25, Figure 25 is schematic top plan view, form interlayer dielectric layer 307, interlayer dielectric layer 30 interlayer dielectric layer 307 covers the base part of dummy grid 310 both sides, the first hard mask lines and the second hard mask lines, first hard mask lines and the second hard mask lines invisible, interlayer dielectric layer 307 upper surface and dummy grid 310 upper surface maintain an equal level;
With reference to Figure 26, remove dummy grid 310(with reference to Figure 25), form pseudo-gate groove, this pseudo-gate groove is divided into the first pseudo-gate groove of the first district I and the second pseudo-gate groove (not shown) in the secondth district, first pseudo-gate groove is by the first grid for the formation of P type fin formula field effect transistor, and the second groove is by the second grid for the formation of N-type fin formula field effect transistor;
With reference to Figure 27, Figure 27 is schematic top plan view, to remove in pseudo-gate groove not by top silicon layer that the first mask lines and the second mask lines cover, expose the insulating barrier 302 of substrate, residue top silicon layer part under first mask lines 314 is as the first fin, residue top silicon layer under second mask lines 324 is as the second fin, and the first fin and the second fin are synchronous formation;
With reference to Figure 28, the first grid 319 of P type fin formula field effect transistor and the second grid 329 of N-type fin formula field effect transistor is formed in pseudo-gate groove, in the present embodiment, first grid 319 and second grid 329 can be commaterials, and at this moment first grid and second grid can be formed in same step;
In other embodiments, first grid 319 also can not be identical with the material of second grid 329, first grid 319 and second grid 329 are formed respectively in different step, according to different materials, regulate the electrical parameter of first grid 319 and second grid 329, improve the performance of transistor, material as first grid 319 is molybdenum, there is higher work-functions, second grid 329 can be Mo layer and the laminated construction being positioned at the tantalum metal layer formation on Mo layer, and tantalum has comparatively low work function compared to molybdenum.
In the present embodiment, first grid 319 and second grid 329 are interconnective, and P type fin formula field effect transistor and N-type fin formula field effect transistor form the device architecture of an inverter or other cooperative works jointly.In other embodiments, may also be spaced apart from each other between first grid 319 and second grid 329.
Except with except the difference part of the first embodiment, in the present embodiment other unspecified in perhaps alternative with reference to the content of the first embodiment, can repeat no more in the present embodiment.
With reference to Figure 21 ~ Figure 23, the present invention also provides a kind of fin formula field effect transistor, and this fin formula field effect transistor comprises:
Substrate 100, substrate 100 is silicon-on-insulator substrate, the top silicon layer 103 that silicon-on-insulator substrate comprises bottom silicon layer 101, is positioned at the insulating barrier 102 on bottom silicon layer 101 and is positioned on insulating barrier 102;
Be positioned at the interlayer dielectric layer 107 in substrate 100;
Be arranged in the pseudo-gate groove (not shown) of interlayer dielectric layer 107;
Be arranged in the source electrode of pseudo-gate groove both sides top silicon layer, drain electrode (not shown);
Be positioned at the fin 109 bottom described pseudo-gate groove, described fin 109 two ends connect source electrode, drain electrode respectively;
Be arranged in pseudo-gate groove across the high-K gate dielectric layer (not shown) of fin 109 be positioned at grid 114 on high-K gate dielectric layer.
In a particular embodiment, described fin formula field effect transistor also comprises: the mask lines 104 being positioned at source electrode, drain electrode and fin 109 upper surface, interlayer dielectric layer 107 coverage mask line 104.
In a particular embodiment, in pseudo-gate groove, grid 114 both sides have the first side wall 111, and the top silicon layer sidewall under the first side wall 111 has the second side wall 112.
In a particular embodiment, described fin formula field effect transistor is P type fin formula field effect transistor, has germanium silicon layer 113 on fin 109 surface.
With reference to Figure 28, the present invention also provides a kind of semiconductor device, and this semiconductor device comprises:
Substrate, substrate is silicon-on-insulator substrate, and described substrate comprises the first district I and the second district II;
Be positioned at the above-mentioned fin formula field effect transistor of the first district I, the fin formula field effect transistor of the first district I is P type fin formula field effect transistor;
Be positioned at the above-mentioned fin formula field effect transistor of the second district II, the fin formula field effect transistor of the second district II is N-type fin formula field effect transistor.
In a particular embodiment, the material of the grid of P type fin formula field effect transistor can be identical with the material of the grid of N-type fin formula field effect transistor, also can not be identical.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Substrate is provided, is formed with dummy grid on the substrate;
Source electrode, drain electrode is formed in the substrate of described dummy grid both sides;
Form interlayer dielectric layer on the substrate, described interlayer dielectric layer upper surface and dummy grid upper surface maintain an equal level;
Remove described dummy grid, in described interlayer dielectric layer, form pseudo-gate groove;
Carry out graphically to the base part bottom described pseudo-gate groove, between described source electrode and drain electrode, form fin, described fin two ends connect source electrode, drain electrode respectively;
The high-K gate dielectric layer across described fin and the grid be positioned on high-K gate dielectric layer is formed in described pseudo-gate groove.
2. form method as claimed in claim 1, it is characterized in that, the formation method of described dummy grid comprises:
Form dummy grid material layer on the substrate;
Carry out graphically, forming dummy grid on the substrate to described dummy grid material layer.
3. form method as claimed in claim 1, it is characterized in that, the material of described dummy grid is polysilicon or amorphous carbon.
4. form method as claimed in claim 1, it is characterized in that, before the described dummy grid of formation, form mask lines on the substrate, described mask lines covers the base part of source electrode, drain locations, and covers the base part between source electrode, drain electrode, and described dummy grid is across mask lines.
5. form method as claimed in claim 4, it is characterized in that, described substrate is silicon-on-insulator substrate, the top silicon layer that described silicon-on-insulator substrate comprises bottom silicon layer, is positioned at the insulating barrier on described bottom silicon layer and is positioned on described insulating barrier;
Described source electrode, drain electrode are arranged in the top silicon layer under the mask lines of described dummy grid both sides;
Carry out patterned method to the base part bottom described pseudo-gate groove to comprise: with described interlayer dielectric layer and mask lines for mask, etch the top silicon layer part that bottom pseudo-gate groove, not masked line covers, to exposing insulating barrier, the residue top silicon layer bottom pseudo-gate groove under mask lines is as fin.
6. form method as claimed in claim 5, it is characterized in that, after the described fin of formation, use hydrogen plasma, or use hydrogen plasma and nitrogen plasma etching fin sidewall, remove the protuberance of described fin sidewall, described protuberance is formed in the top silicon layer process etching the not masked line covering bottom pseudo-gate groove.
7. form method as claimed in claim 6, it is characterized in that, plasmarized formation hydrogen plasma is carried out to hydrogen;
Carrying out plasmarized power bracket to hydrogen is 1W ~ 500W; In etching fin sidewall process, radio frequency range is 2MHz ~ 100MHz; The range of flow of hydrogen is 10sccm ~ 500sccm.
8. the formation method as described in claim 1 or 4, is characterized in that, before the described source electrode of formation, drain electrode, forms the first side wall in described dummy grid both sides.
9. form method as claimed in claim 8, it is characterized in that, after the described fin of formation, the base side wall under described first side wall forms the second side wall.
10. form method as claimed in claim 9, it is characterized in that, described fin formula field effect transistor is P type fin formula field effect transistor, before the described high-K gate dielectric layer of formation and grid, with described second side wall for mask, at described fin portion surface epitaxial growth Ge silicon layer.
11. form method as claimed in claim 1, it is characterized in that, the method forming high-K gate dielectric layer and grid in described pseudo-gate groove comprises:
Form high K dielectric material layer, described high K dielectric layer of material covers interlayer dielectric layer and pseudo-gate groove, described high K dielectric material layer forms gate material layers, and described gate material layers fills full pseudo-gate groove;
Remove the high K dielectric material layer and the gate material layers that exceed described interlayer dielectric layer upper surface, the residue high K dielectric material layer in pseudo-gate groove is as high-K gate dielectric layer, and residue gate material layers is as grid.
12. form method as claimed in claim 1, it is characterized in that, described substrate comprises the firstth district and the secondth district, the fin formula field effect transistor formed in described firstth district is P type fin formula field effect transistor, and the fin formula field effect transistor formed in described secondth district is N-type fin formula field effect transistor;
The described fin of P type fin formula field effect transistor and the fin of N-type fin formula field effect transistor are synchronously formed.
13. form method as claimed in claim 12, it is characterized in that, the material of the grid of described P type fin formula field effect transistor is different from the material of the grid of N-type fin formula field effect transistor.
14. 1 kinds of fin formula field effect transistors, is characterized in that, comprising:
Substrate;
Be positioned at described suprabasil interlayer dielectric layer;
Be arranged in the pseudo-gate groove of described interlayer dielectric layer;
Be arranged in the source electrode of described pseudo-gate groove both sides substrate, drain electrode;
Be positioned at the fin bottom described pseudo-gate groove, described fin two ends connect source electrode, drain electrode respectively;
Be arranged in described pseudo-gate groove across the high-K gate dielectric layer of fin be positioned at grid on high-K gate dielectric layer.
15. fin formula field effect transistors as claimed in claim 14, is characterized in that, also comprise the mask lines, described interlayer dielectric layer and the high-K gate dielectric layer coverage mask line that are positioned at source electrode, drain electrode and fin upper surface.
16. fin formula field effect transistors as described in claims 14 or 15, it is characterized in that, in described pseudo-gate groove, grid both sides have the first side wall.
17. fin formula field effect transistors as claimed in claim 16, it is characterized in that, the base side wall under described first side wall has the second side wall.
18. fin formula field effect transistors as claimed in claim 17, it is characterized in that, described fin formula field effect transistor is P type fin formula field effect transistor, has germanium silicon layer in described fin portion surface.
19. 1 kinds of semiconductor device, is characterized in that, comprising:
Substrate, described substrate comprise the firstth district and and the secondth district;
Be positioned at the fin formula field effect transistor described in any one of claim 14 ~ 18 in the firstth district, the described fin formula field effect transistor in the firstth district is P type fin formula field effect transistor;
Be positioned at the fin formula field effect transistor described in any one of claim 14 ~ 17 in the secondth district, the described fin formula field effect transistor in the secondth district is n type field effect transistor.
20. semiconductor device as claimed in claim 19, is characterized in that, the material of the grid of described P type fin formula field effect transistor is different from the material of the grid of N-type fin formula field effect transistor.
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| CN106158637A (en) * | 2015-03-31 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and forming method thereof |
| CN107437565A (en) * | 2016-05-31 | 2017-12-05 | 三星电子株式会社 | Semiconductor devices and the method being used for producing the semiconductor devices |
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| CN113224145A (en) * | 2020-02-06 | 2021-08-06 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
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