CN103594344A - Method for manufacturing multi-height Fin EFT (field effect transistor) devices - Google Patents
Method for manufacturing multi-height Fin EFT (field effect transistor) devices Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 102
- 239000011159 matrix material Substances 0.000 claims description 85
- 108091006146 Channels Proteins 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910052582 BN Inorganic materials 0.000 claims description 7
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
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- 238000000059 patterning Methods 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
The invention provides a method for manufacturing multi-height Fin EFT (field effect transistor) devices. The thickness of an epitaxially grown semiconductor layer through adjusting the thickness of a patterned mask layer used when a semiconductor substrate is etched to form a first fin base body and a second fin base body, thereby enabling subsequently formed first fins and second fins to be different in height, then manufacturing Fin FETs with different fin heights, and being simple in process.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacture method of many height FinFET devices.
Background technology
MOSFET(metal oxide semiconductor field effect is answered transistor) be the main member of most of semiconductor device, when channel length is less than 100nm, in traditional MOSFET, because the semi-conducting material of the Semiconductor substrate around active area makes between source electrode and drain region interactive, drain electrode is also shortened with the distance of source electrode thereupon, produce short-channel effect, so the control ability variation of grid to raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing, so just makes sub-threshold values electric leakage (Subthrehhold leakage) phenomenon more easily occur.
Fin formula field-effect transistor (Fin Field effect transistor, FinFET) be that a kind of novel metal oxide semiconductor field effect is answered transistor, its structure forms conventionally on silicon-on-insulator (SOI) substrate, comprise that narrow and isolated silicon strip (is the channel structure of vertical-type, also claim fin), fin both sides and top are with grid structure.FinFET structure makes device less, and performance is higher.
As shown in Figure 1, a kind of structure of FinFET device in prior art, comprise: substrate 10, the conductive grid structure 14 that stands on the fin on described substrate 10 and be centered around fin both sides and top, described fin comprises source electrode 11, drain electrode 12, fin channel district 13; Described conductive grid structure 14 is centered around gate dielectric layer and the grid layer (not shown) of 13 both sides, fin channel district and top conventionally.Wherein, source electrode 11, drain electrode 12Yu fin channel district 13, that strained silicon layer and the ion implantation technology being covered on SOI substrate dielectric layer by patterning obtains, the thickness in described fin channel district 13 as thin as a wafer, and three faces of its protrusion are controlled, be subject to the control of grid, can construct and entirely exhaust structure, thoroughly cut off the conductive path of raceway groove.
Conventionally, one group of simulation class circuit, for example sense amplifier, latch and SRAM are mono-, very responsive to transistor channel width, and especially very responsive to the ratio of the channel width of the different FET that contain in device, therefore, in the performance of the different circuit of chip internal, can adjust by the channel width of one or more FET of changing at device inside.This allows designer's needed local performance that changes Different Logic circuit on chip.
For FinFET structure, channel width is proportional to fin height, and this is because channel width is vertical in FinFET device.Because the both sides of fin are all exposed to but electrically isolate from grid, therefore, channel width is actually the twice in the region being produced by fin height (being multiplied by fin length).Therefore,, by increasing or reduce fin height (for given fin length), channel width (be exposed to but electrically isolate from the channel surface area of grid) also correspondingly increases or reduces.
Yet, the manufacturing process of conventional FinFET device can only make all fins on the chip providing, have identical height, therefore, the manufacture method that needs a kind of many height FinFET devices, to manufacture, there is the FinFET of different fin height, thereby meet the FinFET device manufacture requirement of different performance.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of many height FinFET devices, to manufacture the FinFET with different fin height.
For addressing the above problem, the present invention proposes a kind of manufacture method of many height FinFET devices, comprises the following steps:
Semiconductor substrate is provided, in described Semiconductor substrate, forms the patterned mask layer for the manufacture of fin of predefine thickness;
The described patterned mask layer of take is mask, and Semiconductor substrate described in etching, forms the first fin matrix and the second fin matrix, and described the first fin matrix and the second fin matrix are contour;
At described semiconductor substrate surface deposition interlayer dielectric layer, and described in chemical-mechanical planarization interlayer dielectric layer to described patterned mask layer top;
Remove the patterned mask layer covering on described the second fin matrix, form an opening;
Epitaxial growth semiconductor layer in described opening, and carry out top flattening;
Remove remaining patterned mask layer, and interlayer dielectric layer described in time etching, to expose the first fin matrix and the second fin matrix of certain altitude.
Further, described Semiconductor substrate is body silicon substrate or silicon-on-insulator substrate.
Further, the material of described the first fin matrix and the second fin matrix is silicon, germanium silicon or carbon silicon.
Further, the material of described patterned mask layer is one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride.
Further, described epitaxially grown semiconductor layer is germanium silicon layer, carbon silicon layer or polysilicon layer.
Further, before removing the patterned mask layer covering on described the second fin matrix, second mask layer at the patterned mask layer top above formation above described interlayer dielectric layer and patterned mask layer exposes described the second fin matrix.
Further, after removing the patterned mask layer covering on described the second fin matrix, also remove described the second mask layer.
Further, the material of described the second mask layer is one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride.
Further, described manufacture method also comprises:
To expose certain altitude the first fin matrix and, the second fin matrix and on semiconductor layer carry out N-type or P type channel ion and inject, form the first fin-shaped channel region and the second fin-shaped channel region;
Formation is centered around the both sides of the first fin-shaped channel region and the first grid structure of top and is centered around the second grid structure of the second both sides, fin-shaped channel region and top;
The second fin matrix to the first fin matrix of described first grid structure both sides and second grid structure both sides carries out source/drain region Implantation, forms the first fin and the second fin.
Further, described first grid structure and second grid structure include inner gate oxide and outside polysilicon layer.
Further, described first grid structure and second grid structure connect in aggregates between the first fin matrix and the second fin matrix.
Further, described first grid structure and second grid structure are disconnected between the first fin matrix and the second fin matrix.
Compared with prior art, the manufacture method of many height FinFET devices provided by the invention, the thickness of the patterned mask layer of using in the time of can forming the first fin matrix and the second fin matrix by adjusting etching semiconductor substrate regulates the thickness of epitaxially grown semiconductor layer, make the first fin of follow-up formation different from the height of the second fin, and then manufacture the FinFET with different fin height, technique is simple.
Accompanying drawing explanation
Fig. 1 is a kind of FinFET device architecture schematic diagram of the prior art;
Fig. 2 is the FinFET device making method flow chart of the specific embodiment of the invention;
Fig. 3 A ~ 3F is the device architecture schematic diagram in the FinFET device making method of the specific embodiment of the invention.
Embodiment
The manufacture method of FinFET device provided by the invention, the thickness of the patterned mask layer of using when key is to form the first fin matrix and the second fin matrix by adjusting etching semiconductor substrate regulates the difference in height of the fin of follow-up formation, to produce the FinFET with different fin height.
The manufacture method of FinFET device the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.
As shown in Figure 2, the present embodiment provides a kind of manufacture method of FinFET device, comprises the following steps:
S21, provides Semiconductor substrate, forms the patterned mask layer that is used to form fin of predefine thickness in described Semiconductor substrate;
S22, the described patterned mask layer of take is mask, and Semiconductor substrate described in etching, forms the first fin matrix and the second fin matrix, and described the first fin matrix and the second fin matrix are contour;
S23, at described semiconductor substrate surface deposition interlayer dielectric layer, and described in chemical-mechanical planarization interlayer dielectric layer to described patterned mask layer top;
S24, removes the patterned mask layer covering on described the second fin matrix, forms an opening;
S25, epitaxial growth semiconductor layer in described opening, and carry out top flattening;
S26, removes remaining patterned mask layer, and interlayer dielectric layer described in time etching, to expose the first fin matrix and the second fin matrix of certain altitude;
S27, to expose certain altitude the first fin matrix, the second fin matrix and on semiconductor layer carry out N-type or P type channel ion injects, form the first fin-shaped channel region and the second fin-shaped channel region;
S28, forms the second grid structure that is centered around the both sides of the first fin-shaped channel region and the first grid structure of top and is centered around the second both sides, fin-shaped channel region and top;
S29, carries out source/drain region Implantation to the second fin matrix of the first fin matrix of described first grid structure both sides and second grid structure both sides, forms the first fin and the second fin.
Please refer to Fig. 3 A, in step S21, the Semiconductor substrate 300 providing can be body silicon substrate, can be also silicon-on-insulator substrate.Preferably, Semiconductor substrate 300 is carbon doped silicon or Germanium-doped silicon for the part of follow-up formation fin.In step S21, can to Semiconductor substrate 300, carry out N-type or P type well region Implantation first along the direction on vertical semiconductor substrate 300 surfaces, form N-type well region or P type well region; Then, deposition mask layer on Semiconductor substrate 300 surfaces, without extra mask plate, directly by fin mask plate, mask layer described in patterning, is formed for manufacturing the patterned mask layer 301 of fin.Wherein, the material of described hard mask layer 301 comprises one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride, and the difference in height of the fin that thickness can form is as required set.
Please refer to Fig. 3 B, in step S22, the described patterned mask layer 301 of take is mask, described in etching, Semiconductor substrate 300, remove the certain thickness Semiconductor substrate 300 not covered by described patterned mask layer 301, form the first fin matrix 302a and the second fin matrix 302b, described the first fin matrix 302a is identical with the height of the second fin matrix 302b, and relatively described Semiconductor substrate 300 bottoms are upright, and its top is covered with the patterned mask layer 301 of same thickness.Preferably, the material of described the first fin matrix 302a and the second fin matrix 302b is silicon, germanium silicon or carbon silicon.
Please refer to Fig. 3 C, in step S23, at described Semiconductor substrate 300 surface deposition interlayer dielectric layers 303, and described interlayer dielectric layer 303 is carried out to top chemical-mechanical planarization, to expose mask layer 301 tops of described patterning.Wherein, the material of described interlayer dielectric layer 303 comprises one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride.
Please continue to refer to Fig. 3 C, in step S24, can first above described interlayer dielectric layer 303 and patterned mask layer 301, deposit the second mask layer (not shown), wherein, the material of described the second mask layer is one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride; Then patterning the second mask layer, to expose the patterned mask layer top on described the second fin matrix 302b; Then, remove the patterned mask layer on described the second fin matrix 302b, form an opening 301a; Then the second mask layer forming before removing.
Please refer to Fig. 3 D, in step S25, epitaxial growth semiconductor layer 302c in described opening 301a, and epitaxially grown semiconductor layer 302c is carried out to top flattening.Wherein, epitaxially grown semiconductor layer 302c is germanium silicon layer, carbon silicon layer or polysilicon layer.
Please refer to Fig. 3 E, in step S26, remove remaining patterned mask layer, and interlayer dielectric layer 303 described in time etching, to expose the first fin matrix 302a and the second fin matrix 302b of certain altitude, in this step, the second fin matrix 302b and the semiconductor layer 302c on it are for follow-up formation the second fin, the first fin matrix 302a is for follow-up formation the first fin, and the difference in height of the second fin and the first fin is the thickness of semiconductor layer 302c (or claiming height).
Please refer to Fig. 3 F, in step S27, to expose certain altitude the first fin matrix 302a, the second fin matrix 302a and on semiconductor layer 302c carry out N-type or P type channel ion and inject, form the first fin-shaped channel region and the second fin-shaped channel region.
Please continue to refer to Fig. 3 F, in step S28, formation is centered around the both sides of the first fin-shaped channel region and the first grid structure 306a of top and is centered around the second grid structure 306b of the second both sides, fin-shaped channel region and top, in the present embodiment, described first grid structure 306a and second grid structure 306b include inner gate oxide 304 and outside polysilicon layer 305, and described first grid structure 306a and second grid structure 306b connect in aggregates between the first fin matrix 302a and the second fin matrix 302b, can be regarded as one-body molded, by the whole device surface after step S27, deposit successively one deck gate oxide 304 and polysilicon layer 305, then etch polysilicon layer 305 and gate oxide 304 form.The FinFET device with this grid structure is exposed to but electrically isolates from the channel region of grid by using a plurality of fins, can increasing or reduce.Therefore, for the fin with equal length and height, when comparing with single fin, two fins can make effective channel width double, and three fins can make effective channel width increase by three times, etc.And, by providing, thering is the design of using differing heights fin ability in single transistor, the present invention allows the better quantification of channel surface area change, allows thus to adjust better the resolution between the different circuit of chip internal.In other embodiments, described first grid structure 306a and second grid structure 306b can be also disconnected, separate between the first fin matrix 302a and the second fin matrix 302b.
Please continue to refer to Fig. 3 F, in step S29, to the first fin matrix 302a(of described first grid structure 306a both sides, be unlapped the first fin matrix 302a region of first grid structure 306a) and the second fin matrix 302b(of second grid structure 306b both sides be unlapped the second fin matrix 302b region of second grid structure 306b) carry out source/drain region Implantation, formation source/drain electrode, and then complete the manufacture of highly different the first fin and the second fin.The main body of the second fin is the combination of the second fin matrix 302b and epitaxially grown semiconductor layer 302c, and the main body of the first fin is the first fin matrix 302a, and the difference in height of the second fin and the first fin is the thickness of semiconductor layer 302c (or claiming height).
Preferably, before or after carrying out source/drain region Implantation, on the first fin matrix 302a of described first grid structure 306a both sides, (being unlapped the first fin matrix 302a region top of first grid structure 306a) and the second fin matrix 302b of second grid structure 306b both sides upper (being unlapped the second top, fin matrix 302b region of second grid structure 306b) form side wall, so that the first fin and the second fin and first grid structure 306a and second grid structure 306b are insulated.
In sum, the manufacture method of many height FinFET devices provided by the invention, technique is simple, the thickness of the patterned mask layer of using while forming the first fin matrix and the second fin matrix by adjusting etching semiconductor substrate regulates the thickness of epitaxially grown semiconductor layer, make the first fin of follow-up formation different from the height of the second fin, and then manufacture the FinFET with different fin height.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (12)
1. a manufacture method for the FinFET of height more than device, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms the patterned mask layer for the manufacture of fin of predefine thickness;
The described patterned mask layer of take is mask, and Semiconductor substrate described in etching, forms the first fin matrix and the second fin matrix, and described the first fin matrix and the second fin matrix are contour;
At described semiconductor substrate surface deposition interlayer dielectric layer, and described in chemical-mechanical planarization interlayer dielectric layer to described patterned mask layer top;
Remove the patterned mask layer covering on described the second fin matrix, form an opening;
Epitaxial growth semiconductor layer in described opening, and carry out top flattening;
Remove remaining patterned mask layer, and interlayer dielectric layer described in time etching, to expose the first fin matrix and the second fin matrix of certain altitude.
2. the manufacture method of many height FinFET devices as claimed in claim 1, is characterized in that, described Semiconductor substrate is body silicon substrate or silicon-on-insulator substrate.
3. the manufacture method of many height FinFET devices as claimed in claim 1, is characterized in that, the material of described the first fin matrix and the second fin matrix is silicon, germanium silicon or carbon silicon.
4. the manufacture method of many height FinFET devices as claimed in claim 1, is characterized in that, the material of described patterned mask layer is one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride.
5. the manufacture method of many height FinFET devices as claimed in claim 1, is characterized in that, described epitaxially grown semiconductor layer is germanium silicon layer, carbon silicon layer or polysilicon layer.
6. the manufacture method of many height FinFET devices as claimed in claim 1, it is characterized in that, before removing the patterned mask layer covering on described the second fin matrix, second mask layer at the patterned mask layer top above formation above described interlayer dielectric layer and patterned mask layer exposes described the second fin matrix.
7. the manufacture method of many height FinFET devices as claimed in claim 6, is characterized in that, after removing the patterned mask layer covering on described the second fin matrix, also removes described the second mask layer.
8. the manufacture method of the many height FinFET device as described in claim 6 or 7, is characterized in that, the material of described the second mask layer is one or more in silica, silicon nitride silicon oxynitride, amorphous carbon and boron nitride.
9. the manufacture method of many height FinFET devices as claimed in claim 1, is characterized in that, also comprises:
To expose certain altitude the first fin matrix, the second fin matrix and on semiconductor layer carry out N-type or P type channel ion injects, form the first fin-shaped channel region and the second fin-shaped channel region;
Formation is centered around the both sides of the first fin-shaped channel region and the first grid structure of top and is centered around the second grid structure of the second both sides, fin-shaped channel region and top;
The second fin matrix to the first fin matrix of described first grid structure both sides and second grid structure both sides carries out source/drain region Implantation, forms the first fin and the second fin.
10. the manufacture method of many height FinFET devices as claimed in claim 9, is characterized in that, described first grid structure and second grid structure include inner gate oxide and outside polysilicon layer.
The manufacture method of 11. many height FinFET devices as claimed in claim 9, is characterized in that, described first grid structure and second grid structure connect in aggregates between the first fin matrix and the second fin matrix.
The manufacture method of 12. many height FinFET devices as claimed in claim 9, is characterized in that, described first grid structure and second grid structure are disconnected between the first fin matrix and the second fin matrix.
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| CN103871897A (en) * | 2014-02-21 | 2014-06-18 | 上海华力微电子有限公司 | Chemical mechanical grinding method applied to FinFET (fin field-effect transistor) structure |
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| CN105047564A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Fin type field effect transistor base body preparation method |
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| CN105118778A (en) * | 2015-07-22 | 2015-12-02 | 上海华力微电子有限公司 | Multi-height fin field-effect transistor substrate preparation method |
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| CN105448728A (en) * | 2014-08-29 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of forming fin field-effect transistor |
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Cited By (21)
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| CN103871897A (en) * | 2014-02-21 | 2014-06-18 | 上海华力微电子有限公司 | Chemical mechanical grinding method applied to FinFET (fin field-effect transistor) structure |
| CN105097701A (en) * | 2014-04-25 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Static memory cell forming method |
| CN105097701B (en) * | 2014-04-25 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The forming method of static storage cell |
| CN103943484B (en) * | 2014-04-28 | 2016-08-17 | 上海华力微电子有限公司 | Self aligned grid separation method |
| CN103943484A (en) * | 2014-04-28 | 2014-07-23 | 上海华力微电子有限公司 | Self-aligned grid separation method |
| CN105448728B (en) * | 2014-08-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
| CN105448728A (en) * | 2014-08-29 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of forming fin field-effect transistor |
| CN105845572A (en) * | 2015-01-14 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method therefor, and electronic device |
| CN105047564B (en) * | 2015-06-30 | 2017-11-24 | 上海华力微电子有限公司 | Fin field effect pipe matrix preparation method |
| CN105047564A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Fin type field effect transistor base body preparation method |
| CN105118778A (en) * | 2015-07-22 | 2015-12-02 | 上海华力微电子有限公司 | Multi-height fin field-effect transistor substrate preparation method |
| CN105118778B (en) * | 2015-07-22 | 2018-05-11 | 上海华力集成电路制造有限公司 | More height fin field effect pipe matrix preparation methods |
| CN105225963A (en) * | 2015-10-14 | 2016-01-06 | 上海华力微电子有限公司 | A kind of preparation method of FinFET semiconductor device |
| CN105225963B (en) * | 2015-10-14 | 2018-09-04 | 上海华力微电子有限公司 | A kind of preparation method of FinFET semiconductor devices |
| CN108780811A (en) * | 2016-02-24 | 2018-11-09 | 姜全忠 | Layer structural vertical field-effect transistor and its manufacturing method |
| CN108780811B (en) * | 2016-02-24 | 2021-03-30 | 姜全忠 | Layer structure vertical field effect transistor and manufacturing method thereof |
| CN107393917A (en) * | 2016-04-22 | 2017-11-24 | 三星电子株式会社 | IC-components |
| CN107393917B (en) * | 2016-04-22 | 2020-08-18 | 三星电子株式会社 | Integrated circuit device |
| CN106449413B (en) * | 2016-10-26 | 2019-03-26 | 上海华力微电子有限公司 | Fin-shaped semiconductor devices and preparation method thereof |
| CN106449413A (en) * | 2016-10-26 | 2017-02-22 | 上海华力微电子有限公司 | Fin-shaped semiconductor device and preparation method thereof |
| CN113948570A (en) * | 2021-10-14 | 2022-01-18 | 上海集成电路研发中心有限公司 | Semiconductor structure and preparation process thereof |
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