CN113948570A - Semiconductor structure and preparation process thereof - Google Patents
Semiconductor structure and preparation process thereof Download PDFInfo
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- CN113948570A CN113948570A CN202111199257.0A CN202111199257A CN113948570A CN 113948570 A CN113948570 A CN 113948570A CN 202111199257 A CN202111199257 A CN 202111199257A CN 113948570 A CN113948570 A CN 113948570A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000011049 filling Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 122
- 238000000151 deposition Methods 0.000 claims description 23
- 239000002346 layers by function Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 238000002910 structure generation Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000002425 crystallisation Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 4
- 230000008025 crystallization Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 38
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a semiconductor structure, which comprises a bottom structure consisting of a substrate, a plurality of bottom pattern structures and a filling layer, wherein the bottom pattern structures comprise: the bottom pattern structures are arranged on the substrate and comprise a plurality of bottom high pattern parts and a plurality of bottom low pattern parts; the filling layer covers the top surface of the substrate and the top surfaces of the bottom low pattern parts and fills the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to adjust the pattern density; the height of any one of the bottom low pattern parts is lower than that of any one of the bottom high pattern parts, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts, so that the growth of crystal grains in the filling layer can be inhibited, and the flatness of the surface is improved. The invention also provides a preparation process of the semiconductor structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation process thereof.
Background
A metal material having a strong reflective property, such as aluminum, is widely used to form a reflective layer film of various products. However, the metal surface may generate larger grains due to the self-crystallization effect, so that the surface is uneven, which affects the current layer and the subsequent process.
When photoetching is carried out on the metal film, due to strong reflection, the characteristics of key size precision, pattern edge roughness and the like are difficult to control, and the current layer and the subsequent process are influenced.
Therefore, there is a need to provide a novel semiconductor structure and a process for fabricating the same to solve some of the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a preparation process thereof, so as to improve the flatness of a surface.
In order to achieve the above object, the semiconductor structure of the present invention includes a bottom structure composed of a substrate, a plurality of bottom pattern structures, and a filling layer:
the bottom pattern structures are arranged on the substrate and comprise a plurality of bottom high pattern parts and a plurality of bottom low pattern parts;
the filling layer covers the top surfaces of the bottom low pattern parts and fills the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to adjust the pattern density;
the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts.
The semiconductor structure has the beneficial effects that: the filling layer covers the top surface of the substrate and the top surfaces of the bottom low pattern parts and fills spaces between the bottom low pattern parts and any two pattern parts in the bottom high pattern parts so as to adjust pattern density, wherein any one of the bottom low pattern parts is lower than any one of the bottom high pattern parts, and at least one of the bottom low pattern parts is arranged between every two adjacent bottom high pattern parts, so that growth of crystal grains in the filling layer can be inhibited, and the flatness of the surface is improved.
Preferably, the filling layer comprises a plurality of functional layers and a plurality of function adjusting layers.
Further preferably, the filling layer includes a laminated structure formed by alternately stacking the functional layer and the function adjusting layer.
Further preferably, the functional layer is a reflective layer, and the function adjusting layer is a reflection adjusting layer to improve the flatness of the reflective layer by suppressing a crystallization effect of the reflective layer.
Preferably, the width of the bottom low pattern part and the width of the bottom high pattern part are the same or different.
Preferably, the plurality of bottom low pattern parts have the same height, and the plurality of bottom high pattern parts have the same height.
Preferably, the composition material of the bottom low pattern part and the composition material of the bottom high pattern part are the same or different.
Preferably, the semiconductor structure further comprises at least one layer of stacked structure stacked on the bottom structure, wherein the at least one layer of stacked structure covers the top surface of the filling layer;
each layer of stacked structure comprises a plurality of high graph parts, a plurality of low graph parts and a filling part, wherein the filling part covers the top surfaces of the low graph parts and fills the space between any two graph parts in the high graph parts and the low graph parts;
the high graph parts in the adjacent two layers of stacking structures are arranged in a one-to-one correspondence mode, and the low graph parts in the adjacent two layers of stacking structures are arranged in a one-to-one correspondence mode.
The invention also provides a preparation process of the semiconductor structure, which comprises the following steps:
forming a plurality of bottom high pattern parts and a plurality of bottom low pattern parts on a substrate, wherein the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts;
and depositing a filling layer to enable the filling layer to cover the top surfaces of the bottom low pattern parts and fill the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to form a bottom structure.
The preparation process of the semiconductor structure has the beneficial effects that: forming a plurality of bottom high pattern parts and a plurality of bottom low pattern parts on a substrate, wherein the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between two adjacent bottom high pattern parts, so that the growth of crystal grains in the filling layer can be inhibited, and the flatness of the surface is improved.
Preferably, the forming of the bottom high pattern portions and the bottom low pattern portions on the substrate includes:
depositing a first dielectric layer on the substrate, and then etching the first dielectric layer to form a plurality of initial patterns, wherein a part of the initial patterns is used as the bottom low pattern part;
depositing a second dielectric layer on another part of the initial patterns, and removing part of the second dielectric layer to form the bottom high pattern part.
Preferably, the depositing the filling layer includes: and alternately depositing a functional layer and a function adjusting layer to form the filling layer.
Preferably, the process for manufacturing a semiconductor structure further includes a stacked structure generation step, the stacked structure generation step including:
forming high pattern parts corresponding to the bottom high pattern parts one by one on the tops of the bottom high pattern parts, and forming low pattern parts corresponding to the bottom low pattern parts one by one on the tops of the bottom low pattern parts;
and depositing a filling part to enable the filling part to cover the top surfaces of the bottom low pattern parts and fill the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to form a layer of stacked structure.
Drawings
FIG. 1 is a flow chart of a process for fabricating a semiconductor structure in accordance with some embodiments of the present invention;
FIG. 2 is a schematic diagram of the structure of a photoresist structure formed in some embodiments of the present invention;
FIG. 3 is a schematic diagram of the structure of FIG. 2 after photolithography;
FIG. 4 is a schematic diagram of the structure of FIG. 3 after removal of the photoresist structure;
FIG. 5 is a schematic view of the structure shown in FIG. 4 after photoresist is coated and exposed;
FIG. 6 is a schematic diagram illustrating the deposition of a second dielectric layer in FIG. 5;
FIG. 7 is a schematic diagram illustrating the structure of FIG. 6 after polishing a second dielectric layer;
FIG. 8 is a schematic diagram of the structure of FIG. 7 after removal of the photoresist;
FIG. 9 is a schematic structural view of the structure of FIG. 7 after alternate deposition of a functional layer and a functional adjustment layer;
FIG. 10 is a schematic view of a semiconductor structure having only a bottom structure formed after polishing a fill layer according to the structure shown in FIG. 9;
fig. 11 is a schematic view of a semiconductor structure after a layer of stack structure is formed on a bottom structure in some embodiments of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a semiconductor structure, which includes a bottom structure composed of a substrate, a plurality of bottom pattern structures, and a filling layer: the bottom pattern structures are arranged on the substrate and comprise a plurality of bottom high pattern parts and a plurality of bottom low pattern parts; the filling layer covers the top surface of the substrate and the top surfaces of the bottom low pattern parts and fills the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to adjust the pattern density; the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts.
In some embodiments, the semiconductor structure further comprises at least one layer of stacked structure stacked on the bottom structure, the at least one layer of stacked structure covering the top surface of the filling layer; each layer of stacked structure comprises a plurality of high graph parts, a plurality of low graph parts and a filling part, wherein the filling part covers the top surfaces of the low graph parts and fills the space between any two graph parts in the high graph parts and the low graph parts; the high graph parts in the stacking structure are arranged in a one-to-one correspondence manner, the low graph parts in the stacking structure are arranged in a one-to-one correspondence manner, the high graph parts in the stacking structure and the bottom high graph parts are arranged in a one-to-one correspondence manner, and the low graph parts in the stacking structure and the bottom low graph parts are arranged in a one-to-one correspondence manner.
In some embodiments, the filler layer and the filler portion each include a plurality of functional layers and a plurality of function adjusting layers. Preferably, the filling layer includes a laminated structure formed by alternately stacking the functional layers and the function adjusting layers. Specifically, the functional layer is a reflective layer, and the function adjusting layer is a reflection adjusting layer to improve the flatness of the reflective layer by suppressing the crystallization effect of the reflective layer.
In some embodiments, the material of the reflection layer is any one of aluminum, gold and platinum, and the material of the reflection adjusting layer is any one of aluminum oxide, zirconium oxide and platinum.
In some embodiments, the width of the bottom low pattern part and the width of the bottom high pattern part are the same or different; the height of the low pattern part is the same as or different from the height of the high pattern part. In some preferred embodiments, the width of the bottom low pattern part is the same as the width of the bottom high pattern part, and the width of the bottom low pattern part is the same as the width of the low pattern part; the bottom low graph parts have the same height, and the bottom high graph parts have the same height; the low pattern parts have the same height, and the high pattern parts have the same height.
In some specific embodiments, the height of the bottom low pattern part is 500A to 2 μm, the width of the bottom low pattern part is 0.1 μm to 1 μm, the height of the bottom high pattern part is 1000A to 2 μm, the width of the bottom high pattern part is 0.2 μm to 1.2 μm, the thickness of the reflective layer is 500A to 2 μm, and the thickness of the emission adjusting layer is 200A to 1 μm.
In some embodiments, the constituent material of the bottom low pattern portion and the constituent material of the bottom high pattern portion are the same or different; the constituent material of the low pattern part and the constituent material of the high pattern part may be the same or different. In some preferred embodiments, the composition material of the bottom low pattern part is the same as the composition material of the bottom high pattern part; the composition material of the low pattern part is the same as that of the high pattern part.
FIG. 1 is a flow chart of a process for fabricating a semiconductor structure in accordance with some embodiments of the present invention; FIG. 2 is a schematic diagram of the structure of a photoresist structure formed in some embodiments of the present invention; FIG. 3 is a schematic diagram of the structure of FIG. 2 after photolithography; FIG. 4 is a schematic diagram of the structure of FIG. 3 after removal of the photoresist structure; FIG. 5 is a schematic view of the structure shown in FIG. 4 after photoresist is coated and exposed; FIG. 6 is a schematic diagram illustrating the deposition of a second dielectric layer in FIG. 5; FIG. 7 is a schematic diagram illustrating the structure of FIG. 6 after polishing a second dielectric layer;
FIG. 8 is a schematic diagram of the structure of FIG. 7 after removal of the photoresist; FIG. 9 is a schematic structural view of the structure of FIG. 7 after alternate deposition of a functional layer and a functional adjustment layer; FIG. 10 is a schematic view of a semiconductor structure having only a bottom structure formed after polishing a fill layer according to the structure shown in FIG. 9.
Referring to fig. 1 to 10, a process for fabricating a semiconductor structure includes the steps of:
s1: forming a plurality of bottom high pattern parts and a plurality of bottom low pattern parts on a substrate, wherein the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts.
In some embodiments, the forming a number of bottom high patterns and a number of bottom low patterns on the substrate includes: depositing a first dielectric layer on the substrate, and then etching the first dielectric layer to form a plurality of initial patterns, wherein a part of the initial patterns is used as the bottom low pattern part; depositing a second dielectric layer on another portion of the initial pattern, and then removing a portion of the second dielectric layer to form the bottom high pattern portion.
Specifically, a first dielectric layer 11 is deposited on the substrate 10, and then photoresist is coated on the first dielectric layer 11, and the photoresist is exposed to form a first photoresist structure 111, a second photoresist structure 112, a third photoresist structure 113, a fourth photoresist structure 114, a fifth photoresist structure 115, a sixth photoresist structure 116, and a seventh photoresist structure 117, as shown in fig. 2;
performing photolithography on the first dielectric layer 11 to remove the first dielectric layer 11 not covered by the first photoresist structure 111, the second photoresist structure 112, the third photoresist structure 113, the fourth photoresist structure 114, the fifth photoresist structure 115, the sixth photoresist structure 116, and the seventh photoresist structure 117, so as to form a first initial pattern 1111, a second initial pattern 1121, a third initial pattern 1131, a fourth initial pattern 1141, a fifth initial pattern 1151, a sixth initial pattern 1161, and a seventh initial pattern 1171 covered by photoresist, which is the structure shown in fig. 3;
removing the first photoresist structure 111, the second photoresist structure 112, the third photoresist structure 113, the fourth photoresist structure 114, the fifth photoresist structure 115, the sixth photoresist structure 116, and the seventh photoresist structure 117 to expose the first initial pattern 1111, the second initial pattern 1121, the third initial pattern 1131, the fourth initial pattern 1141, the fifth initial pattern 1151, the sixth initial pattern 1161, and the seventh initial pattern 1171, wherein the second initial pattern 1121, the third initial pattern 1131, the fifth initial pattern 1151, and the sixth initial pattern 1161 are bottom low pattern portions, such as the structure shown in fig. 4;
coating a photoresist 118 on the substrate 10, the first initial pattern 1111, the second initial pattern 1121, the third initial pattern 1131, the fourth initial pattern 1141, the fifth initial pattern 1151, the sixth initial pattern 1161 and the seventh initial pattern 1171, and then exposing the photoresist 118 to expose the first initial pattern 1111, the fourth initial pattern 1141 and the seventh initial pattern 1171, as in the structure of fig. 5;
depositing a second dielectric layer 12 on the photoresist 118 coated at step S14, the first initial pattern 1111, the fourth initial pattern 1141 and the seventh initial pattern 1141, as in the structure shown in fig. 6;
performing chemical mechanical polishing on the second dielectric layer 12 until the photoresist 118 coated in step S14 is reached, that is, exposing the photoresist 118 coated in step S14, as shown in the structure of fig. 7;
and removing the photoresist, wherein the first initial pattern 1111 and the second dielectric layer 12 constitute a first bottom high pattern portion, the fourth initial pattern 1141 and the second dielectric layer 12 constitute a second bottom high pattern portion, and the seventh initial pattern 1171 and the second dielectric layer 12 constitute a third bottom high pattern portion, as shown in fig. 8.
S2: and depositing a filling layer to enable the filling layer to cover the top surface of the substrate and the top surfaces of the bottom low pattern parts and fill the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to form a bottom structure.
In some embodiments, the depositing a fill layer comprises: and alternately depositing a functional layer and a function adjusting layer to form the filling layer.
Specifically, an aluminum layer and an aluminum oxide layer are alternately deposited on the substrate 10 and the second dielectric pattern to form a filling layer 13, wherein the aluminum layer is the functional layer, and the aluminum oxide layer is the function adjusting layer, and the structure is shown in fig. 9;
the filling layer 13 is chemically and mechanically polished until reaching the bottom high pattern portion, i.e. the bottom high pattern portion is exposed, so as to form a bottom structure, such as the structure shown in fig. 10.
In some preferred embodiments, the process for manufacturing a semiconductor structure further comprises a stacked structure generation step, the stacked structure generation step comprising: forming high pattern parts corresponding to the bottom high pattern parts one by one on the tops of the bottom high pattern parts, and forming low pattern parts corresponding to the bottom low pattern parts one by one on the tops of the bottom low pattern parts; and depositing a filling part to enable the filling part to cover the top surface of the substrate and the top surfaces of the bottom low pattern parts and fill the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to form a layer of stacked structure.
Fig. 11 is a schematic view of a semiconductor structure after a layer of stack structure is formed on a bottom structure in some embodiments of the present invention. Referring to fig. 11, the low pattern part 14 is formed using the same fabrication process as that used to form the bottom low pattern part, the high pattern part 15 is formed using the same fabrication process as that used to form the bottom high pattern part, and the filling part 16 is deposited by the same process as that used to form the filling layer to form a one-layer stacked structure, as shown in fig. 11. The number of layers of the stacked structure is not particularly limited, and may be one layer of the stacked structure, two layers of the stacked structure, three layers of the stacked structure, or even more layers of the stacked structure.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A semiconductor structure, comprising a bottom structure composed of a substrate, a plurality of bottom pattern structures and a filling layer:
the bottom pattern structures are arranged on the substrate and comprise a plurality of bottom high pattern parts and a plurality of bottom low pattern parts;
the filling layer covers the top surfaces of the bottom low pattern parts and fills the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts;
the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts.
2. The semiconductor structure of claim 1, wherein the fill layer comprises a plurality of functional layers and a plurality of functional adjustment layers.
3. The semiconductor structure of claim 2, wherein the filling layer comprises a stacked structure formed by alternately stacking the functional layer and the function adjusting layer.
4. The semiconductor structure according to claim 3, wherein the functional layer is a reflective layer, and the function adjusting layer is a reflection adjusting layer for improving flatness of the reflective layer by suppressing a crystallization effect of the reflective layer.
5. The semiconductor structure of claim 1, wherein the bottom low pattern portions have the same height, and the bottom high pattern portions have the same height.
6. The semiconductor structure of claim 1, further comprising at least one layer of stacked structure stacked on the bottom structure, the at least one layer of stacked structure covering a top surface of the fill layer;
each layer of stacked structure comprises a plurality of high graph parts, a plurality of low graph parts and a filling part, wherein the filling part covers the top surfaces of the low graph parts and fills the space between any two graph parts in the high graph parts and the low graph parts;
the high graph parts in the adjacent two layers of stacking structures are arranged in a one-to-one correspondence mode, and the low graph parts in the adjacent two layers of stacking structures are arranged in a one-to-one correspondence mode.
7. A process for fabricating a semiconductor structure, comprising:
forming a plurality of bottom high pattern parts and a plurality of bottom low pattern parts on a substrate, wherein the height of any one bottom low pattern part is lower than that of any one bottom high pattern part, and at least one bottom low pattern part is arranged between every two adjacent bottom high pattern parts;
and depositing a filling layer to enable the filling layer to cover the top surfaces of the bottom low pattern parts and fill the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to form a bottom structure.
8. The process of claim 7, wherein the forming the bottom high features and the bottom low features on the substrate comprises:
depositing a first dielectric layer on the substrate, and then etching the first dielectric layer to form a plurality of initial patterns, wherein a part of the initial patterns is used as the bottom low pattern part;
and depositing a second dielectric layer on another part of the initial patterns, and then removing part of the second dielectric layer to form the bottom high pattern part.
9. The process of claim 7, wherein the depositing the fill layer comprises: and alternately depositing a functional layer and a function adjusting layer to form the filling layer.
10. The process for manufacturing a semiconductor structure according to claim 7, further comprising a stacked structure generation step, the stacked structure generation step comprising:
forming high pattern parts corresponding to the bottom high pattern parts one by one on the tops of the bottom high pattern parts, and forming low pattern parts corresponding to the bottom low pattern parts one by one on the tops of the bottom low pattern parts;
and depositing a filling part to enable the filling part to cover the top surfaces of the bottom low pattern parts and fill the space between any two pattern parts in the bottom low pattern parts and the bottom high pattern parts so as to form a layer of stacked structure.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06188243A (en) * | 1992-12-18 | 1994-07-08 | Toshiba Corp | Semiconductor device and its manufacture |
| TW536738B (en) * | 2002-04-25 | 2003-06-11 | Taiwan Semiconductor Mfg | Multi-layer photoresist lithography and method for forming dual damascene openings by the same |
| KR20050023204A (en) * | 2002-07-19 | 2005-03-09 | 소니 가부시끼 가이샤 | Production Method For Semiconductor Device |
| KR20100002553A (en) * | 2008-06-30 | 2010-01-07 | 삼성전자주식회사 | Reflection mask, method of manufacturing the same and method of correcting a design of the same |
| CN103594344A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing multi-height Fin EFT (field effect transistor) devices |
| CN104124197A (en) * | 2013-04-24 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN105047564A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Fin type field effect transistor base body preparation method |
| JP2016152356A (en) * | 2015-02-18 | 2016-08-22 | 大日本印刷株式会社 | Reflective mask, manufacturing method of reflective mask, and correction method for reflective mask |
| US20210305061A1 (en) * | 2020-03-31 | 2021-09-30 | Rashid Mavliev | Methods and systems of forming metal interconnect layers using engineered templates |
-
2021
- 2021-10-14 CN CN202111199257.0A patent/CN113948570B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06188243A (en) * | 1992-12-18 | 1994-07-08 | Toshiba Corp | Semiconductor device and its manufacture |
| TW536738B (en) * | 2002-04-25 | 2003-06-11 | Taiwan Semiconductor Mfg | Multi-layer photoresist lithography and method for forming dual damascene openings by the same |
| KR20050023204A (en) * | 2002-07-19 | 2005-03-09 | 소니 가부시끼 가이샤 | Production Method For Semiconductor Device |
| KR20100002553A (en) * | 2008-06-30 | 2010-01-07 | 삼성전자주식회사 | Reflection mask, method of manufacturing the same and method of correcting a design of the same |
| CN103594344A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing multi-height Fin EFT (field effect transistor) devices |
| CN104124197A (en) * | 2013-04-24 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| JP2016152356A (en) * | 2015-02-18 | 2016-08-22 | 大日本印刷株式会社 | Reflective mask, manufacturing method of reflective mask, and correction method for reflective mask |
| CN105047564A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Fin type field effect transistor base body preparation method |
| US20210305061A1 (en) * | 2020-03-31 | 2021-09-30 | Rashid Mavliev | Methods and systems of forming metal interconnect layers using engineered templates |
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