CN105225963A - A kind of preparation method of FinFET semiconductor device - Google Patents
A kind of preparation method of FinFET semiconductor device Download PDFInfo
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- CN105225963A CN105225963A CN201510663113.4A CN201510663113A CN105225963A CN 105225963 A CN105225963 A CN 105225963A CN 201510663113 A CN201510663113 A CN 201510663113A CN 105225963 A CN105225963 A CN 105225963A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000005530 etching Methods 0.000 claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 23
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 98
- 239000011241 protective layer Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention relates to a kind of preparation method of semiconductor structure, particularly relate to a kind of preparation method of FinFET semiconductor device, the method is after epitaxial growth forms doped epitaxial layer, utilize the etch differential opposite sex of epitaxial loayer and Semiconductor substrate and oxide skin(coating), etching forms the fin of differing heights successively, the grid of specifying separately is formed double grid by the method adopting machinery to polish again, and then the FinFET semiconductor device that formation 3T and 4T combines.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of preparation method of FinFET semiconductor device.
Background technology
Along with the development of semiconductor technology, traditional flatness device can not meet the demand of people to high performance device.FinFET (FinField-EffectTransistor, fin formula field effect transistor) is a kind of solid type device, is included in fin and the stacking gate crossing with fin that substrate is vertically formed.This design significantly can improve control circui and reduce leakage current (leakage), and the lock that also significantly can shorten transistor is long
At present, there are two kinds of approach by two of FinFET grids separately, a kind of is remove with the grid of cmp by Fin top, but in traditional FinFET structure, the method is difficult to 4T-FinFET (four-terminalFinFET) and 3T-FinFET (three-terminalFinFET) to be integrated together; Another kind method is increase by one light shield, is fallen by the grid etch on the Fin top of specifying, but the method is a huge challenge for aligning (alignment) technique in photoetching (photo).
Chinese patent (publication number is: CN103515231A) discloses a kind of FinFET manufacture method, under the prerequisite not increasing device size, by dielectric layer etching groove on a semiconductor substrate, described groove filled by the stressed semiconductor material adopting lattice to be different from described Semiconductor substrate again, removal medium layer and autoregistration define the fin stood on substrate, the lattice mismatch of fin and the Semiconductor substrate below it, make to produce stress in the channel region of fin, improve channel carrier mobility, and then improve the drive current of FinFET; Further, carbon and/or N~+ implantation are carried out to described fin, to reduce the ion implantation defect when source/drain region and channel region doping of carrying out fin, improve the interface quality in fin channel district simultaneously, improve FinFET performance.
Chinese patent (publication number is: CN104752221A) discloses a kind of formation method of fin formula field effect transistor, comprising: on substrate, form first, second adjacent fin; Form the grid across first, second fin; Form the first protective layer, the first etching stop layer, the second protective layer, second etching stop layer of cover gate and substrate from the bottom to top successively; Second etching stop layer forms patterned mask layer, covers the second etching stop layer of the second fin; Remove the second etching stop layer on the first fin, in same technique, remove the second protective layer on patterned mask layer and the first fin afterwards; The first etching stop layer on first etching removal first fin, the first protective layer afterwards on the second etching removal first fin, exposes the first fin; Heated substrate, carries out ion implantation to the first fin of grid both sides, forms source electrode and drain electrode; Remove the first etching stop layer and first protective layer of covering second fin.The method of this invention reduces making transistor difficulty, improves transistor performance.
The problem preparing the FinFET combined by 3T and 4T is difficult in all unresolved prior art of above-mentioned two patents.
Summary of the invention
For above-mentioned Problems existing, the invention discloses a kind of preparation method of FinFET semiconductor device, comprise the steps:
Semiconductor substrate is provided, surface has the first fin and the second fin, described first fin comprises epitaxial loayer, oxide layer and mask layer successively according to order from bottom to up, described second fin comprises oxide layer and mask layer successively according to order from bottom to up, and the thickness sum of the oxide layer of described epitaxial loayer and described first fin equals the thickness of the oxide layer of described second fin;
With the described Semiconductor substrate that the mask layer of described first fin and the second fin is mask etching predetermined thickness, to form the substrate layer be positioned at below described first fin and described second fin;
Remove described mask layer, the oxide layer of described first fin and the oxide layer of described second fin;
Insulating barrier is formed surperficial with the partial sidewall of the upper surface described Semiconductor substrate exposed and described substrate layer on described Semiconductor substrate;
Formed after dielectric layer and gate material layers covered with the surface that the sidewall upper surface of described insulating barrier, described substrate layer exposed and described epitaxial loayer expose on described Semiconductor substrate successively, machinery is carried out to described gate material layers and described dielectric layer and polishes upper surface stopping to described epitaxial loayer to form described FinFET semiconductor device.
The preparation method of above-mentioned FinFET semiconductor device, wherein, the method forming described first fin and described second fin in described semiconductor substrate surface comprises the steps:
An epitaxial loayer is grown on described Semiconductor substrate;
The described epitaxial loayer of etching appointed area is to be exposed the upper surface of part semiconductor substrate;
Deposited oxide layer is all covered with the surface exposed by described epitaxial loayer and the exposed upper surface of described Semiconductor substrate;
Form the mask layer of patterning on described oxide layer after, with the mask layer of described patterning for oxide layer described in mask etching stops to described epitaxial loayer upper surface;
With the mask layer of described patterning for after epitaxial loayer described in mask etching to described first fin of upper surface stopping formation of described Semiconductor substrate, continue the upper surface stopping of the described oxide layer of etching to described Semiconductor substrate to form described second fin.
The preparation method of above-mentioned FinFET semiconductor device, wherein, described oxide is silicon dioxide.
The preparation method of above-mentioned FinFET semiconductor device, wherein, the thickness of described epitaxial loayer is greater than 5nm
The preparation method of above-mentioned FinFET semiconductor device, wherein, the material of described Semiconductor substrate is monocrystalline silicon.
The preparation method of above-mentioned FinFET semiconductor device, wherein, the material of described mask layer is silicon nitride.
The preparation method of above-mentioned FinFET semiconductor device, wherein, described epitaxial loayer is Ge-doped extension or carbon doping extension.
The preparation method of above-mentioned FinFET semiconductor device, wherein, described dielectric layer is high dielectric constant material layer
The preparation method of above-mentioned FinFET semiconductor device, wherein, the material of described high dielectric constant material layer is HfO2.
The preparation method of above-mentioned FinFET semiconductor device, wherein, described gate material layers is metal or polysilicon.
Foregoing invention tool has the following advantages or beneficial effect:
The invention discloses a kind of preparation method of FinFET semiconductor device, the method is after epitaxial growth forms doped epitaxial layer, utilize the etch differential opposite sex of epitaxial loayer and Semiconductor substrate and oxide skin(coating), etching forms the fin of differing heights successively, the grid of specifying separately is formed double grid (doublegaet) by the method adopting machinery to polish again, and then the FinFET that formation 3T and 4T combines.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 ~ 15 are flowage structure schematic diagrames of the preparation method of FinFET semiconductor device in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
The present embodiment relates to a kind of preparation method of FinFET semiconductor device, and concrete, the method comprises the steps:
Step S1, semi-conductive substrate 1 is provided, in the present invention's preferred embodiment, the material of Semiconductor substrate 1 is monocrystalline silicon, certainly this Semiconductor substrate 1 also can other semi-conducting materials, due to the emphasis that this Semiconductor substrate 1 non-invention are improved, at this, just it will not go into details, structure as shown in Figure 1.
Step S2, on Semiconductor substrate 1, doped epitaxial grows an epitaxial loayer 2, and in the present invention's preferred embodiment, this epitaxial loayer 2 is Ge-doped extension or carbon doping extension; Preferably, the thickness of this epitaxial loayer 2 is greater than 5nm (such as 6nm, 10nm, 15nm, 20nm etc.); Structure as shown in Figure 2.
Step S3, the epitaxial loayer 2 of etching appointed area is to be exposed the upper surface of part semiconductor substrate 1, and this appointed area can according to concrete technology requirements set; Concrete, wet-etching technology or dry etch process can be adopted to etch this epitaxial loayer 2, structure as shown in Figure 3.
Step S4, deposited oxide layer 3 is all covered with the surface exposed by epitaxial loayer 2 and the exposed upper surface of Semiconductor substrate 1; In the present invention's preferred embodiment, this step is specially: first, adopts the method deposition oxide of chemical vapour deposition (CVD) all to be covered with the surface exposed by epitaxial loayer 2 and the exposed upper surface of Semiconductor substrate 1; Secondly, machinery is carried out to the top of this oxide and polishes, to form the oxide layer 3 that the surface that exposed by epitaxial loayer 2 and the exposed upper surface of Semiconductor substrate 1 are all covered; Preferably, the material of this oxide layer 3 is silicon dioxide; Structure as shown in Figure 4.
Step S5, forms the mask layer 4 of patterning on oxide layer 3, the concrete technology forming the mask layer 4 of patterning on oxide layer 3 is: first in oxide layer 3 surface deposition one deck mask layer 4, formed afterwards the photoresistance with gate patterns with respectively by the portion of upper surface of the mask layer 4 be positioned on epitaxial loayer 2 and be positioned at above-mentioned appointed area Semiconductor substrate 1 on the portion of upper surface of mask layer 4 covered, the upper surface that the photoresistance having gate patterns with this is mask etching mask layer 4 to oxide layer 3 stops with the mask layer 4 forming patterning, namely the mask layer 4 of this patterning covers the portion of upper surface of the oxide layer 3 on the portion of upper surface being positioned at oxide layer 3 on epitaxial loayer 2 and the Semiconductor substrate 1 being positioned at above-mentioned appointed area, in one embodiment of the invention, the material of this mask layer 4 is silicon nitride, structure as shown in Figure 5.
Step S6 is that mask etching oxide layer 3 to epitaxial loayer 2 upper surface stops with the mask layer 4 of patterning; In an embodiment of the present invention, dry etch process or wet-etching technology is taked to etch this oxide layer 3; Structure as shown in Figure 6.
Step S7, formation first fin is stopped with the upper surface that the mask layer 4 of patterning is mask etching epitaxial loayer 2 to Semiconductor substrate 1, concrete, to cover upper surface stopping formation first fin that the mask layer 4 of the portion of upper surface of the oxide layer 3 be positioned on epitaxial loayer 2 is mask etching epitaxial loayer 2 to Semiconductor substrate 1; This this first fin comprises epitaxial loayer 2, oxide layer 3 and mask layer 4 successively according to order from bottom to up; Structure as shown in Figure 7.
Step S8, continue to stop with the upper surface that the mask layer 4 of patterning is mask etching oxide layer 3 to Semiconductor substrate 1 to form the second fin, concrete, with cover be positioned at above-mentioned appointed area Semiconductor substrate 1 on the mask layer 4 of portion of upper surface of oxide layer 3 be that the upper surface of mask etching oxide layer 3 to Semiconductor substrate 1 stops forming the second fin, this second fin comprises oxide layer 3 and mask layer 4 successively according to order from bottom to up; And easily known by above-mentioned steps, this second fin and the first fin contour; The thickness of the oxide layer 3 in this second fin equals the thickness sum of oxide layer 3 and epitaxial loayer 2 in the first fin, structure as shown in Figure 8.
Step S9, with the Semiconductor substrate 1 that the mask layer 4 of the first fin and the second fin is mask etching predetermined thickness, to form the substrate layer 11 be positioned at below the first fin and the second fin, remaining Semiconductor substrate 1 (being namely positioned at the Semiconductor substrate below substrate layer 11) according to concrete technology requirements set, can be referred to as Semiconductor substrate 12 below by this predetermined thickness; Structure as shown in Figure 9.
Step S10, removes the oxide layer 3 of mask layer 4, first fin and the oxide layer 3 of the second fin, in an embodiment of the present invention, adopts dry etch process or wet-etching technology to remove the oxide layer 3 of mask layer 4, first fin and the oxide layer 3 of the second fin; Structure as shown in Figure 10.
Step S11, deposition of insulative material is covered with the semiconductor structure formed by step S10; In an embodiment of the present invention, this insulating material is oxide; Structure as shown in figure 11.
Step S12, etching insulating material covers the insulating barrier 5 on the upper surface of Semiconductor substrate 12 exposure and the partial sidewall surface of substrate layer 11 to be formed; Structure as shown in figure 12.
Step S13, on Semiconductor substrate 12, form the surface that dielectric layer 6 exposes with the surface upper surface of insulating barrier 5, substrate layer 11 exposed and epitaxial loayer 2 all covered, in a preferred embodiment of the invention, the material of this dielectric layer 6 is high dielectric constant material; On this basis, further, this high dielectric constant material is HfO
2; Structure as shown in fig. 13 that.
Step S14, deposition of gate material layer 7 is to be covered the upper surface of dielectric layer 6 and sidewall thereof; In the present invention's preferred embodiment, gate material layers 7 is metal gates, and this metal gates is made up of TIN/TaN/AL etc.; This gate material layers 7 not must adopt metal gates, and also can adopt the technique such as oxidation technology or original position moisture-generation process (ISSG) outside raceway groove, form oxide layer, deposit spathic silicon is as this gate material layers 7.Structure as shown in figure 14.
Step S15, carries out to gate material layers 7 and dielectric layer 6 upper surface that machinery polishes to epitaxial loayer 2 and stops combining FinFET semiconductor device to form 3T and 4T; Structure as shown in figure 15.
The invention discloses a kind of preparation method of FinFET semiconductor device, the method is after epitaxial growth forms doped epitaxial layer, utilize the etch differential opposite sex of epitaxial loayer and Semiconductor substrate and oxide skin(coating), etching forms the fin of differing heights successively, the grid of specifying separately is formed double grid by the method adopting machinery to polish again, and then the FinFET semiconductor device that formation 3T and 4T combines.
It should be appreciated by those skilled in the art that those skilled in the art are realizing change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a preparation method for FinFET semiconductor device, is characterized in that, comprises the steps:
Semiconductor substrate is provided, surface has the first fin and the second fin, described first fin comprises epitaxial loayer, oxide layer and mask layer successively according to order from bottom to up, described second fin comprises oxide layer and mask layer successively according to order from bottom to up, and the thickness sum of the oxide layer of described epitaxial loayer and described first fin equals the thickness of the oxide layer of described second fin;
Respectively with the described Semiconductor substrate that the mask layer of described first fin and the second fin is mask etching predetermined thickness, to form the substrate layer be positioned at below described first fin and described second fin;
Remove described mask layer, the oxide layer of described first fin and the oxide layer of described second fin;
Insulating barrier is formed surperficial with the partial sidewall of the upper surface described Semiconductor substrate exposed and described substrate layer on described Semiconductor substrate;
On described Semiconductor substrate, form dielectric layer covered with the surface of the sidewall that the upper surface of described insulating barrier, described substrate layer are exposed and the exposure of described epitaxial loayer;
Deposition of gate material layer covers upper surface and the sidewall thereof of described dielectric layer, and after gate material layers described in polishing, form described FinFET semiconductor device.
2. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, the step forming described first fin and described second fin in described semiconductor substrate surface comprises:
In the growing epitaxial layers of described Semiconductor substrate;
The described epitaxial loayer of etching appointed area is to be exposed the upper surface of part semiconductor substrate;
Deposited oxide layer is all covered with the surface exposed by described epitaxial loayer and the exposed upper surface of described Semiconductor substrate;
Form the mask layer of patterning on described oxide layer after, with the mask layer of described patterning for oxide layer described in mask etching stops to described epitaxial loayer upper surface;
With the mask layer of described patterning for after epitaxial loayer described in mask etching to described first fin of upper surface stopping formation of described Semiconductor substrate, continue the upper surface stopping of the described oxide layer of etching to described Semiconductor substrate to form described second fin.
3. the preparation method of FinFET semiconductor device as claimed in claim 2, it is characterized in that, described oxide is silicon dioxide.
4. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described epitaxial loayer is greater than 5nm.
5. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, the material of described Semiconductor substrate is monocrystalline silicon.
6. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, the material of described mask layer is silicon nitride.
7. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, described epitaxial loayer is Ge-doped extension or carbon doping extension.
8. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, described dielectric layer is high dielectric constant material layer.
9. the preparation method of FinFET semiconductor device as claimed in claim 8, it is characterized in that, the material of described high dielectric constant material layer is HfO2.
10. the preparation method of FinFET semiconductor device as claimed in claim 1, it is characterized in that, described gate material layers is metal or polysilicon.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449413A (en) * | 2016-10-26 | 2017-02-22 | 上海华力微电子有限公司 | Fin-shaped semiconductor device and preparation method thereof |
| CN114530447A (en) * | 2022-04-24 | 2022-05-24 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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|---|---|---|---|---|
| US20080224258A1 (en) * | 2006-11-06 | 2008-09-18 | International Business Machines Corporation | Semiconductor structue with multiple fins having different channel region heights and method of forming the semiconductor structure |
| EP1993136A1 (en) * | 2007-05-14 | 2008-11-19 | Interuniversitair Microelektronica Centrum (IMEC) | Multi-gate MOSFET device and method of manufacturing same |
| CN103594344A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing multi-height Fin EFT (field effect transistor) devices |
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2015
- 2015-10-14 CN CN201510663113.4A patent/CN105225963B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080224258A1 (en) * | 2006-11-06 | 2008-09-18 | International Business Machines Corporation | Semiconductor structue with multiple fins having different channel region heights and method of forming the semiconductor structure |
| EP1993136A1 (en) * | 2007-05-14 | 2008-11-19 | Interuniversitair Microelektronica Centrum (IMEC) | Multi-gate MOSFET device and method of manufacturing same |
| CN103594344A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing multi-height Fin EFT (field effect transistor) devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106449413A (en) * | 2016-10-26 | 2017-02-22 | 上海华力微电子有限公司 | Fin-shaped semiconductor device and preparation method thereof |
| CN106449413B (en) * | 2016-10-26 | 2019-03-26 | 上海华力微电子有限公司 | Fin-shaped semiconductor devices and preparation method thereof |
| CN114530447A (en) * | 2022-04-24 | 2022-05-24 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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