CN105225963B - A kind of preparation method of FinFET semiconductor devices - Google Patents
A kind of preparation method of FinFET semiconductor devices Download PDFInfo
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- CN105225963B CN105225963B CN201510663113.4A CN201510663113A CN105225963B CN 105225963 B CN105225963 B CN 105225963B CN 201510663113 A CN201510663113 A CN 201510663113A CN 105225963 B CN105225963 B CN 105225963B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000002360 preparation method Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 21
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 131
- 239000011241 protective layer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention relates to a kind of preparation methods of semiconductor structure, more particularly to a kind of preparation method of FinFET semiconductor devices, this method is after being epitaxially-formed doped epitaxial layer, it is anisotropic using epitaxial layer and semiconductor substrate and the etch differential of oxide skin(coating), etching forms the fin of different height successively, specified grid is formed separately by double grid using the method that machinery polishes again, and then forms the FinFET semiconductor devices that 3T and 4T is combined.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of preparation methods of FinFET semiconductor devices.
Background technology
With the continuous development of semiconductor technology, traditional flatness device cannot meet people to high performance device
Demand.FinFET (Fin Field-Effect Transistor, fin formula field effect transistor) is a kind of solid type device,
Including the fin being vertically formed on substrate and the stacking gate intersected with fin.This design can greatly improve circuit control and subtract
Few leakage current (leakage), the lock that can also substantially shorten transistor are long
Currently, two grids of FinFET are separated there are two types of approach, one is with chemical mechanical grinding by the tops Fin
Grid removes, but in traditional FinFET structure, the method be difficult by 4T-FinFET (four-terminal FinFET) and
3T-FinFET (three-terminal FinFET) is integrated together；Another method is to increase by one of light shield, will be specified
The grid etch on the tops Fin falls, but the method is one huge for alignment (alignment) technique in photoetching (photo)
Challenge.
Chinese patent (Publication No.：CN103515231A a kind of FinFET manufacturing methods) are disclosed, device is not being increased
Under the premise of size, served as a contrast different from the semiconductor by dielectric layer etching groove on a semiconductor substrate, then using lattice
The stressed semiconductor material at bottom fills the groove, and removal medium layer, that is, autoregistration forms the fin stood on substrate, fin
The lattice mismatch of piece and semiconductor substrate below so that generate stress in the channel region of fin, improve channel carrier
Mobility, and then improve the driving current of FinFET；Further, carbon and/or N~+ implantation are carried out to the fin,
Ion implanting defect when reducing the source/drain region carried out to fin and channel region doping, while improving fin channel area
Interface quality improves FinFET performance.
Chinese patent (Publication No.：CN104752221A a kind of forming method of fin formula field effect transistor) is disclosed,
Including：The first, second adjacent fin is formed on substrate；It is developed across the grid of the first, second fin；From the bottom to top successively
Form the first protective layer, the first etching stop layer, the second protective layer, the second etching stop layer of covering grid and substrate；Second
Patterned mask layer is formed on etching stop layer, covers the second etching stop layer of the second fin；Remove on the first fin
Two etching stop layers remove the second protective layer on patterned mask layer and the first fin later in same technique；First etching
The first etching stop layer on the first fin is removed, the first protective layer on second etching the first fin of removal, exposes the later
One fin；Substrate is heated, ion implanting is carried out to the first fin of grid both sides, forms source electrode and drain electrode；Removal covering second
The first etching stop layer and the first protective layer of fin.The method of the invention, which reduces, makes transistor difficulty, improves transistor
Energy.
It is difficult to prepare the combined FinFET devices of 3T and 4T in the prior art that above-mentioned two patent is unresolved
The problem of part.
Invention content
In view of the above problems, the invention discloses a kind of preparation methods of FinFET semiconductor devices, including such as
Lower step：
Semiconductor substrate is provided, surface has the first fin and the second fin, and first fin is according to from bottom to up
Sequence includes epitaxial layer, oxide layer and mask layer successively, and second fin includes oxidation successively according to sequence from bottom to up
Layer and mask layer, and the sum of thickness of oxide layer of the epitaxial layer and first fin is equal to the oxidation of second fin
The thickness of layer；
Using the mask layer of first fin and the second fin as the semiconductor substrate of mask etching predetermined thickness, with
Form the substrate layer below first fin and second fin；
Remove the oxide layer of the oxide layer and second fin of the mask layer, first fin；
Insulating layer is formed on the semiconductor substrate with the upper surface for exposing the semiconductor substrate and the lining
The partial sidewall surface of bottom covers；
Sequentially formed on the semiconductor substrate dielectric layer and gate material layers with by the upper surface of the insulating layer,
After the side wall of substrate layer exposure and the surface of epitaxial layer exposure give covering, to gate material layers and described
Dielectric layer carries out machinery and polishes the upper surface stopping to the epitaxial layer to form the FinFET semiconductor devices.
The preparation method of above-mentioned FinFET semiconductor devices, wherein form described in the semiconductor substrate surface
The method of one fin and second fin includes the following steps：
An epitaxial layer is grown on the semiconductor substrate；
Etching specifies the epitaxial layer in region to be exposed the upper surface of part semiconductor substrate；
Deposited oxide layer is given with the exposed upper surface in the surface for exposing the epitaxial layer and the semiconductor substrate
With covering；
After forming patterned mask layer on the oxide layer, using the patterned mask layer as mask etching institute
Oxide layer to the epitaxial layer upper surface is stated to stop；
Stop by the upper surface of epitaxial layer described in mask etching to the semiconductor substrate of the patterned mask layer
After forming first fin, continues to etch the oxide layer and stop to the upper surface of the semiconductor substrate to form described the
Two fins.
The preparation method of above-mentioned FinFET semiconductor devices, wherein the oxide is silica.
The preparation method of above-mentioned FinFET semiconductor devices, wherein the thickness of the epitaxial layer is more than 5nm
The preparation method of above-mentioned FinFET semiconductor devices, wherein the material of the semiconductor substrate is monocrystalline silicon.
The preparation method of above-mentioned FinFET semiconductor devices, wherein the material of the mask layer is silicon nitride.
The preparation method of above-mentioned FinFET semiconductor devices, wherein the epitaxial layer is that Ge-doped extension or carbon adulterate
Extension.
The preparation method of above-mentioned FinFET semiconductor devices, wherein the dielectric layer is high dielectric constant material layer
The preparation method of above-mentioned FinFET semiconductor devices, wherein the material of the high dielectric constant material layer is
HfO2。
The preparation method of above-mentioned FinFET semiconductor devices, wherein the gate material layers are metal or polysilicon.
Foregoing invention has the following advantages that or advantageous effect：
The invention discloses a kind of preparation method of FinFET semiconductor devices, this method is outer in being epitaxially-formed doping
Anisotropic using epitaxial layer and semiconductor substrate and the etch differential of oxide skin(coating) after prolonging layer, etching successively forms the fin of different height
Portion, then specified grid is formed separately by double grid (double gaet) using the method that machinery polishes, and then form 3T and 4T phases
In conjunction with FinFET.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in whole attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the purport of the present invention.
Fig. 1~15 are the flowage structure schematic diagrames of the preparation method of FinFET semiconductor devices in the embodiment of the present invention.
Specific implementation mode
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
The present embodiment is related to a kind of preparation method of FinFET semiconductor devices, specifically, this method comprises the following steps：
Step S1 provides semi-conductive substrate 1, in a preferred embodiment of the invention, the material of semiconductor substrate 1
For monocrystalline silicon, certain semiconductor substrate 1 can also other semi-conducting materials, due to the semiconductor substrate 1 and non-present invention changes
Into emphasis, just it will not go into details herein, structure as shown in Figure 1.
Step S2, doped epitaxial grows an epitaxial layer 2 on semiconductor substrate 1, in one preferred implementation of the present invention
In example, which is Ge-doped extension or carbon doped epitaxial；Preferably, the thickness of the epitaxial layer 2 be more than 5nm (such as 6nm,
10nm, 15nm, 20nm etc.)；Structure as shown in Figure 2.
Step S3 etches the epitaxial layer 2 in specified region to be exposed the upper surface of part semiconductor substrate 1, this refers to
Determining region can set according to concrete technology demand；Specifically, can be used wet-etching technology or dry etch process etching should
Epitaxial layer 2, structure as shown in Figure 3.
Step S4, deposited oxide layer 3 are equal with the exposed upper surface in the surface for exposing epitaxial layer 2 and semiconductor substrate 1
It is covered；In a preferred embodiment of the invention, which is specially：First, using the method for chemical vapor deposition
Deposition oxide is covered with the exposed upper surface in the surface for exposing epitaxial layer 2 and semiconductor substrate 1；Secondly, right
The top of the oxide carries out machinery and polishes, the exposed upper table in the surface and semiconductor substrate 1 for being exposed epitaxial layer 2 with formation
The oxide layer 3 that face is covered；Preferably, the material of the oxide layer 3 is silica；Structure as shown in Figure 4.
Step S5 forms patterned mask layer 4 on oxide layer 3；Patterned mask is formed on oxide layer 3
Layer 4 concrete technology be：First in 3 surface of oxide layer deposit one layer of mask layer 4, later formed with gate patterns photoresist with
Respectively by the portion of upper surface of the mask layer 4 on epitaxial layer 2 and on the semiconductor substrate 1 in above-mentioned specified region
The portion of upper surface of mask layer 4 covered, using the photoresist with gate patterns as mask etching mask layer 4 to oxide layer
3 upper surface stops forming patterned mask layer 4, i.e. the patterned mask layer 4 covering is located at the oxygen on epitaxial layer 2
Change the portion of upper surface of the portion of upper surface and the oxide layer 3 on the semiconductor substrate 1 in above-mentioned specified region of layer 3；
In one embodiment of the present of invention, the material of the mask layer 4 is silicon nitride；Structure as shown in Figure 5.
Step S6 is that mask etching oxide layer 3 to 2 upper surface of epitaxial layer stops with patterned mask layer 4；In the present invention
Embodiment in, take dry etch process or wet-etching technology to etch the oxide layer 3；Structure as shown in FIG. 6.
Step S7 is that mask etching epitaxial layer 2 to the upper surface of semiconductor substrate 1 stops shape with patterned mask layer 4
At the first fin, specifically, the mask layer 4 of the portion of upper surface to be covered in the oxide layer 3 being located on epitaxial layer 2 is mask
The upper surface of etching epitaxial layer 2 to semiconductor substrate 1 stops forming the first fin；First fin is suitable according to from bottom to up
Sequence includes epitaxial layer 2, oxide layer 3 and mask layer 4 successively；Structure as shown in Figure 7.
Step S8 continues to stop with the upper surface that patterned mask layer 4 is mask etching oxide layer 3 to semiconductor substrate 1
Only to form the second fin, specifically, to be covered in the oxide layer 3 being located on the semiconductor substrate 1 in above-mentioned specified region
The mask layer 4 of portion of upper surface is that mask etching oxide layer 3 to the upper surface of semiconductor substrate 1 stops forming the second fin,
Second fin includes oxide layer 3 and mask layer 4 successively according to sequence from bottom to up；And be apparent from by above-mentioned steps, this second
Fin and the first fin are contour；The thickness of oxide layer 3 in second fin is equal to oxide layer 3 and epitaxial layer 2 in the first fin
The sum of thickness, structure as shown in Figure 8.
Step S9 is the semiconductor substrate 1 of mask etching predetermined thickness with the mask layer 4 of the first fin and the second fin,
To form the substrate layer 11 below the first fin and the second fin, which can set according to concrete technology demand,
Remaining semiconductor substrate 1 (semiconductor substrate for being located at 11 lower section of substrate layer) is referred to as semiconductor substrate 12 below；Such as
Structure shown in Fig. 9.
Step S10, removal mask layer 4, the oxide layer 3 of the first fin and the oxide layer 3 of the second fin, in the reality of the present invention
It applies in example, using dry etch process or the oxide layer 3 and the second fin of wet-etching technology removal mask layer 4, the first fin
Oxide layer 3；Structure as shown in Figure 10.
Step S11, deposition of insulative material are covered with the semiconductor structure for forming step S10；In the reality of the present invention
It applies in example, which is oxide；Structure as shown in figure 11.
Step S12, etching insulating material is to form the portion of upper surface and substrate layer 11 that covering semiconductor substrate 12 exposes
Divide the insulating layer 5 of sidewall surfaces；Structure as shown in figure 12.
Step S13 forms dielectric layer 6 to expose the upper surface of insulating layer 5, substrate layer 11 on semiconductor substrate 12
Surface and epitaxial layer 2 expose surface covered, in a preferred embodiment of the invention, the dielectric layer 6
Material be high dielectric constant material；On this basis, further, which is HfO2；As shown in figure 13
Structure.
Step S14, deposition of gate material layer 7 is to be covered the upper surface of dielectric layer 6 and its side wall；In the present invention one
In a preferred embodiment, gate material layers 7 are metal gates, which is made of TIN/TaN/AL etc.；The grid material
The bed of material 7 will not necessarily use metal gates, can also use the works such as oxidation technology or moisture-generation process (ISSG) in situ
Skill forms oxide layer on the outside of raceway groove, and deposit polycrystalline silicon is as the gate material layers 7..Structure as shown in figure 14.
Step S15 carries out machinery to gate material layers 7 and dielectric layer 6 and polishes the upper surface stopping to epitaxial layer 2 to be formed
3T and 4T is combined FinFET semiconductor devices；Structure as shown in figure 15.
The invention discloses a kind of preparation method of FinFET semiconductor devices, this method is outer in being epitaxially-formed doping
Anisotropic using epitaxial layer and semiconductor substrate and the etch differential of oxide skin(coating) after prolonging layer, etching successively forms the fin of different height
Portion, then specified grid is formed separately by double grid using the method that machinery polishes, and then form the FinFET that 3T and 4T is combined
Semiconductor devices.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (9)
1. a kind of preparation method of FinFET semiconductor devices, which is characterized in that include the following steps：
Semiconductor substrate is provided, surface has the first fin and the second fin, and first fin is according to sequence from bottom to up
Successively include epitaxial layer, oxide layer and mask layer, second fin according to sequence from bottom to up successively include oxide layer and
Mask layer, and the sum of thickness of oxide layer of the epitaxial layer and first fin is equal to the oxide layer of second fin
Thickness；
Respectively using the mask layer of first fin and the second fin as the semiconductor substrate of mask etching predetermined thickness, with
Form the substrate layer below first fin and second fin；
Remove the oxide layer of the oxide layer and second fin of the mask layer, first fin；
Insulating layer is formed on the semiconductor substrate with the upper surface for exposing the semiconductor substrate and the substrate layer
Partial sidewall surface covering；
The side wall that dielectric layer is formed on the semiconductor substrate to expose the upper surface of the insulating layer, the substrate layer
And the surface of the epitaxial layer exposure is covered；
Deposition of gate material layer covers upper surface and its side wall of the dielectric layer, and is formed after polishing the gate material layers
The FinFET semiconductor devices；
Include in the step of semiconductor substrate surface forms first fin and second fin：
In the growing epitaxial layers of the semiconductor substrate；
Etching specifies the epitaxial layer in region to be exposed the upper surface of part semiconductor substrate；
Deposited oxide layer is covered with the exposed upper surface in the surface for exposing the epitaxial layer and the semiconductor substrate
Lid；
After forming patterned mask layer on the oxide layer, using the patterned mask layer as oxygen described in mask etching
Change layer to the epitaxial layer upper surface to stop；
Stop being formed as the upper surface of epitaxial layer described in mask etching to the semiconductor substrate using the patterned mask layer
After first fin, continue to etch upper surface stopping of the oxide layer to the semiconductor substrate to form second fin
Portion.
2. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the oxide layer is dioxy
SiClx.
3. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the thickness of the epitaxial layer
More than 5nm.
4. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate
Material is monocrystalline silicon.
5. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the material of the mask layer
For silicon nitride.
6. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the epitaxial layer is mixed for germanium
Miscellaneous extension or carbon doped epitaxial.
7. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the dielectric layer is Gao Jie
Dielectric constant material.
8. the preparation method of FinFET semiconductor devices as claimed in claim 7, which is characterized in that the high-k material
The material of the bed of material is HfO2.
9. the preparation method of FinFET semiconductor devices as described in claim 1, which is characterized in that the gate material layers are
Metal or polysilicon.
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| CN106449413B (en) * | 2016-10-26 | 2019-03-26 | 上海华力微电子有限公司 | Fin-shaped semiconductor devices and preparation method thereof |
| CN114530447B (en) * | 2022-04-24 | 2022-10-25 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1993136A1 (en) * | 2007-05-14 | 2008-11-19 | Interuniversitair Microelektronica Centrum (IMEC) | Multi-gate MOSFET device and method of manufacturing same |
| CN103594344A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing multi-height Fin EFT (field effect transistor) devices |
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| US7544994B2 (en) * | 2006-11-06 | 2009-06-09 | International Business Machines Corporation | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1993136A1 (en) * | 2007-05-14 | 2008-11-19 | Interuniversitair Microelektronica Centrum (IMEC) | Multi-gate MOSFET device and method of manufacturing same |
| CN103594344A (en) * | 2012-08-15 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing multi-height Fin EFT (field effect transistor) devices |
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