CN105448984B

CN105448984B - A kind of FinFET and preparation method thereof

Info

Publication number: CN105448984B
Application number: CN201410384118.9A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-08-06
Filing date: 2014-08-06
Publication date: 2018-09-07
Anticipated expiration: 2034-08-06
Also published as: CN105448984A

Abstract

The present invention provides a kind of FinFET and preparation method thereof, it is formed with fleet plough groove isolation structure (STI) by the groove between adjacent fin structure, and oxide layer and material are provided between shallow trench and fin structure and substrate as the insulation material layer of silicon oxynitride, isolation effect can be realized well, the Doped ions in fin structure and substrate are avoided to be diffused, the present invention can skip the ion implanting of C co or the F co of high dose in traditional FinFET preparation processes simultaneously, and then bombardment effect when reduction ion implanting is to the damage caused by substrate and fin structure；Further, the pattern of SSRW can also realize good holding, and can effectively improve carrier mobility, significant increase device performance.

Description

A kind of FinFET and preparation method thereof

Technical field

The present invention relates to a kind of semiconductor manufacturing process, specifically, are related to a kind of FinFET and preparation method thereof.

Background technology

Field-effect transistor (Field Effect Transistor, FET) participates in conduction by majority carrier, also referred to as Unipolar transistor.It belongs to voltage controlled semiconductor device.With input resistance is high, noise is small, low in energy consumption, dynamic range Greatly, it is easily integrated, there is no the advantages that secondary-breakdown phenomenon, safety operation area field width, be widely used in semiconductor preparation field In.Continuous pursuit with the continuous ripe and people of FET technology to high performance device, the Hu of University of California Berkeley Positive penetrating judgment awards research and development a kind of novel field-effect transistor-FinFET (fin field-effect transistor), in the framework of FinFET, lock Door, can be in the connecting and disconnecting of the both sides control circuit of circuit at the forked 3D frameworks of similar fin.This design can be substantially Improve circuit control and reduce leakage current (leakage current), the lock that can also substantially shorten transistor is long；Therefore FinFET has low in energy consumption, the small advantage of area, while can effectively inhibit short-channel effect and lower drain-induced gesture Building reduces effect, is gradually in high volume put into production at present.

Meanwhile carrier mobility is also the important index weighed device and had excellent performance, carrier mobility is got over It is high, it is meant that resistivity is smaller, and when passing through same current, power consumption is smaller, and current carrying capacity is bigger；Mobility is bigger simultaneously, The transition time needed is shorter, and the cutoff frequency of transistor is directly proportional to the carrier mobility of base area material, therefore improves Carrier mobility can not only reduce power consumption, moreover it is possible to improve the current carrying capacity of device.A kind of SSRW is developed at present (Super Steep Retrograde Well, super steep retrogressing trap) technology can effectively improve carrier mobility, but the technology It is only had obtained relatively broad application in the FET of plane, but is also difficult to being applied to SSRW technological perfectionisms at present In the preparation of FinFET.This is because in FinFET, if fin structure (Fin) width of protrusion is too small, SSRW is being carried out Ion implanting technique when, be injected into the ion of FinFET and easily generated during being heat-treated and diffuse to shallow trench Isolation structure (STI, Shallow Trench Isolation), to cause certain dopant dose to lose, especially in oxygen Spread even more serious in enhanced diffustion technique, after undergoing multiple doping and heat treatment, diffusion phenomena can be increasingly severe, And then the pattern of SSRW is influenced, so that device performance is promoted well.

Invention content

The present invention provides a kind of FinFET preparation methods, can effectively avoid and are applied in FinFET by SSRW, The phenomenon that adulterating the diffusion easy tod produce in the process, to improve the carrier mobility of FinFET.Concrete scheme is as follows：

A kind of FinFET preparation methods, wherein include the following steps：

A substrate is provided, the substrate is formed with several fin structures, is formed at the top of each fin structure Cushion oxide layer and mask layer；

An oxide layer is prepared to cover the surface that the substrate, fin structure, cushion oxide layer and mask layer expose, And the oxide layer at the top of each fin structure prepares a dielectric layer；

Prepare one layer of insulation material layer the surface of the dielectric layer is covered, while the insulation material layer by substrate with And the oxide layer of each fin structure side wall is covered；

Depositing isolation material layer will be filled between each fin structure, grind the spacer material layer to it is described absolutely The upper surface of edge material layer；

It is etched back the spacer material layer and forms fleet plough groove isolation structure, the overhead height of the fleet plough groove isolation structure is less than The overhead height of the fin structure；

The part insulation material layer, oxide layer and the dielectric layer, cushion oxide layer and mask layer are removed, will be located at Fin structure surface on remaining spacer material layer top planes is exposed；

One layer of gate oxide is prepared on exposed fin structure surface, deposit polycrystalline silicon is simultaneously ground.

Above-mentioned method, wherein the method further includes：

After the upper surface of the substrate prepares one layer of cushion oxide layer, ion implantation technology is carried out to the substrate, it Multi-lager semiconductor material layer is deposited on the cushion oxide layer afterwards, wherein be located at one layer of cushion oxide layer upper surface Semiconductor material layer is mask layer, and it is APF layers to be located at the layer of semiconductor material layer at the top of the semiconductor material layer；

After APF layers described in partial etching, one layer of side wall film of deposition is by remaining APF layers and under the remaining APF layers The surface of the semiconductor material layer exposure of side is covered；

The part side wall film is removed, and retains the side wall film for being located at the remaining APF layers side-walls, and then Remaining side wall film is performed etching, the sidewall structure of several strips is formed；

It is etched down in the substrate by mask of the sidewall structure, forms several fin structures in the substrate, it Extra semiconductor material layer is removed afterwards and retains the cushion oxide layer being located at the top of each fin structure and mask layer.

Above-mentioned method, wherein the substrate definition has NMOS area and the areas PMOS, right using masked ion implant process The NMOS area and the areas PMOS carry out the ion implantation technology respectively.

Above-mentioned method, wherein the multi-lager semiconductor material layer is followed successively by mask layer from bottom to top, the first oxide is covered Film, the first APF layers, the second oxide mask, first medium anti-reflecting layer and the second APF layers.

Above-mentioned method, wherein the dielectric layer is prepared using following technique：

After one layer of layer of dielectric material of deposition is covered in the upper surface of the oxide layer, the layer of dielectric material is selected Property etching, and retain be located at the fin structure top oxide layer above layer of dielectric material as the dielectric layer.

Above-mentioned method, wherein the material of the mask layer, dielectric layer and the side wall film is silicon nitride.

Above-mentioned method, wherein the method further includes：

After depositing the spacer material layer, once made annealing treatment；And

Technique is ground to the spacer material layer and then is once made annealing treatment.

Above-mentioned method, wherein using insulation material layer described in ALD process deposits.

Above-mentioned method, wherein the material of the insulation material layer is silicon oxynitride.

Above-mentioned method, wherein using spacer material layer described in FCVD process deposits.

A kind of FinFET, wherein including：

Substrate, the substrate are formed with several fin structures, shallow trench are formed between the adjacent fin structure Isolation structure, the top planes of the fleet plough groove isolation structure are less than the top planes of the fin structure；

Insulation material layer and oxide layer are provided between the fleet plough groove isolation structure and the fin structure and substrate, The oxide layer is covered in the upper surface of the substrate and the partial sidewall of each fin structure, the insulation material layer covering It is contacted in the upper surface of the oxide layer and with the fleet plough groove isolation structure；

The fin structure surface on the fleet plough groove isolation structure top planes is covered with one layer of gate oxidation Layer, polysilicon layer is covered on the gate oxide.

Above-mentioned FinFET, wherein the FinFET includes I/O device and core devices, and I/O device and core devices Definition has NMOS area and the areas PMOS.

Above-mentioned FinFET, wherein the material of the insulation material layer is silicon oxynitride.

Above-mentioned FinFET, wherein the insulation material layer is prepared using ALD techniques.

Above-mentioned FinFET, wherein the fleet plough groove isolation structure is the oxide prepared using FCVD techniques.

Groove of the present invention between adjacent fin structure is formed with shallow trench, and in shallow trench and fin structure and lining It is provided with oxide layer and material between bottom as the insulation material layer of silicon oxynitride, can realize isolation effect well, avoid fin-shaped Doped ions in structure and substrate are diffused, and improve carrier mobility, and then are reduced device power consumption and be greatly improved Device performance.

Description of the drawings

Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer Shape and advantage will become more apparent upon.Identical label indicates identical part in whole attached drawings.Not deliberately proportionally Draw attached drawing, it is preferred that emphasis is the purport of the present invention is shown.

Fig. 1~20 are a kind of flow chart of FinFET preparation methods provided by the present invention；

Figure 21 is a kind of structure chart of FinFET provided by the invention.

Specific implementation mode

The specific implementation mode of the present invention is further described below in conjunction with the accompanying drawings：

The present invention provides a kind of FinFET preparation methods, and can SSRW technologies solid be applied to well in the present invention FinFET prepare in, referring to Fig.1~20 shown in, be as follows,

Step S1：Semi-conductive substrate 1 is provided first, and surface prepares one layer of 2 (PAD of cushion oxide layer over the substrate Oxide).The substrate 1 includes IO (Input Output, input and output) device regions and core (CORE) device region, and IO Device region and core device region, which all define, NMOS area and the areas PMOS；Using masked ion implant process to NMOS area and PMOS Area carries out one or many ion implantation technologies respectively, is specifically：Using photoetching process, using photoresist by I/O device area And the areas PMOS in core device region are blocked, and then carry out ion implanting to NMOS area using photoresist as mask；Later again into The identical step of row, is blocked NMOS area using photoresist, and ion implanting is carried out to the areas PMOS.It should be noted that right The sequencing of NMOS area and the injection of the areas PMOS does not limit to above description, also first can carry out ion to the areas PMOS according to demand Then injection carries out ion implanting to NMOS area again, has no effect in the present invention.As shown in Fig. 1~2.

Step S2：Multi-lager semiconductor material layer is prepared in 2 upper surface of cushion oxide layer, specifically, the multi-lager semiconductor material The bed of material is followed successively by mask layer 3, the first oxide mask 4, the first APF (Advanced Patterning Film, figure from bottom to top Film) layer 5, the second oxide mask 6, first medium anti-reflecting layer (DARC, Dielectric Anti-Reflective Coating) the 7, second APF layers 8, as shown in figure 3, foring the composite construction of multi-lager semiconductor material on substrate 1.It is preferred that , the material of the mask layer 3 is silicon nitride；It is as hard mask layer, since APF has that the present invention selects APF layers herein simultaneously Excellent physical property is capable of providing high etching selectivity and low line edge roughness (LER), APF is applied in the present invention Good technique effect can be brought.It should be noted that due in the present invention, to I/O device area and core device region The technique carried out is identical, therefore only selects one of device region to be described in the following description, correspondingly, attached drawing Also it selects the technological process of one of device region as description, can be the schematic diagram in I/O device area shown in Fig. 3, or core Heart device region.

Step S3：Photoetching process is carried out, photoresist mask 10 is formed at the top of device, the specific steps are：First The upper surface of two APF layers 8 coats one layer of second medium anti-reflecting layer 9, to reduce in the exposure-processed light for carrying out photoetching process To the overexposure caused by photoresist；Then then at one layer photoresist of upper surface spin coating of second medium anti-reflecting layer 9 (or Photoresist), and it is exposed developing process, removal part photoresist and then formation photoresist mask 10 using a mask plate.Such as Fig. 4 It is shown.

Step S4：It is etch mask with photoresist mask 10, is performed etching downwards using dry etch process, and stop at 7 upper surface of first medium anti-reflecting layer forms structure shown in Fig. 5.Then deposit one layer of side wall film 11 by the surface of device into Row covering, it is preferred that the side wall film 11 is silicon nitride (SiN), forms structure shown in Fig. 6.Selective etch removes part Side wall film 11 simultaneously removes remaining second medium anti-reflecting layer 9 ', and side wall 11 ' is formed in the side wall of remaining second APF layers 8 ', After completing to the etching of side wall film 11, need to ensure that the thickness of final side wall 11 ' is sufficiently thin, which is conduct The etch mask of the Fin of subsequent technique, and the present invention is to apply in SSRW technologies simultaneously, it is therefore desirable to ensure the width of Fin It wants sufficiently narrow, is as shown in Figure 7 so that the FinFET for being formed and there is ideal pattern can be etched.Remove remaining second APF layers 8 ', in the present invention, the mask of dimension is selected according to the shape of remaining second APF layers 8 ' being distributed on substrate 1 Plate is to be removed it.Such as in an embodiment of the present invention, the second APF layers 8 ' after over etching are rectangular, therefore need The mask plate with rectangular aperture pattern is selected, and the patterns of openings on mask plate and remaining second APF layers 8 ' are one by one It is corresponding, and then realize and be only removed remaining second APF layers 8 '.As shown in Figure 8.Use the mask of another specification again later Each side wall 11 ' for surrounding a rectangle is cut off (Fin cut) by plate, to form the sidewall structure 11 of several strips ".

The step is described further in combination with Fig. 9 a~Fig. 9 c below, can refer to first shown in Fig. 9 a, The upper surface of one dielectric anti reflective layer 7 is formed with the second APF layers 8 ' of residue of several protrusions after over etching, is carried in the present invention In the embodiment supplied, each individually remaining second APF layers 8 ' are rectangle, therefore the side wall 11 ' formed is around remaining Second APF layers 8 ', as illustrated in fig. 9；After removing remaining second APF layers 8 ', then structure described in Fig. 9 b is formed；It is gone partly After cricoid side wall 11 ', then structure described in Fig. 9 c is formed, if being finally formed in the upper surface of first medium anti-reflecting layer 7 Dry strip sidewall structure 11 ".

Step S5：" it is etch mask, is performed etching downwards using non-dry etch process, until substrate 1 with sidewall structure 11 In to form several fin structure 1a as the Fin in FinFET, after forming fin structure 1a, by extra semiconductor material The bed of material is removed, while remaining cushion oxide layer 2 ', mask layer 3 ', the first oxygen are remained at the top of each fin structure 1a Compound mask 4 ', structure as shown in Figure 10.Due to being using side wall 11 " as etch mask, the fin structure 1a wide prepared Degree is all smaller.Why sidewall structure 11 is used " it is used as etch mask, this is because in current technology, using photoetching skill The photoresist that art is hardly formed narrower in width is used as etch mask, even if can be formed using advanced lithographic equipment very narrow Photoresist mask, but photoresist also easy tos produce phenomenon of collapsing since depth-width ratio is excessive；Therefore in the side of remaining APF layers 7 ' Wall formation prepares side wall 11 ', then removes remaining APF layers 8 ' and can realize expected effect with side wall 11 ' for etch mask. Since side wall is to be formed by silicon nitride film material using CVD deposition, it is easy to by the reaction condition for controlling deposition And then the width of side wall 11 ' is controlled, required sidewall structure 11 in a strip shape is formed after being cut to side wall 11 ' ", and with the side Wall construction 11 " is etched to substrate as etch mask, and then forms the fin structure 1a of required narrower width, form Figure 10 institutes Show structure.Device is cleaned again later, remaining first oxide mask 4 ' at the top of fin structure 1a is removed, such as Shown in Figure 11.

Step S6：Layer of oxide layer 12 is formed on the surface of device, and the oxide layer 12 is by substrate 1 ', fin structure 1a, surplus The surface covering of remaining cushion oxide layer 2 ' and the exposure of mask layer 3 ', forms structure shown in Figure 12；Then positioned at each fin-shaped knot 12 top of oxide layer at the top of structure 1a prepares a dielectric layer 13 again, as shown in figure 13, it is preferred that the dielectric layer is silicon nitride.Shape Concrete technology at the dielectric layer 13 is：After first one layer of layer of dielectric material of deposition is covered in the upper surface of oxide layer 12, and to being situated between The material bed of material carries out selective etch, and retains the layer of dielectric material for being located at 12 top of fin structure 1a top oxide layers as institute State dielectric layer 13.

Step S7：It prepares an insulation material layer 14 surface of dielectric layer 13 is completely covered, while an also insulation material The oxide layer of the oxide layer 12 on 1 ' surface of substrate and each fin structure 1a side walls also cover as shown in figure 14 by the bed of material 14. In the present invention, which preferably uses ALD (Atomic Layer Deposition, atomic layer deposition) work The silicon oxynitride (SiON) of rich nitrogen prepared by skill.Why silicon oxy-nitride material is used, is since silicon oxynitride is a kind of good Good heat-resisting material has excellent mechanical property, electrodynamic performance, thermodynamic property, chemical stability and resistance to elemental oxygen Characteristic, it is often more important that silicon oxy-nitride material can effectively inhibit the diffusion of the impurity elements such as boron, oxygen.Currently in microelectronic component master Will using silica as dielectric film, although silica membrane have lower dielectric constant, defect concentration and Residual stress, but the diffusion in impurity elements such as blocking boron, oxygen is not so good as silicon nitride；However the presence of the dangling bonds of silicon nitride Si And its with nitrogen content increase and increased characteristic causes film to show very high dielectric constant and tensile stress under certain condition, And the silicon nitride film of rich nitrogen contains very high positive charge and negative electrical charge defect, becomes the center of electric charge capture, and nitrogen oxidation Silicon thin film material has both the good characteristic of silicon nitride and silica, which is applied in the present invention can play resistance well Gear acts on, the diffusion for avoiding the ion adulterated in substrate from generating under the high temperature conditions, while also reducing and may be made to device At adverse effect.

Step S8：After the interstructural groove of adjacent fin-shaped is filled up completely by one layer of spacer material layer 15 of deposition, it is preferred that adopt With FCVD (Fluid Chemical Vapor Deposition, fluid chemistry vapor deposition) process deposits monoxide conduct Spacer material layer 15.FCVD techniques are a kind of advanced deposition technique that company of Applied Materials is developed, the deposition technique The groove with high-aspect-ratio can be filled well, while the material compactness filled is also fine, concrete technology is this Well known to field, it will not be described here.After the completion of depositing isolation material layer 15, needs once to be made annealing treatment, pass through annealing The compactness of spacer material layer 15 can be improved in processing, and improves the defect caused by ion implanting；It simultaneously can also be in step S1 The ion of middle doping is into line activating.The top that spacer material layer 15 is polished to insulation material layer 14 by CMP process is carried out later, so After can once made annealing treatment, and then improve the compactness of the spacer material layer after grinding 15 again, and to before The ion of injection carries out further activation and handles and improve defect.As shown in Figure 15~16.

Step S9：It is etched back remaining spacer material layer 15 ', forms fleet plough groove isolation structure (shallow trench Isolation, STI) 15 ", as shown in figure 17." the insulation material on top planes that removal is exposed to fleet plough groove isolation structure 15 The bed of material 14, oxide layer 12 and dielectric layer 13 and remaining mask layer 3 ', later again clean device, remove each fin-shaped knot Remaining cushion oxide layer 2 ' at the top of structure 1a, after the completion of step, to by " the fin on top planes of fleet plough groove isolation structure 15 Shape structure 1a is fully exposed, and forms structure shown in Figure 18

Step S10：Stronger gate oxide (the Gate of one layer of compactness is grown on the surfaces fin structure 1a exposed Oxide, abbreviation grid oxygen) 16.Thermal oxidation technology (HTO) can be selected and form one layer of thin silica on the surface of fin structure 1a Layer is passed through oxygen under the high temperature conditions, oxygen is reacted with the silicon generation for being exposed to the outer surfaces fin structure 1a, and then is formed Layer of silicon dioxide layer is as grid oxygen；Last redeposition polysilicon (poly) layer 17 simultaneously carries out CMP process.Specifically it can refer to attached drawing 19~20.

The present invention is formed with fleet plough groove isolation structure between adjacent fin structure, and in fin structure and shallow ditch groove structure Between be provided with oxide layer and insulation material layer, in the present invention, select silicon oxynitride as under insulating materials hot conditions The phenomenon that produced diffusion；Preparation method using the present invention simultaneously, due to the phenomenon that effectively doped chemical being inhibited to spread, because This can skip the ion implanting of the C-co or F-co of high dose in traditional FinFET preparation processes, and then reduce banging for ion implanting Effect is hit to the damage caused by substrate and fin structure；Further, the pattern of SSRW can realize good holding, and can Effectively improve carrier mobility, significant increase device performance.

The present invention also provides a kind of FinFETs using prepared by SSRW techniques simultaneously, with reference to shown in Figure 21, Including IO (Input Output) device regions and core (CORE) device region.In the present invention, due to I/O device area and core device The structure in part area is identical, therefore only chooses one of device region below and be described, but those skilled in the art It should be understood that arrangement described below is all present in I/O device area and core device region, it is specific as follows：

I/O device area and core device region be both provided with one with ion doping type substrate 101, and I/O device area and And core device region defines NMOS area and the areas PMOS.Fleet plough groove isolation structure is formed between adjacent fin structure 101 105, which is the oxide skin(coating) that is deposited using FCVD techniques, and the fleet plough groove isolation structure 105 Top planes are less than the top planes of fin structure 102, so that the upper part protrusion of each fin structure 102.Positioned at shallow 102 surface of fin structure on 105 top planes of groove isolation construction is covered with one layer of gate oxide 106, is located at gate oxidation It is covered with polysilicon layer (not indicated in figure) on layer 106.

Further, one layer of insulation is also formed between fleet plough groove isolation structure 105 and fin structure 102 and substrate 101 Material layer 104 and layer of oxide layer 103, insulation material layer 104 are covered in the upper surface of oxide layer 103, oxide layer 103 and fin-shaped Structure 102 and substrate 101 form contact.In the present invention, insulation material layer 104 is the rich nitrogen that is deposited using ALD techniques Silicon oxy-nitride material layer.

Since FinFET provided by the present invention has structure as above, shallow trench is formed between adjacent fin structure Isolation structure, and it is nitrogen oxidation to be provided with oxide layer and one layer of material between fleet plough groove isolation structure and fin structure and substrate The insulation material layer of silicon can be realized isolation effect, be avoided in hot conditions well due to the good isolation characteristic of silicon oxynitride Under, the Doped ions in fin structure and substrate easy to produce diffusion, improve carrier mobility, and greatly improve device Performance.

In conclusion after preparation forms fin structure, shallow ridges is formed between adjacent fin structure for above example Recess isolating structure, and it is nitrogen oxidation to be also formed with oxide layer and one layer of material between shallow ditch groove structure and fin structure and substrate The insulation material layer of silicon can avoid the element adulterated in fin structure to external diffusion well.Simultaneously using provided by the present invention Preparation method can skip the ion implanting of the C-co or F-co of high dose in traditional FinFET preparation processes, and then reduce ion Bombardment effect when injection is to the damage caused by substrate and fin structure；Further, the pattern of SSRW can also be realized good Good holding, and carrier mobility can be effectively improved, significant increase device performance.

Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc. Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention In the range of technical solution protection.

Claims

1. a kind of FinFET preparation methods, which is characterized in that include the following steps：

A substrate is provided, the substrate is formed with several fin structures, liner is formed at the top of each fin structure Oxide layer and mask layer；

An oxide layer is prepared to cover the surface that the substrate, fin structure, cushion oxide layer and mask layer expose, and Oxide layer at the top of each fin structure prepares a dielectric layer；

It prepares one layer of insulation material layer to cover the surface of the dielectric layer, while the insulation material layer is by substrate surface Oxide layer and the oxide layer of each fin structure side wall are covered；

Depositing isolation material layer will be filled between each fin structure, grind the spacer material layer to the insulation material The upper surface of the bed of material；

It is etched back the spacer material layer and forms fleet plough groove isolation structure, the overhead height of the fleet plough groove isolation structure is less than described The overhead height of fin structure；

The part insulation material layer, oxide layer and the dielectric layer, cushion oxide layer and mask layer are removed, residue will be located at Fin structure surface on spacer material layer top planes is exposed；

One layer of gate oxide is prepared on exposed fin structure surface, deposit polycrystalline silicon is simultaneously ground；

The material of the insulation material layer is silicon oxynitride.

2. the method as described in claim 1, which is characterized in that the method further includes：

After the upper surface of the substrate prepares one layer of cushion oxide layer, ion implantation technology, Zhi Houzai are carried out to the substrate Multi-lager semiconductor material layer is prepared on the cushion oxide layer, wherein one and half positioned at cushion oxide layer upper surface lead Body material layer is mask layer, and it is APF layers to be located at the layer of semiconductor material layer at the top of the semiconductor material layer；

After APF layers described in partial etching, one layer of side wall film of deposition is by remaining APF layers and below the remaining APF layers The surface of semiconductor material layer exposure is covered；

The part side wall film is removed, and retains the side wall film for being located at the remaining APF layers side-walls, and then to surplus Remaining side wall film performs etching, and forms the sidewall structure of several strips；

It is etched down in the substrate by mask of the sidewall structure, forms several fin structures, Zhi Houyi in the substrate Except extra semiconductor material layer and retain the cushion oxide layer being located at the top of each fin structure and mask layer.

3. method as claimed in claim 2, which is characterized in that the substrate definition has NMOS area and the areas PMOS, using mask Ion implantation technology carries out the ion implantation technology respectively to the NMOS area and the areas PMOS.

4. method as claimed in claim 2, which is characterized in that the multi-lager semiconductor material layer is followed successively by mask from bottom to top Layer, the first oxide mask, the first APF layers, the second oxide mask, first medium anti-reflecting layer and the second APF layers.

5. the method as described in claim 1, which is characterized in that prepare the dielectric layer using following technique：

After one layer of layer of dielectric material of deposition is covered in the upper surface of the oxide layer, is carried out to the layer of dielectric material selective quarter Erosion, and retain the layer of dielectric material being located above the fin structure top oxide layer as the dielectric layer.

6. method as claimed in claim 2, which is characterized in that the mask layer, dielectric layer and the side wall film material It is silicon nitride.

7. the method as described in claim 1, which is characterized in that the method further includes：

After depositing isolation material layer, once made annealing treatment；And

8. the method as described in claim 1, which is characterized in that using insulation material layer described in ALD process deposits.

9. the method as described in claim 1, which is characterized in that using spacer material layer described in FCVD process deposits.

10. a kind of FinFET, which is characterized in that it is formed using as prepared by any one of claim 1-9, including：

Substrate, the substrate are formed with several fin structures, shallow trench isolation are formed between the adjacent fin structure Structure, the top planes of the fleet plough groove isolation structure are less than the top planes of the fin structure；

Insulation material layer and oxide layer are provided between the fleet plough groove isolation structure and the fin structure and substrate, it is described Oxide layer is covered in the upper surface of the substrate and the partial sidewall of each fin structure, the insulation material layer are covered in institute It states the upper surface of oxide layer and is contacted with the fleet plough groove isolation structure；

The fin structure surface on the fleet plough groove isolation structure top planes is covered with one layer of gate oxide, position It is covered with polysilicon layer on the gate oxide.

11. FinFET as claimed in claim 10, which is characterized in that the FinFET includes I/O device and core devices, And I/O device and core devices define NMOS area and the areas PMOS.

12. FinFET as claimed in claim 10, which is characterized in that the material of the insulation material layer is silicon oxynitride.

13. FinFET as claimed in claim 10, which is characterized in that prepare the insulation material layer using ALD techniques.

14. FinFET as claimed in claim 10, which is characterized in that the fleet plough groove isolation structure is using FCVD technique systems Standby oxide.