CN109860291B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN109860291B CN109860291B CN201711241953.7A CN201711241953A CN109860291B CN 109860291 B CN109860291 B CN 109860291B CN 201711241953 A CN201711241953 A CN 201711241953A CN 109860291 B CN109860291 B CN 109860291B
- Authority
- CN
- China
- Prior art keywords
- fin
- layer
- isolation
- forming
- liner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate and a fin portion protruding out of the substrate, wherein the fin portion comprises a first fin portion located on the surface of the substrate and a second fin portion located on the top of the first fin portion; forming a first liner layer on the side wall of the first part of the fin part; forming a second liner layer on the surface of the first liner layer, the top of the second part of the fin part and the side wall; forming an isolation film covering the second liner layer on the substrate, wherein the top of the isolation film is higher than or flush with the top of the fin part; removing the second liner layer and the isolation film which are higher than the top of the first part of the fin part, and forming an isolation layer by the residual isolation film; and forming a gate oxide layer on the top of the fin part and the surface of the side wall exposed by the isolation layer. According to the invention, the stress applied to the side wall of the fin part by the isolation layer can be effectively weakened by the first liner layer and the second liner layer, so that the fin part is prevented from being bent, and the process window for forming the isolation layer is large, thereby being beneficial to improving the forming quality of the isolation layer.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has correspondingly continued to decrease. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and short-channel effects (SCE) are more likely to occur.
The fin field effect transistor (FinFET) has outstanding performance in the aspect of inhibiting short channel effect, and the grid electrode of the FinFET can control the fin part at least from two sides, so that compared with a planar MOSFET, the grid electrode of the FinFET has stronger channel control capability, and the short channel effect can be well inhibited.
However, the performance of the prior art semiconductor structures is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can weaken the stress applied to the side wall of a fin part by an isolation layer in the process of forming a gate oxide layer, thereby avoiding the fin part from bending, and the process window for forming the isolation layer is large, thus being beneficial to improving the forming quality of the isolation layer, and in addition, the surface of the fin part can be prevented from being oxidized in the process of forming the isolation layer.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a fin portion protruding out of the substrate, wherein the fin portion comprises a first fin portion located on the surface of the substrate and a second fin portion located on the top of the first fin portion; forming a first liner layer on the side wall of the first part of the fin part; forming a second liner layer on the surface of the first liner layer, the top of the second part of the fin part and the side wall; forming an isolation film covering the second liner layer on the substrate, wherein the top of the isolation film is higher than the top of the fin portion or is flush with the top of the fin portion; removing the second liner layer and the isolation film which are higher than the top of the first part of the fin part, and forming an isolation layer by the residual isolation film; and forming a gate oxide layer on the top of the fin part and the surface of the side wall exposed by the isolation layer.
Optionally, before the gate oxide layer is formed, widths of the isolation layers on two sides of the fin portion are not equal.
Optionally, the number of the fin portions is multiple, before the gate oxide layer is formed, the widths of the isolation layers on two sides of some fin portions are equal, and the widths of the isolation layers on two sides of the other fin portions are not equal.
Optionally, the substrate comprises edge regions and a central region located between adjacent edge regions; the widths of the isolation layers on the two sides of the fin portion in the central area are equal, and the widths of the isolation layers on the two sides of the fin portion in the edge area are unequal.
Optionally, the top of the isolation layer is flush with the top of the first part of the fin portion; and in the step of forming the gate oxide layer, forming the gate oxide layer on the top and the side wall of the second part of the fin part exposed out of the isolation layer.
Optionally, the top of the isolation layer is lower than the top of the first portion of the fin portion; in the process step of forming the isolation layer, the first liner layer, the second liner layer and the isolation film on the sidewall of the first part of the fin portion are also removed, and the sidewall of the first part of the fin portion is exposed; and in the step of forming the gate oxide layer, forming the gate oxide layer on the side wall of the first part of the fin part, the top of the second part of the fin part and the side wall which are exposed out of the isolation layer.
Optionally, the thickness of the isolation film on the sidewall of the first portion of the fin portion is removed
Optionally, the process of forming the isolation film includes: forming an initial isolation film covering the second liner layer on the substrate, wherein the top of the initial isolation film is higher than the top of the second liner layer on the top of the second part of the fin portion; and carrying out planarization treatment on the initial isolation film to form the isolation film.
Optionally, the top of the isolation film is higher than the top of the second liner layer on the top of the second portion of the fin; or the top of the isolation film is flush with the top of the second liner layer on the second top of the fin portion.
Optionally, the forming process of the initial isolation film includes a fluid chemical vapor deposition process or a high aspect ratio chemical vapor deposition process.
Optionally, the sum of the thickness of the first liner layer and the thickness of the second liner layer is
Optionally, the ratio of the thickness of the first liner layer to the thickness of the second liner layer is 0.5-1.
Optionally, a ratio of the height of the first portion of the fin to the height of the second portion of the fin is 0.5-1.25.
Optionally, the gate oxide layer is formed by a thermal oxidation process.
Optionally, the temperature of the thermal oxidation treatment process is 800-1050 ℃.
Optionally, the process step of forming the first liner layer includes: forming a first liner film on the side wall of the first part of the fin part, the top of the second part of the fin part and the side wall; forming an anti-reflection coating on the substrate, wherein the top of the anti-reflection coating is flush with the top of the first part of the fin; removing the first liner film on the top and the side wall of the second part of the fin part, and forming a first liner layer by the remaining first liner film; and removing the anti-reflection coating.
Optionally, the first liner layer is made of silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbonitride; the second liner layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, amorphous silicon or polysilicon.
Accordingly, the present invention also provides a semiconductor structure comprising: the fin part comprises a first fin part positioned on the surface of the substrate and a second fin part positioned on the top of the first fin part; a first liner layer on sidewalls of a first portion of the fin; a second liner layer on a surface of the first liner layer, the first liner layer being located between the first portion of the fin and the second liner layer; the isolation layer is positioned on the substrate and covers the surface of the second liner layer, and the top of the isolation layer is flush with the top of the second liner layer; and the gate oxide layer is positioned on the top of the fin part and the surface of the side wall, which are exposed out of the isolation layer.
Optionally, the substrate includes edge regions and a central region located between adjacent edge regions, the substrate has a plurality of fin portions, the widths of the isolation layers on both sides of the fin portion in the central region are equal, and the widths of the isolation layers on both sides of the fin portion in the edge region are not equal.
Optionally, the sum of the thickness of the first liner layer and the thickness of the second liner layer is
The ratio of the height of the first part of the fin to the height of the second part of the fin is 0.5-1.25.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the forming method of the semiconductor structure, a first liner layer is formed on the side wall of the first part of the fin part; forming a second liner layer on the surface of the first liner layer, the top of the second part of the fin part and the side wall; and forming an isolation film covering the second liner layer on the substrate. Compared with the second liner layer on the surface of the first liner layer, the distance between the second liner layers on the side walls of the second parts of the adjacent fins is larger, so that the process window for forming the isolation film is larger; the larger process window helps to improve the quality of the isolation film formation. And because a first liner layer and a second liner layer are formed between the isolation film and the surface of the fin portion, the first liner layer and the second liner layer can play a role in protecting the surface of the fin portion, and can prevent the surface of the fin portion from being oxidized in the process of forming the isolation film. And after the isolation film is formed, removing the second liner layer and the isolation film which are higher than the top of the first part of the fin part, forming an isolation layer by the residual isolation film, and then forming a gate oxide layer on the top and the side wall surface of the fin part exposed by the isolation layer. Because the process environment who forms gate oxide makes isolation layer inner structure change, consequently is forming gate oxide's in-process the isolation layer is right the first partial lateral wall of fin portion applys the stress action, the isolation layer with be formed with first gasket layer and second gasket layer between the first partial lateral wall of fin portion, first gasket layer and second gasket layer can play certain cushioning effect, first gasket layer and second gasket layer thickness sum are big, are favorable to improving the cushioning effect of first gasket layer and second gasket layer to effectively weaken the stress size that the isolation layer applyed to the first partial lateral wall of fin portion, avoid the fin portion takes place to buckle, improve semiconductor structure's performance.
In the alternative, the ratio of the height of the first part of the fin to the height of the second part of the fin is 0.5-1.25, and the ratio of the height of the first part of the fin to the height of the second part of the fin is proper, so that on one hand, the size of the isolation layer is ensured to be proper, and the stress applied to the fin by the isolation layer is reduced; on the other hand, the thickness of the isolation layer meets the requirement, so that the insulation effect of the isolation layer is ensured.
In an alternative, the sum of the thickness of the first and second liner layers is
The sum of the thickness of the first liner layer and the thickness of the second liner layer is proper, so that on one hand, the first liner layer and the second liner layer have good buffering effects, and the stress action of the isolation layer on the side wall of the fin part can be effectively weakened; on the other hand, the depth-to-width ratio of the area between the second liner layers on the first portions of the adjacent fins is proper, so that the filling capacity of the isolation film is improved, and the forming quality of the isolation film is improved.
In an alternative scheme, the temperature of the thermal oxidation treatment process is 800-1050 ℃, and the process temperature of the thermal oxidation treatment process is proper, so that the forming quality of the gate oxide layer is ensured; on the other hand, the stress applied to the side wall of the fin part by the isolation layer is reduced.
Drawings
Fig. 1to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the art, the performance of the conventional semiconductor structure is still to be improved.
Now, an analysis is performed in combination with a method for forming a semiconductor structure, and fig. 1to 5 are schematic structural diagrams corresponding to respective steps in the method for forming a semiconductor structure, where the steps of the process for forming a semiconductor structure mainly include:
referring to fig. 1, a substrate 10 and a fin 20 protruding from the substrate 10 are provided.
The substrate 10 includes edge regions i and a central region ii between adjacent edge regions i.
The number of the fin portions 20 is plural, and the plural fin portions 20 are arranged on the substrate 10 at equal intervals. The distance between the fin portion 20 of the edge region i and the sidewall of the substrate 10 is a first distance M1, the distance between the fin portion 20 of the edge region i and the adjacent fin portion 20 is a second distance M2, and M1 ≠ M2.
Referring to fig. 2, a liner layer 32 is formed on the top and sidewalls of the fin 20, and the liner layer 32 also covers the top of the substrate 10.
Referring to fig. 3, an isolation film 61 is formed on the substrate 10to cover the liner layer 32, and the top of the isolation film 61 is higher than the surface of the liner layer 32 on the top of the fin 20.
Referring to fig. 4, a portion of the thickness of the isolation film 61 (see fig. 3) and the liner layer 32 on the top and a portion of the sidewall of the fin 20 are removed, an isolation layer 62 is formed by remaining the isolation film 61, the top of the isolation layer 62 is lower than the top of the fin 20, and the top of the isolation layer 62 is flush with the top of the liner layer 32.
Referring to fig. 5, a gate oxide layer 70 is formed on the top and sidewall surfaces of the fin 20 exposed by the isolation layer 62 by a thermal oxidation process.
The semiconductor structure formed by the above method has poor performance, and the reason for this is analyzed to be that:
in the process step of forming the gate oxide layer 70, the isolation layer 62 may be affected by a process environment in which the gate oxide layer 70 is formed, for example, a temperature in the process environment, so that an internal structure of the isolation layer 62 changes to apply stress to the sidewall of the fin 20, and a magnitude of the stress applied to the fin 20 by the isolation layer 62 is related to a volume of the isolation layer 62. Since M1 ≠ M2, the volumes of the isolation layers 62 on the two sides of the fin portion 20 in the edge region i are different, which results in that the magnitudes of the stresses applied by the isolation layers 62 on the sidewalls of the fin portion 20 in the edge region i are different.
When the gate oxide layer 70 is formed by a thermal oxidation process, because the process temperature of the thermal oxidation process is high, the isolation layer 62 applies a greater stress to the sidewalls of the fin portion 20 in a high temperature environment, which may cause severe imbalance of the stress applied to the sidewalls of the fin portion 20 at the edge region i, thereby causing the fin portion 20 at the edge region i to bend.
The liner layer 32 is formed between the sidewall of the isolation layer 62 and the sidewall of the fin portion 20, and the liner layer 32 has a certain buffer effect on the stress applied by the isolation layer 62 on the sidewall of the fin portion 20. The greater the thickness of the cushion layer 32, the better the cushioning effect. However, although the method of increasing the thickness of the liner layer 32 can weaken the stress applied by the isolation layer 62 to the fin 20, the process window for forming the isolation film 61 is small, so that the ability of the isolation film 61 to fill the region between the liner layers 32 on the sidewalls of the adjacent fins 20 is poor, which results in poor quality of the formed isolation film 61 and thus poor quality of the isolation layer 62.
To this end, the present invention provides a method for forming a semiconductor structure, comprising: the fin part comprises a first fin part positioned on the surface of the substrate and a second fin part positioned on the top of the first fin part; forming a first liner layer on the side wall of the first part of the fin part; forming a second liner layer on the surface of the first liner layer, the top of the second part of the fin part and the side wall; forming an isolation film covering the second liner layer on the substrate, wherein the top of the isolation film is higher than the top of the fin portion or is flush with the top of the fin portion; removing the second liner layer and the isolation film which are higher than the top of the first part of the fin part, and forming an isolation layer by the residual isolation film; and forming a gate oxide layer on the top of the fin part and the surface of the side wall exposed by the isolation layer.
The isolation layer is influenced by the process environment in the process of forming the gate oxide layer and is right the stress is exerted to the fin portion side wall, the first liner layer reaches the second liner layer is located the isolation layer with between the fin portion side wall, just the first liner layer reaches the total sum of second liner layer thickness is big, consequently the first liner layer reaches the buffering effect of the stress that the second liner layer was exerted on the fin portion side wall to the isolation layer is good, can effectively weaken the isolation layer is right the stress size that the fin portion side wall was exerted, thereby avoids the fin portion takes place to buckle, improves semiconductor structure's performance. In addition, before the isolation film is formed, compared with the second liner layer on the first liner layer, the distance between the second liner layers on the sidewalls of the second portions of the adjacent fins is larger, that is, a process window for forming the isolation film is larger, and the larger process window is beneficial to improving the formation quality of the isolation film. In addition, before the isolation film is formed, the first liner layer and the second liner layer on the fin portion can play a role in protecting the surface of the fin portion, and the surface of the fin portion can be prevented from being oxidized in the process of forming the isolation film.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 15 are schematic cross-sectional views corresponding to steps of a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 6, a substrate 100 and a fin 200 protruding from the substrate 100 are provided, where the fin 200 includes a fin first portion 210 located on a surface of the substrate 100 and a fin second portion 220 located on a top of the fin first portion 210.
In this embodiment, the substrate 100 includes edge regions i and center regions ii between adjacent edge regions i.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a glass substrate.
In this embodiment, the number of the fin portions 200 is plural, and the plural fin portions 200 are arranged on the substrate 100 at equal intervals. The distance between the fin part 200 in the central area II and the adjacent fin parts 200 at two sides is equal; one side of the fin portion 200 of the edge region i is adjacent to the side wall of the substrate 100, the other side of the fin portion 200 of the center region ii is adjacent to the side wall of the substrate 100, the distance between the fin portion 200 of the edge region i and the side wall of the substrate 100 is N1, the distance between the fin portion 200 of the edge region i and the adjacent fin portion 200 is N2, and N1 is not equal to N2.
A first liner layer is subsequently formed on the sidewall of the first portion 210 of the fin, where in this embodiment, the first portion 210 of the fin is used to define a position of the first liner layer.
Subsequently forming a second liner layer on the surface of the first liner layer, the top and the sidewalls of the second portion 220 of the fin portion; an isolation film covering the second pad layer is formed on the substrate 100. Because a first liner layer and a second liner layer are formed on the sidewall of the first portion 210 of the fin, wherein the first liner layer is located between the sidewall of the first portion 210 of the fin and the second liner layer, the distance between adjacent second liner layers on the sidewall of the first portion 210 of the fin is smaller than the distance between adjacent second liner layers on the sidewall of the second portion 220 of the fin.
If the height of the first portion 210 of the fin portion is too large, the aspect ratio of the region between the second liner layers on the sidewalls of the first portions 210 of adjacent fin portions is too high, which may result in poor filling capability of the formed isolation film, and affect the formation quality of the isolation film. If the height of the first portion 210 of the fin portion is too small, the isolation film higher than the top of the first portion 210 of the fin portion is removed subsequently to form an isolation layer, so that the thickness of the isolation layer is too small, and the isolation layer has poor insulating property. In this embodiment, the fin first portion 210 has a height of
Subsequently, the isolation film higher than the top of the first portion 210 of the fin portion is removed to form an isolation layer; and then forming a gate oxide layer on the top of the fin part and the surface of the side wall exposed by the isolation layer. If the ratio of the height of the first fin portion 210 to the height of the second fin portion 220 is too large, the thickness of the formed isolation layer is too large, and further the volumes of the isolation layers on the two sides of the fin portion 200 are too large, so that in the process of forming the gate oxide layer, the stress applied by the isolation layer to the side wall of the first fin portion 210 is too large. If the ratio of the height of the first portion 210 of fins to the height of the second portion 220 of fins is too small, the thickness of the subsequently formed isolation layer is too small, resulting in poor insulating properties of the isolation layer. In this embodiment, the ratio of the height of the first portion 210 of fins to the height of the second portion 220 of fins is 0.5-1.25.
In this embodiment, the material of fin 200 is silicon, i.e., the material of fin first portion 210 and fin second portion 220 is silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In other embodiments, the fin portion of the central region has the same distance from the adjacent fin portions on two sides, and the fin portion of the remaining central region has the same distance from the adjacent fin portions on two sides.
In addition, in other embodiments, the number of the fin portion may also be one, and distances between sidewalls of two sides of the fin portion and the sidewalls of the adjacent substrate are not equal.
A first liner layer is subsequently formed on the sidewalls of the first portion 210 of the fin, and the forming steps of the first liner layer are described in detail with reference to fig. 7 to 9.
Referring to fig. 7, a first liner film 310 is formed on sidewalls of the fin first portion 210, a top of the fin second portion 220, and sidewalls.
In this embodiment, the first liner film 310 further covers the surface of the substrate 100 exposed by the fin portion 200.
In this embodiment, the material of the first liner film 310 is silicon oxide. In other embodiments, the material of the first liner film may also be silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
The first liner film 310 on the top and sidewalls of the second portion of the fin 220 is subsequently removed to form a first liner layer, and a second liner layer is formed on the surface of the first liner layer and on the top and sidewalls of the second portion of the fin 220. If it is the firstIf the thickness of the liner film 310 is too small, the thickness of the first liner layer is too small, which results in an excessively large thickness of the second liner layer, and an excessively small interval between the second liner layers on the sidewalls of the second portions 220 of adjacent fins, so that a process window for forming an isolation film subsequently is too small, which affects the formation quality of the isolation film. If the thickness of the first liner film 310 is too large, the thickness of the second liner layer will be too small, so that the second liner layer has a poor protection effect on the top and sidewalls of the second portion of the fin portion 220, and the surface of the second portion of the fin portion 220 is easily oxidized in the subsequent formation of the isolation film. In this embodiment, the thickness of the first liner film 310 is
Referring to fig. 8, an anti-reflective coating 400 is formed on the substrate 100, the top of the anti-reflective coating 400 being flush with the top of the fin first portion 210.
In this embodiment, the material of the anti-reflective coating 400 includes silicon-containing oxycarbide.
The first liner film 310 on the top and sidewalls of the second portion of fins 220 is subsequently removed, and the anti-reflective coating 400 serves to protect the first liner film 310 on the sidewalls of the first portion of fins 210.
The process steps for forming the anti-reflective coating 400 include: forming an anti-reflection coating film on the substrate 100 to cover the first liner film 310, wherein the top of the anti-reflection coating film is higher than the surface of the first liner film 310 on the top of the second portion 220 of the fin portion or is flush with the surface of the first liner film 310; and etching to remove the anti-reflection coating higher than the top of the first fin portion 210 to form the anti-reflection coating 400.
Referring to fig. 9, the first liner film 310 on the top and sidewalls of the fin second portion 220 is removed (refer to fig. 8), and a first liner layer 320 is formed by remaining the first liner film 310.
In this embodiment, the first liner film 310 on the top and the sidewalls of the second portion 220 of the fin portion is removed by a dry etching process. The dry methodThe technological parameters of the etching process comprise: the etching gas comprises He and NH3And NF3Wherein, the gas flow rate of He is 600sccm to 2000sccm, NH3The gas flow rate of (1) is 200sccm to 500sccm, NF3The flow rate of the etching gas is 20sccm to 200sccm, the pressure of the chamber is 2Torr to 10Torr, and the flowing time of the etching gas is 20s to 100 s.
In this embodiment, the material of the fin portion second portion 220 is silicon, and the material of the first liner film 310 is silicon oxide; the dry etching process has a high etching selectivity ratio for the first liner film 310 and the fin portion second portion 220, so as to avoid etching the surface of the fin portion second portion 220 in the process of removing the first liner film 310.
A second liner layer is subsequently formed on the surface of the first liner layer 320, the top and sidewalls of the fin second portion 220, and an isolation film is formed on the substrate 100 to cover the second liner layer. If the thickness of the first liner layer 320 is too small, and correspondingly, the thickness of the second liner layer is too large, the interval between the second liner layers on the sidewalls of the second portions 220 of the adjacent fins is too small, so that the process window for forming the isolation film subsequently is too small, and the formation quality of the isolation film is affected. If the thickness of the first liner layer 320 is too large, and correspondingly, the thickness of the second liner layer 320 is too small, the second liner layer has a poor protection effect on the top and the sidewalls of the second portion of the fin 220, so that the surface of the second portion of the fin 220 is easily oxidized in the subsequent formation of the isolation film. In this embodiment, the thickness of the first liner layer 320 is equal to that of the first liner film 310, and is
In this embodiment, after the first liner layer 320 is formed, the anti-reflective coating 400 is removed.
Referring to fig. 10, a second liner layer 500 is formed on the surface of the first liner layer 320, on the top and sidewalls of the fin second portion 220.
The function of the second liner layer 500 includes two aspects: on one hand, the second liner layer 500 covers the top and the sidewalls of the second portion 220 of the fin portion to protect the top and the sidewalls of the second portion 220 of the fin portion, and an isolation film covering the second liner layer 500 is formed on the substrate 100 subsequently, so that the top and the sidewalls of the second portion 220 of the fin portion can be prevented from being oxidized in the step of forming the isolation film. On the other hand, the isolation film with a part of thickness is removed subsequently to form an isolation layer, and a gate oxide layer is formed on the top and the sidewall surface of the fin portion 200 exposed by the isolation layer. The isolation layer is affected by a process environment to apply stress to the sidewall of the fin portion 200 in the process of forming the gate oxide layer, and the second liner layer 500 and the first liner layer 320 can weaken the stress applied by the isolation layer to the sidewall of the fin portion 200.
If the thickness of the second liner layer 500 is too thick, which results in too high aspect ratio of the region between the second liner layers 500 on the sidewalls of the adjacent fins 200, then forming an isolation film covering the second liner layer 500 on the substrate 100 will cause poor filling capability of the isolation film, and affect the formation quality of the isolation film; if the thickness of the second liner layer 500 is too thin, the protection effect of the second liner layer 500 on the top and sidewall surfaces of the second portion 220 of the fin will be affected, so that the surface of the second portion 220 of the fin is easily oxidized during the formation of the isolation film. In this embodiment, the thickness of the second liner layer 500 is
An isolation film covering the second liner layer 500 is formed on the substrate 100, and if the sum of the thickness of the first liner layer 320 and the thickness of the second liner layer 500 is too large, the distance between the second liner layers 500 on the first portions 210 of the adjacent fins is too small, so that the capability of the isolation film to fill the area between the second liner layers 500 on the first portions 210 of the adjacent fins is poor, and the formation quality of the isolation film is affected. Subsequently removing the isolation film higher than the top of the first part 210 of the fin part to form an isolation layer, wherein the isolation layer is processed in the subsequent gate oxide layer forming processThe sidewalls of the fin 200 are stressed by the process environment, and if the sum of the thicknesses of the first liner layer 320 and the second liner layer 500 is too small, the first liner layer 320 and the second liner layer 500 have a poor buffering effect, so that it is difficult to effectively reduce the stress applied to the sidewalls of the fin 200 by the isolation layer 620. In this embodiment, the sum of the thickness of the first liner layer 320 and the thickness of the second liner layer 500 is
In this embodiment, the material of the second liner layer 500 is amorphous silicon. In other embodiments, the material of the second liner layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or polysilicon.
Referring to fig. 11, an isolation film 610 covering the second liner layer 500 is formed on the substrate 100, and the top of the isolation film 610 is higher than the top of the fin 200 or is flush with the top of the fin 200.
The process steps for forming the isolation film 610 include: forming an initial isolation film (not shown) on the substrate 100 covering the second liner layer 500 with a top higher than a top of the second liner layer on top of the fin second portion 220; the initial isolation film is planarized to form the isolation film 610.
In this embodiment, the isolation film 610 is made of silicon oxynitride. In other embodiments, the material of the initial isolation film may also be silicon nitride or silicon oxide.
Before the isolation film 610 is formed, the sidewall of the first fin portion 210 is covered with a first liner layer 320, and the surface of the first liner layer 320, the top of the second fin portion 220 and the sidewall are covered with a second liner layer 500, so that the distance between the second liner layers 500 on the sidewalls of the first fin portions 210 adjacent to each other is narrow, and the distance between the second liner layers 500 on the sidewalls of the second fin portions 220 adjacent to each other is wide, so that the process window for forming the isolation film 610 is large; a large process window is advantageous to improve the quality of the formation of the isolation film 610.
In this embodiment, the process for forming the initial isolation film includes a fluid chemical vapor deposition process. The process parameters of the fluid chemical vapor deposition process comprise: the temperature is 30 ℃ to 190 ℃, the pressure is 0.01Torr to 10Torr, and the process gas comprises N (SIH)3)3、NH3And O2The gas flow of the process gas is 20sccm to 10000 sccm.
In other embodiments, the formation process of the initial isolation film may further include a high aspect ratio chemical vapor deposition process.
In this embodiment, the material of the second liner layer 500 is amorphous silicon, and in the process of forming the initial isolation film, the introduced oxygen and water vapor easily oxidize the material of the second liner layer 500, so that the material of the second liner layer 500 is converted into silicon oxide.
Since the sidewall of the first fin portion 210 is covered with the first liner layer 320, and the surface of the first liner layer 320, the top of the second fin portion 220 and the sidewall are covered with the second liner layer 500, the first liner layer 320 and the second liner layer 500 can prevent the introduced oxygen and water vapor from oxidizing the surface of the fin portion 200 during the formation of the initial isolation film, thereby preventing the width of the fin portion 200 from narrowing. If the fin portion is exposed in the process environment of the fluid chemical vapor deposition process, oxygen and water vapor in the process environment are prone to oxidize the surface of the fin portion, and the width of the fin portion is narrowed.
In this embodiment, the top of the isolation film 610 is higher than the surface of the second liner layer 500 on top of the fin second portion 220.
In other embodiments, the top of the isolation film may also be flush with the top of the second liner layer on top of the second portion of the fin.
In addition, in other embodiments, in the step of planarizing the initial isolation film, the second liner layer on the top of the second portion of the fin may be removed, so that the top of the isolation film is flush with the top of the fin.
Referring to fig. 12, the second liner layer 500 and the isolation film 610 (refer to fig. 11) above the top of the first portion 210 of the fin portion are removed, and the isolation film 610 is left to form an isolation layer 620.
In this embodiment, the top of the isolation layer 620 is flush with the top of the first portion 210 of the fin portion, and the isolation layer 620 exposes the top and the sidewall of the second portion 220 of the fin portion, thereby providing a spatial location for the subsequent formation of a gate oxide layer.
In this embodiment, the second liner layer 500 and the isolation film 610 higher than the top of the first portion 210 of the fin portion are removed by a dry etching process. The technological parameters of the dry etching process comprise: the etching gas comprises CH4And CHF3In which CH4The gas flow rate of the gas is 8sccm to 500sccm, CHF3The gas flow is 30sccm to 200sccm, the chamber pressure is 10mTorr to 2000mTorr, the radio frequency power is 100W to 1300W, the direct current self-bias voltage is 80V to 500V, and the etching gas is introduced for 4s to 500 s.
And forming a gate oxide layer on the top and the surface of the side wall of the fin portion 200 exposed by the isolation layer 620, wherein the isolation layer 620 applies stress to the side wall of the fin portion 200 under the influence of a process environment in the process of forming the gate oxide layer. If the thickness of the isolation layer 620 is too large, correspondingly, the volumes of the isolation layers 620 on the two sides of the fin portion 200 are too large, so that the stress applied by the isolation layers 620 to the side walls of the first portion 210 of the fin portion is too large in the process of forming the gate oxide layer; if the thickness of the isolation layer 620 is too small, the isolation layer has poor insulating properties. In this embodiment, the thickness of the isolation layer 620 is equal to the height of the first portion 210 of the fin portion, i.e.
In this embodiment, the widths of the isolation layers 620 on two sides of a part of the fin portion 200 are equal, and the widths of the isolation layers 620 on two sides of the rest of the fin portion 200 are not equal. Specifically, the widths of the isolation layers 620 on the two sides of the fin portion 200 in the central region ii are equal; the widths of the isolation layers 620 on the two sides of the fin portion 200 in the edge region i are not equal.
In other embodiments, the widths of the isolation layers on both sides of each fin are different.
Referring to fig. 13, a gate oxide layer 700 is formed on the top and sidewall surfaces of the fin 200 exposed by the isolation layer 620.
In this embodiment, the gate oxide layer 700 is formed on the top and sidewall surfaces of the fin second portion 220.
In this embodiment, the gate oxide layer 700 is made of silicon oxide.
In this embodiment, the gate oxide layer 700 is formed by a thermal oxidation process. In other embodiments, the gate oxide layer may also be formed using a chemical oxidation method or an atomic layer deposition method.
In this embodiment, the isolation layer 620 has a structure that changes due to the high temperature environment of the thermal oxidation process, and applies stress to the sidewalls of the fin portion 200. If the temperature of the thermal oxidation process is too high, the stress applied by the isolation layer 620 to the sidewall of the fin portion 200 will be too large; if the temperature of the thermal oxidation process is too low, the formation quality of the gate oxide layer 700 is affected. In this embodiment, the temperature of the thermal oxidation process is 800-1050 ℃.
In this embodiment, the widths of the isolation layers 620 on the two sides of the fin portion 200 in the edge region i are not equal, that is, the volumes of the isolation layers 620 on the two sides of the fin portion 200 in the edge region i are not equal, so that the stress of the isolation layers 620 on the sidewalls of the fin portion 200 in the edge region i is not equal.
The first liner layer 320 and the second liner layer 500 are arranged between the isolation layer 620 and the side wall of the first portion 210 of the fin portion, so that the first liner layer 320 and the second liner layer 500 have a buffer effect on the stress applied to the side wall of the first portion 210 of the fin portion by the isolation layer 620, the thickness sum of the first liner layer 320 and the second liner layer 500 is large, the buffer effect of the first liner layer 320 and the second liner layer 500 is favorably improved, the stress effect on the side wall of the first portion 210 of the fin portion is reduced according to a certain proportion, the stress difference on the side walls of two sides of the fin portion 200 in the edge area I is reduced, and the fin portion 200 in the edge area I is prevented from being bent.
In summary, a first liner layer 320 is formed on the sidewalls of the first portion 210 of the fin; forming a second liner layer 500 on the surface of the first liner layer 320, on the top and sidewalls of the fin second portion 220; forming an isolation film 610 covering the second liner layer 500 on the substrate 100, wherein the distance between the second liner layers 500 on the sidewalls of the second portions 220 of adjacent fins is larger, so as to ensure that a process window of the isolation film 610 is larger, thereby improving the formation quality of the isolation film 610; the first liner layer 320 and the second liner layer 500 can protect the surface of the fin 200, and prevent the surface of the fin 200 from being oxidized during the formation of the isolation film 610. After the isolation film 610 is formed, the second liner layer 500 and the isolation film 610 higher than the top of the first portion 210 of the fin portion are removed, the isolation film 610 is remained to form an isolation layer 620, then a gate oxide layer 700 is formed on the top and the surface of the sidewall of the fin portion 200 exposed by the isolation layer 620, stress is applied to the sidewall of the fin portion 200 by the isolation layer 620 in the process of forming the gate oxide layer 700, a first liner layer 320 and a second liner layer 500 are arranged between the isolation layer 620 and the sidewall of the first portion 210 of the fin portion, the sum of the thicknesses of the first liner layer 320 and the second liner layer 500 is large, so that the buffer effect is good, the stress applied to the sidewall of the fin portion 200 by the isolation layer 620 can be effectively weakened, the fin portion 200 is prevented from being bent, and the performance of the semiconductor structure is improved.
In other embodiments, in the step of forming the isolation layer, the first liner layer, the second liner layer, and the isolation film on the sidewall of the first portion of the fin are also removed. Next, the step of forming the isolation layer will be described in detail with reference to fig. 14 and 15. The steps before forming the isolation layer can refer to the previous embodiment, and are not described again.
Referring to fig. 14, the second liner layer 500 and the isolation film 610 higher than the top of the first portion 210 of the fin are removed, the first liner layer 320, the second liner layer 500 and the isolation film 610 on the sidewall of the first portion 210 of the fin are also removed (refer to fig. 11), an isolation layer 620 is formed on the remaining isolation film 610, and the isolation layer 620 exposes the sidewall of the second portion 220 of the fin and the sidewall of the first portion 210 of the fin.
In this embodiment, the fin portions 200 are arranged on the substrate 100 at equal intervals, so that the widths of the isolation layers 620 on the two sides of the fin portion 200 in the central region ii are equal; in addition, since N1 ≠ N2 (refer to fig. 6), the widths of the isolation layers 620 at the two sides of the fin portion 200 in the edge region i are not equal.
If the removed thickness of the isolation film 610 is too large, correspondingly, the thickness of the isolation layer 620 is too small, resulting in poor insulation performance of the isolation layer 620. In this embodiment, the thickness of the isolation film 610 on the sidewalls of the first portion 210 of the fin portion is removed
Referring to fig. 15, a gate oxide layer 700 is formed on the top and sidewall surfaces of the fin 200 exposed by the isolation layer 620.
In this embodiment, the gate oxide layer 700 is formed on the sidewalls of the first fin portion 210, the top of the second fin portion 220, and the sidewalls.
In this embodiment, the gate oxide layer 700 is formed by a thermal oxidation process. In other embodiments, the gate oxide layer may also be formed using a chemical oxidation method or an atomic layer deposition method.
In the process of forming the gate oxide layer 700, the isolation layer 620 exerts stress on the sidewalls of the fin portion 200 under the influence of the process environment, and since the widths of the isolation layers 620 on the two sides of the fin portion 200 in the edge region i are not equal, that is, the volumes of the isolation layers 620 are not equal, the magnitudes of the stresses exerted by the isolation layers 620 on the sidewalls of the two sides of the fin portion 200 in the edge region i are not equal.
The first liner layer 320 and the second liner layer 500 are arranged between the isolation layer 620 and the partial side wall of the first portion 210 of the fin portion, and the sum of the thicknesses of the first liner layer 320 and the second liner layer 500 is large, so that the buffering effect of the stress applied to the side wall of the fin portion 200 by the isolation layer 620 by the first liner layer 320 and the second liner layer 500 is good, the stress applied to the side wall of the fin portion 200 by the isolation layer 620 can be effectively weakened, the stress difference applied to the side walls at two sides of the fin portion 200 in the edge area I is further reduced, the fin portion 200 in the edge area I is prevented from being bent, and the performance of a semiconductor structure is improved.
Referring to fig. 13, the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure including: the semiconductor device comprises a substrate 100 and a fin portion 200 protruding from the substrate 100, wherein the fin portion 200 comprises a fin portion first portion 210 located on the surface of the substrate 100 and a fin portion second portion 220 located on the top of the fin portion first portion 210; a first liner layer 320 on sidewalls of the fin first portion 210; a second liner layer 500 on a surface of the first liner layer 320, the first liner layer 320 being between the fin first portion 210 and the second liner layer 500; an isolation layer 620 on the substrate 100 and covering a surface of the second pad layer 500, and a top of the isolation layer 620 is flush with a top of the second pad layer 500; and the gate oxide layer 700 is positioned on the top and the side wall surface of the fin portion 200 exposed by the isolation layer 620.
In this embodiment, the substrate 100 includes edge regions i and a central region ii located between the adjacent edge regions i, the substrate 100 has a plurality of fins 200, the widths of the isolation layers 620 on two sides of the fin 200 in the central region ii are equal, and the widths of the isolation layers 620 on two sides of the fin 200 in the edge region i are not equal.
In this embodiment, the isolation layer 620 exerts a stress effect on the sidewall of the first fin portion 210 under the influence of the process environment for forming the gate oxide layer 700, and the first liner layer 320 and the second liner layer 500 are located between the isolation layer 620 and the sidewall of the first fin portion 210, so that the stress exerted by the isolation layer 620 on the first fin portion 210 can be relieved.
If the sum of the thickness of the first liner layer 320 and the thickness of the second liner layer 500 is too small, the first liner layer 320 and the second liner layer 500 have poor buffering effect, and it is difficult to effectively reduce the stress applied by the isolation layer 620 to the sidewall of the first portion 210 of the fin portionSmall; if the sum of the thicknesses of the first liner layer 320 and the second liner layer 500 is too large, the distance between the second liner layers 500 on the sidewalls of the first portions 210 of adjacent fins is too narrow, resulting in poor formation quality of the isolation layer 620. In this embodiment, the sum of the thickness of the first liner layer 320 and the thickness of the second liner layer 500 is
If the ratio of the height of the first fin portion 210 to the height of the second fin portion 220 is too large, the volumes of the isolation layers on the two sides of the first fin portion 210 are too large, so that the stress difference applied by the isolation layer 620 on the sidewalls of the fin portion 200 in the edge region i is too large in the process of forming the gate oxide layer 700. If the ratio of the height of the first portion of fins 210 to the height of the second portion of fins 220 is too small, the thickness of the isolation layer 620 is too small, resulting in poor insulating properties of the isolation layer 620. In the present embodiment, a ratio of the height of the first portion 210 of the fin to the height of the second portion 220 of the fin is 0.5-1.
In other embodiments, the fin portion in the partial central region has equal spacing to adjacent fin portions on two sides, and the fin portion in the partial central region has unequal spacing to adjacent fin portions on two sides.
In addition, in other embodiments, the widths of the isolation layers on both sides of each fin portion may be different.
In summary, the sum of the thicknesses of the first liner layer 320 and the second liner layer 500 is large, the buffer effect is good, and the stress applied by the isolation layer 620 to the sidewalls of the fin 200 can be effectively reduced, so that the fin 200 in the edge region i can be prevented from being bent, and the performance of the semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method for forming a semiconductor structure, comprising:
providing a substrate and a fin portion protruding out of the substrate, wherein the fin portion comprises a first fin portion located on the surface of the substrate and a second fin portion located on the top of the first fin portion;
forming a first liner layer on the side wall of the first part of the fin part;
forming a second liner layer on the surface of the first liner layer, the top of the second part of the fin part and the side wall; forming an isolation film covering the second liner layer on the substrate, wherein the top of the isolation film is higher than the top of the fin portion or is flush with the top of the fin portion;
removing the second liner layer and the isolation film which are higher than the top of the first part of the fin part, and forming an isolation layer by the residual isolation film;
forming a gate oxide layer on the top of the fin part and the surface of the side wall, which are exposed out of the isolation layer;
the process step of forming the first liner layer comprises: forming a first liner film on the side wall of the first part of the fin part, the top of the second part of the fin part and the side wall; forming an anti-reflection coating on the substrate, wherein the top of the anti-reflection coating is flush with the top of the first part of the fin; removing the first liner film on the top and the side wall of the second part of the fin part, and forming a first liner layer by the remaining first liner film; and removing the anti-reflection coating.
2. The method of claim 1, wherein the isolation layer widths on both sides of the fin are not equal prior to forming the gate oxide layer.
3. The method for forming a semiconductor structure of claim 1, wherein the number of the fins is multiple, and before the gate oxide layer is formed, the widths of the isolation layers on two sides of part of the fins are equal, and the widths of the isolation layers on two sides of the rest of the fins are not equal.
4. The method of forming a semiconductor structure of claim 3, wherein the substrate includes edge regions and a central region between adjacent edge regions; the widths of the isolation layers on the two sides of the fin portion in the central area are equal, and the widths of the isolation layers on the two sides of the fin portion in the edge area are unequal.
5. The method of claim 1, wherein a top of the isolation layer is flush with a top of the first portion of the fin; and in the step of forming the gate oxide layer, forming the gate oxide layer on the top and the side wall of the second part of the fin part exposed out of the isolation layer.
6. The method of claim 1, wherein a top of the isolation layer is lower than a top of the first portion of the fin; in the process step of forming the isolation layer, the first liner layer, the second liner layer and the isolation film on the sidewall of the first part of the fin portion are also removed, and the sidewall of the first part of the fin portion is exposed; and in the step of forming the gate oxide layer, forming the gate oxide layer on the side wall of the first part of the fin part, the top of the second part of the fin part and the side wall which are exposed out of the isolation layer.
7. The method of claim 6, wherein said removing said isolation film on said sidewalls of said first portion of said fin is performed to a thickness of
8. The method of forming a semiconductor structure of claim 1, wherein the process step of forming the isolation film comprises: forming an initial isolation film covering the second liner layer on the substrate, wherein the top of the initial isolation film is higher than the top of the second liner layer on the top of the second part of the fin portion; and carrying out planarization treatment on the initial isolation film to form the isolation film.
9. The method of claim 8, wherein a top of said isolation film is higher than a top of a second liner layer on top of a second portion of the fin; or the top of the isolation film is flush with the top of the second liner layer on the second top of the fin portion.
10. The method of claim 8, wherein the initial isolation film forming process comprises a fluid chemical vapor deposition process or a high aspect ratio chemical vapor deposition process.
11. The method of claim 1, wherein a sum of the thickness of the first liner layer and the thickness of the second liner layer is
12. The method of claim 1 or 11, wherein a ratio of the thickness of the first liner layer to the thickness of the second liner layer is 0.5 to 1.
13. The method of claim 1, wherein a ratio of a height of the first portion of the fin to a height of the second portion of the fin is between 0.5 and 1.25.
14. The method of forming a semiconductor structure of claim 1, wherein said gate oxide layer is formed using a thermal oxidation process.
15. The method of claim 14, wherein the thermal oxidation process is performed at a temperature of 800 ℃ to 1050 ℃.
16. The method for forming a semiconductor structure according to claim 1, wherein a material of the first liner layer is silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride; the second liner layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, amorphous silicon or polysilicon.
17. A semiconductor structure formed by the method of forming a semiconductor structure of any one of claims 1to 16, comprising:
the fin part comprises a first fin part positioned on the surface of the substrate and a second fin part positioned on the top of the first fin part;
a first liner layer on sidewalls of a first portion of the fin;
a second liner layer on a surface of the first liner layer, the first liner layer being located between the first portion of the fin and the second liner layer;
the isolation layer is positioned on the substrate and covers the surface of the second liner layer, and the top of the isolation layer is flush with the top of the second liner layer;
and the gate oxide layer is positioned on the top of the fin part and the surface of the side wall, which are exposed out of the isolation layer.
18. The semiconductor structure of claim 17, wherein the substrate comprises edge regions and a central region between adjacent edge regions, the substrate having a plurality of fins thereon, the spacers on both sides of the fins in the central region having equal widths, the spacers on both sides of the fins in the edge regions having unequal widths.
19. The semiconductor structure of claim 17, wherein the sum of the thickness of the first liner layer and the thickness of the second liner layer is
The ratio of the height of the first part of the fin to the height of the second part of the fin is 0.5-1.25.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711241953.7A CN109860291B (en) | 2017-11-30 | 2017-11-30 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711241953.7A CN109860291B (en) | 2017-11-30 | 2017-11-30 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109860291A CN109860291A (en) | 2019-06-07 |
| CN109860291B true CN109860291B (en) | 2021-11-12 |
Family
ID=66888656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711241953.7A Active CN109860291B (en) | 2017-11-30 | 2017-11-30 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109860291B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151360B (en) * | 2019-06-28 | 2023-07-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11568121B2 (en) | 2020-06-19 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET semiconductor device grouping |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140367795A1 (en) * | 2013-06-12 | 2014-12-18 | International Business Machines Corporation | Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices |
| CN105336609A (en) * | 2014-06-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Fin FET device and manufacturing method thereof, and electronic device |
| CN105448984A (en) * | 2014-08-06 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | FinFET and preparation method thereof |
| CN107026126A (en) * | 2016-02-02 | 2017-08-08 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
-
2017
- 2017-11-30 CN CN201711241953.7A patent/CN109860291B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140367795A1 (en) * | 2013-06-12 | 2014-12-18 | International Business Machines Corporation | Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices |
| CN105336609A (en) * | 2014-06-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Fin FET device and manufacturing method thereof, and electronic device |
| CN105448984A (en) * | 2014-08-06 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | FinFET and preparation method thereof |
| CN107026126A (en) * | 2016-02-02 | 2017-08-08 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109860291A (en) | 2019-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20210313468A1 (en) | Semiconductor device and manufacturing method thereof | |
| US10964542B2 (en) | Selective high-K formation in gate-last process | |
| US20080277745A1 (en) | Fin filled effect transistor and method of forming the same | |
| CN107591362B (en) | Semiconductor structure and forming method thereof | |
| KR101985594B1 (en) | Forming transistor by selectively growing gate spacer | |
| CN106206307A (en) | Semiconductor structure and forming method thereof | |
| CN109285875B (en) | Fin type transistor and forming method thereof | |
| CN103578988A (en) | Fin part and finned-type field-effect transistor and forming method thereof | |
| CN109860291B (en) | Semiconductor structure and forming method thereof | |
| CN112309978A (en) | Forming method of semiconductor structure and transistor | |
| US11488858B2 (en) | Methods for forming stacked layers and devices formed thereof | |
| US7989350B2 (en) | Method for fabricating semiconductor device with recess gate | |
| US20220384263A1 (en) | Methods for Forming Stacked Layers and Devices Formed Thereof | |
| CN110648915B (en) | Semiconductor device and method of forming the same | |
| CN111129142A (en) | Semiconductor device and method of forming the same | |
| CN107706111B (en) | Method for forming semiconductor device | |
| CN110911342A (en) | Shallow trench isolation structure and preparation method thereof | |
| CN115346920A (en) | Method for manufacturing an integrated circuit structure and integrated circuit structure | |
| CN109786254B (en) | Selective high-k formation in gate last process | |
| CN109300844B (en) | Fin type transistor and forming method thereof | |
| CN110349913B (en) | Semiconductor structure and forming method thereof | |
| CN113871351A (en) | Semiconductor structure and forming method thereof | |
| CN108962971B (en) | Semiconductor structure and forming method thereof | |
| JP2004235429A (en) | Method for manufacturing semiconductor device | |
| CN109994428B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |