CN109860291A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109860291A CN109860291A CN201711241953.7A CN201711241953A CN109860291A CN 109860291 A CN109860291 A CN 109860291A CN 201711241953 A CN201711241953 A CN 201711241953A CN 109860291 A CN109860291 A CN 109860291A
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Abstract
A kind of semiconductor structure and forming method thereof, forming method include: the fin for providing substrate and protruding from substrate, and fin includes the fin first part positioned at substrate surface and the fin second part at the top of fin first part；The first laying is formed on fin first part side wall；The second laying is formed at the top of the first laying surface, fin second part and on side wall；The isolation film of the second laying of covering is formed on the substrate, be higher than at the top of fin at the top of isolation film or is flushed with fin top；Removal is higher than the second laying and isolation film at the top of fin first part, and remaining isolation film forms separation layer；At the top of the fin that separation layer exposes and sidewall surfaces form gate oxide.In the present invention, the first laying and the second laying can effectively weaken the stress intensity that separation layer applies fin side wall, to avoid fin from bending, and the process window for forming separation layer is big, help to improve the formation quality of separation layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In semiconductor fabrication, as integrated circuit feature size persistently reduces, the channel length of MOSFET also it is corresponding not
It is disconnected to shorten.However, the distance between device source electrode and drain electrode also shorten therewith with the shortening of device channel length, lead to grid
It is extremely deteriorated to the control ability of channel, short-channel effect (SCE:short-channel effects) is easier to occur.
Fin formula field effect transistor (FinFET) has performance outstanding, the grid of FinFET in terms of inhibiting short-channel effect
Best can control fin from two sides less, thus compared with planar MOSFET, control of the grid of FinFET to channel
Ability is stronger, can be good at inhibiting short-channel effect.
But the performance of semiconductor structure is still to be improved in the prior art.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can weaken separation layer and formed
The stress intensity applied during gate oxide to fin side wall, so that fin be avoided to bend, and forms separation layer
Process window it is big, the formation quality of the separation layer is helped to improve, in addition it is possible to which the fin portion surface is avoided to be formed
It is oxidized during the separation layer.
To solve the above problems, the present invention provides a kind of method for forming semiconductor structure, comprising: provide substrate and protrude from
The fin of the substrate, the fin include pushing up positioned at the fin first part of substrate surface and positioned at the fin first part
The fin second part in portion；The first laying is formed on fin first part side wall；First laying surface,
The second laying is formed at the top of the fin second part and on side wall；It is formed over the substrate and covers second laying
Isolation film, be higher than at the top of the fin at the top of the isolation film or with flushed at the top of the fin；Removal is higher than the fin
The second laying and isolation film at the top of first part, remaining isolation film form separation layer；In the institute that the separation layer exposes
It states at the top of fin and sidewall surfaces forms gate oxide.
Optionally, before forming the gate oxide, the spacer width of the fin two sides is unequal.
Optionally, the quantity of the fin is multiple, before forming the gate oxide, the part fin two sides
The spacer width is equal, and the spacer width of remaining fin two sides is unequal.
Optionally, the substrate includes fringe region and the central area between adjacent edge region；In described
The spacer width of the fin two sides in heart district domain is equal, the isolation of the fin two sides of the fringe region
Slice width degree is unequal.
Optionally, it is flushed at the top of the separation layer with the fin first part top；Forming the gate oxide
In step, the gate oxide is formed at the top of the fin second part that the separation layer exposes and on side wall.
Optionally, at the top of at the top of the separation layer lower than the fin first part；In the technique for forming the separation layer
In step, the first laying, the second laying and the isolation film in fin first part partial sidewall are also removed, is exposed
Fin first part partial sidewall；In the step of forming the gate oxide, in the fin that the separation layer exposes
The gate oxide is formed at the top of a part of side wall, fin second part and on side wall.
Optionally, remove the isolation film in fin first part partial sidewall with a thickness of
Optionally, the processing step for forming the isolation film includes: to form covering second liner over the substrate
The initial isolation film of layer, and it is higher than the second laying top being located at the top of fin second part at the top of the initial isolation film
Portion；Planarization process is carried out to the initial isolation film, forms the isolation film.
Optionally, the top of the isolation film is higher than at the top of the second laying being located at the top of fin second part；Or
It is flushed at the top of person, the isolation film top and the second laying being located on the second top of fin.
Optionally, the formation process of the initial isolation film includes fluid chemistry gas-phase deposition or high-aspect-ratio chemistry
Gas-phase deposition.
Optionally, the summation of the first laying thickness and the second laying thickness is
Optionally, the ratio of the first laying thickness and the second laying thickness is 0.5~1.
Optionally, the ratio of fin first part height and the fin second part height is 0.5~1.25.
Optionally, the gate oxide is formed using thermal oxidation processes.
Optionally, the temperature of the thermal oxidation processes is 800 DEG C~1050 DEG C.
Optionally, the processing step for forming first laying includes: in fin first part side wall, the fin
The first liner membrane is formed at the top of portion's second part and on side wall；Anti-reflection coating, the anti-reflective coating are formed over the substrate
It is flushed at the top of layer top and the fin first part；Removal is located at described the at the top of the fin second part and on side wall
One liner membrane, remaining first liner membrane form the first laying；Remove the anti-reflection coating.
Optionally, the material of first laying is silica, silicon nitride, silicon oxynitride or carbon silicon oxynitride；It is described
The material of second laying is silica, silicon nitride, silicon oxynitride, carbon silicon oxynitride, amorphous silicon or polysilicon.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate and the fin for protruding from the substrate, institute
Stating fin includes the fin first part positioned at substrate surface and the fin second part at the top of the fin first part；
The first laying on fin first part side wall；Positioned at the second laying of first laying surface, and
First laying is between the fin first part and second laying；On the substrate and cover institute
The separation layer of the second laying surface is stated, and is flushed at the top of the separation layer at the top of second laying；Positioned at it is described every
The gate oxide at fin top and sidewall surfaces that absciss layer exposes.
Optionally, the substrate includes fringe region and the central area between adjacent edge region, the lining
There are multiple fins, the spacer width of the fin two sides of the central area is equal, the fringe region on bottom
The fin two sides the spacer width it is unequal.
Optionally, the summation of the first laying thickness and the second laying thickness isThe fin
The ratio of first part's height and the fin second part height is 0.5~1.25.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of semiconductor structure provided by the invention, on fin first part side wall
Form the first laying；The second liner is formed at the top of first laying surface, the fin second part and on side wall
Layer；The isolation film for covering second laying is formed over the substrate.Compared to the second of first laying surface
Laying, the spacing between the second laying on the adjacent fin second part side wall is larger, therefore forms the isolation
The process window of film is larger；Biggish process window helps to improve the formation quality of the isolation film.And due to it is described every
From the first laying and the second laying is formed between film and the fin portion surface, so first laying and described
Two layings can play the role of the protection fin portion surface, can prevent fin portion surface quilt during forming isolation film
Oxidation.After forming the isolation film, removal is higher than the second laying and isolation film at the top of the fin first part, remaining
Isolation film formed separation layer, then the separation layer expose the fin at the top of and sidewall surfaces formed gate oxide.By
In the process environments for forming the gate oxide separation layer internal structure is changed, therefore is forming the gate oxide
During the separation layer stress, the separation layer and the fin first are applied to fin first part side wall
The first laying and the second laying are formed between partial sidewall, first laying and the second laying can play certain
Buffer function, first laying and the second laying thickness summation are big, are conducive to improve first laying and second
The buffering effect of laying avoids described to effectively weaken the stress intensity that separation layer applies fin first part side wall
Fin bends, and improves the performance of semiconductor structure.
In optinal plan, the ratio of fin first part height and the fin second part height is 0.5~
1.25, fin first part height and the ratio of the fin second part height are appropriate, on the one hand, guarantee the isolation
The volume adequacy of layer, helps to reduce the stress intensity that the separation layer applies the fin；On the other hand, make the isolation
The thickness meet demand of layer, to guarantee the insulation effect of the separation layer.
In optinal plan, the summation of the first laying thickness and the second laying thickness isIt is described
The summation of first laying thickness and the second laying thickness is appropriate, on the one hand, guarantees the first laying thickness and second
Laying has good buffering effect, can effectively weaken the stress that the separation layer applies fin side wall；It is another
Aspect keeps the depth-to-width ratio in region between the second laying in the adjacent fin first part suitable, helps to improve isolation
The filling capacity of film improves the formation quality of isolation film.
In optinal plan, the temperature of the thermal oxidation processes is 800 DEG C~1050 DEG C, the thermal oxidation processes
Technological temperature it is appropriate, on the one hand help to ensure that the formation quality of the gate oxide；On the other hand facilitate described in reduction
The stress intensity that separation layer applies the fin side wall.
Detailed description of the invention
Fig. 1 to Fig. 5 is the corresponding structural schematic diagram of each step in a kind of forming method of semiconductor structure；
Fig. 6 to Figure 15 is the corresponding structural schematic diagram of each step in one embodiment of method for forming semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that the performance of existing semiconductor structure is still to be improved.
It is analyzed now in conjunction with a kind of forming method of semiconductor structure, Fig. 1 to Fig. 5 is a kind of formation of semiconductor structure
The corresponding structural schematic diagram of each step, the processing step for forming semiconductor structure specifically include that in method
With reference to Fig. 1, substrate 10 is provided and protrudes from the fin 20 of the substrate 10.
The substrate 10 includes the fringe region i and central area ii between the i of adjacent edge region.
The quantity of the fin 20 is multiple, multiple fins 20 spacing arrangements such as on the substrate 10.The side
The fin 20 of edge region i and 10 side wall of substrate distance are first distance M1, the fin 20 of the fringe region i
With at a distance from adjacent fin 20 be second distance M2, M1 ≠ M2.
With reference to Fig. 2, laying 32 is formed on 20 top of fin and side wall, and described in the laying 32 also covers
10 top of substrate.
With reference to Fig. 3, the isolation film 61 for covering the laying 32,61 top of isolation film are formed on the substrate 10
Higher than 32 surface of the laying for being located at 20 top of fin.
With reference to Fig. 4, removes the isolation film 61 (with reference to Fig. 3) of segment thickness and be located at 20 top of fin and part side
Laying 32 on wall, the remaining isolation film 61 form separation layer 62, push up at the top of the separation layer 62 lower than the fin 20
Portion, and flushed at the top of 62 top of the separation layer and the remaining laying 32.
With reference to Fig. 5, using thermal oxidation processes in 20 top of the fin that the separation layer 62 exposes and side wall table
Face forms gate oxide 70.
The performance for the semiconductor structure that the above method is formed is poor, analyzes its reason and is:
It is formed in the processing step of the gate oxide 70, the separation layer 62 will receive to form the gate oxide 70
The influence of process environments, for example, in process environments temperature influence so that 62 internal structure of the separation layer change to
Stress applied to 20 side wall of fin, and the size of stress that applies to the fin 20 of the separation layer 62 and the separation layer 62
Volume it is related.Since 62 volume of separation layer of M1 ≠ M2, thus 20 two sides of fin of fringe region i differ, lead to marginal zone
The stress intensity that the separation layer 62 that the 20 two sides side wall of fin of domain i is subject to applies is unequal.
When forming the gate oxide 70 using thermal oxidation processes, due to the technique of the thermal oxidation processes
Temperature is high, and under high temperature environment, the stress that the separation layer 62 applies 20 side wall of fin is bigger, be easy to cause marginal zone
The stress intensity serious unbalance that the 20 two sides side wall of fin of domain i is subject to, in turn result in fringe region i the fin 20 occur it is curved
It is bent.
It is formed with the laying 32 between 20 side wall of 62 side wall of separation layer and the fin, for the fin 20
The stress that the separation layer 62 that side wall is subject to applies, the laying 32 have certain buffer function.32 thickness of laying is got over
Greatly, then buffering effect is better.Although but separation layer 62 can be weakened to fin using the method for increasing by 32 thickness of laying
20 apply stress intensities, but will lead to be formed the isolation film 61 process window it is small so that the isolation film 61 fill
The ability in region is poor between laying 32 on adjacent 20 side wall of fin, and it is of poor quality to cause to be formed by isolation film 61, Jin Erzao
Formation at separation layer 62 is of poor quality.
For this purpose, the present invention provides a kind of method for forming semiconductor structure, comprising: fin includes the fin positioned at substrate surface
First part and the fin second part at the top of the fin first part；It is formed on fin first part side wall
First laying；The second laying is formed at the top of first laying surface, the fin second part and on side wall；?
The isolation film for covering second laying is formed on the substrate, be higher than at the top of the fin at the top of the isolation film or with institute
It states and is flushed at the top of fin；Removal is higher than the second laying and isolation film at the top of the fin first part, remaining isolation film
Form separation layer；At the top of the fin that the separation layer exposes and sidewall surfaces form gate oxide.
The separation layer is influenced to apply stress to the fin side wall by process environments during forming gate oxide,
First laying and second laying are between the separation layer and the fin side wall, and first liner
Layer and the second laying thickness summation are big, therefore first laying and second laying are applied to separation layer
The buffering effect of stress on fin side wall is good, can effectively weaken the stress that the separation layer applies the fin side wall
Size improves the performance of semiconductor structure so that the fin be avoided to bend.In addition, being compared before forming the isolation film
Spacing between the second laying on the second laying on the first laying, the adjacent fin second part side wall compared with
Greatly, that is to say, that the process window for forming the isolation film is larger, and biggish process window helps to improve the isolation film
Form quality.In addition, before forming the isolation film, first laying and second laying on the fin can be with
Play the role of the protection fin portion surface, fin portion surface can be prevented to be oxidized during forming isolation film.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 6 to Figure 15 is the corresponding section of each step that the semiconductor structure that one embodiment of the invention provides forms process
Structural schematic diagram.
With reference to Fig. 6, substrate 100 is provided and protrudes from the fin 200 of the substrate 100, the fin 200 includes being located at lining
The fin first part 210 on 100 surface of bottom and the fin second part 220 at the top of the fin first part 210.
In the present embodiment, the substrate 100 includes fringe region I and the center between adjacent edge region I
Domain II.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be the silicon substrate on insulator, the germanium on insulator
Substrate or glass substrate.
In the present embodiment, the quantity of the fin 200 be it is multiple, between multiple fins 200 are equal on the substrate 100
Away from arrangement.The spacing of the fin 200 of the central area II fin 200 adjacent with two sides is equal；The fringe region I
200 side of fin adjacent to 100 side wall of substrate, the other side adjacent to central area II fin 200, the fringe region I
Fin 200 between 100 side wall of substrate at a distance from be N1, the fin 200 of the fringe region I is at a distance from adjacent fin 200
N2, N1 ≠ N2.
It is subsequent to form the first laying on 210 side wall of fin first part, in the present embodiment, the fin first
Part 210 is used to define the position of first laying.
It is subsequent to form the second liner on first laying surface, 220 top of the fin second part and side wall
Layer；The isolation film for covering second laying is formed on the substrate 100.Due to 210 side wall of fin first part
On be formed with the first laying and the second laying, wherein first laying is located at 210 side wall of fin first part
It is adjacent described between second laying, therefore compared to the second laying on 220 side wall of fin second part
The spacing of the second laying on 210 side wall of fin first part is smaller.
If 210 height of fin first part is excessive, make the second laying on adjacent 210 side wall of fin first part
Between region depth-to-width ratio it is excessively high, the filling capacity that will lead to the isolation film to be formed is poor, influences the formation quality of the isolation film.
If 210 height of fin first part is too small, subsequent removal is higher than the isolation film at 210 top of fin first part, shape
At separation layer, then make the thickness of the separation layer too small, causes the insulating property (properties) of the separation layer poor.In the present embodiment, institute
Stating 210 height of fin first part is
Subsequent removal is higher than the isolation film at 210 top of fin first part, forms separation layer；Then in the isolation
At the top of the fin that layer exposes and sidewall surfaces form gate oxide.If 210 height of fin first part and the fin
The ratio of two parts, 220 height is excessive, then the thickness of the separation layer formed is excessive, and then the institute of 200 two sides of the fin
The volume for stating separation layer is excessive, so that the separation layer will be caused to the fin during forming the gate oxide
The stress that 210 side wall of first part applies is excessive.If 210 height of fin first part and the fin second part 220
The ratio of height is too small, then the thickness for the separation layer being subsequently formed is too small, causes the separation layer insulating property (properties) poor.This reality
It applies in example, the ratio of 210 height of fin first part and 220 height of fin second part is 0.5~1.25.
In the present embodiment, the material of the fin 200 is silicon, i.e., the described fin first part 210 and fin second part
220 material is silicon.In other embodiments, the material of the fin can also be germanium, SiGe, silicon carbide, GaAs or
Gallium indium.
In other embodiments, the spacing of the fin of portion central region fin adjacent with two sides is equal, remaining part
The spacing of the fin in branch center region fin adjacent with two sides is unequal.
In addition, in other embodiments, the quantity of the fin can also be one, and fin two sides side wall and neighbour
The distance of the close substrate side wall is unequal.
It is subsequent to form the first laying on 210 side wall of fin first part, below with reference to Fig. 7 to Fig. 9, to described
The forming step of first laying is described in detail.
With reference to Fig. 7, formed on 210 side wall of fin first part, 220 top of the fin second part and side wall
First liner membrane 310.
In the present embodiment, first liner membrane 310 also covers 100 surface of the substrate that the fin 200 exposes.
In the present embodiment, the material of first liner membrane 310 is silica.In other embodiments, first lining
The material of pad film can also be silicon nitride, silicon oxynitride or carbon silicon oxynitride.
First liner membrane 310 on subsequent 220 top of removal fin second part and side wall, forms the first liner
Layer, and the second laying is formed on the first laying surface, 220 top of fin second part and side wall.If first lining
The thickness of pad film 310 is too small, then the first laying thickness is too small, and the second laying thickness will be caused excessive, adjacent
The second laying interval too small on 220 side wall of fin second part, so that the process window for being subsequently formed isolation film is too small, shadow
Ring the formation quality of the isolation film.If the thickness of first liner membrane 310 is excessive, the second laying thickness will be caused
It is too small, thus second laying is poor to the protecting effect at 220 top of fin second part and side wall, causes the fin
Second part 220 surface in portion's is oxidized easily during being subsequently formed the isolation film.In the present embodiment, first lining
Pad film 310 with a thickness of
With reference to Fig. 8, form anti-reflection coating 400 on the substrate 100,400 top of anti-reflection coating with it is described
It is flushed at the top of fin first part 210.
In the present embodiment, the material of the anti-reflection coating 400 includes siliceous oxycarbide.
Subsequent removal is located at first liner membrane 310 on 220 top of fin second part and side wall, the antireflection
Coating 400 plays the role of protecting the first liner membrane 310 on 210 side wall of fin first part.
The processing step for forming the anti-reflection coating 400 includes: that covering first lining is formed on the substrate 100
The antireflection film of pad film 310, and it is higher than the first liner for being located at 220 top of fin second part at the top of the antireflection film
310 surface of film is flushed with 310 surface of the first liner membrane；Etching removal is higher than 210 top of fin first part
The antireflection film forms anti-reflection coating 400.
With reference to Fig. 9, removal is located at the (ginseng of first liner membrane 310 on 220 top of fin second part and side wall
Examine Fig. 8), remaining first liner membrane 310 forms the first laying 320.
In the present embodiment, it is located on 220 top of fin second part and side wall using dry etch process removal
First liner membrane 310.The technological parameter of the dry etch process includes: that etching gas includes He, NH3And NF3, wherein
The gas flow of He is 600sccm to 2000sccm, NH3Gas flow be 200sccm to 500sccm, NF3Gas flow
For 20sccm to 200sccm, chamber pressure is 2Torr to 10Torr, and etching gas is passed through the time as 20s to 100s.
In the present embodiment, the material of the fin second part 220 is silicon, and the material of first liner membrane 310 is oxygen
SiClx；The dry etch process is high to the etching selection ratio of first liner membrane 310 and the fin second part 220,
To avoid causing to etch to 220 surface of fin second part during removing the first liner membrane 310.
It is subsequent to form the second laying on 320 surface of the first laying, 220 top of fin second part and side wall, and
The isolation film for covering second laying is formed on the substrate 100.If 320 thickness of the first laying is too small, phase
It answers, the second laying thickness is then excessive, will cause the second laying interval on adjacent 220 side wall of fin second part
It is too small, so that the process window for being subsequently formed isolation film is too small, influence the formation quality of the isolation film.If first liner
320 thickness of layer are excessive, correspondingly, 320 thickness of the second laying is then too small, thus second laying is to the fin
The protecting effect of the top of second part 220 and side wall is poor, cause 220 surface of fin second part be subsequently formed it is described every
It is oxidized easily during from film.In the present embodiment, the thickness of first laying 320 and first liner membrane 310
Thickness it is equal, be
In the present embodiment, after forming first laying 320, the anti-reflection coating 400 is removed.
With reference to Figure 10, formed on 320 surface of the first laying, 220 top of the fin second part and side wall
Second laying 500.
The effect of second laying 500 includes two aspects: on the one hand, second laying 500 covers the fin
220 top of portion's second part and side wall play the role of protection 220 top of fin second part and sidewall surfaces, subsequent
The isolation film for covering second laying 500 is formed on the substrate 100, can be avoided the fin second part 220
Top and side wall are oxidized in the step of forming the isolation film.On the other hand, subsequent removal segment thickness isolation film is formed
Separation layer, and gate oxide is formed at 200 top of the fin that the separation layer exposes and sidewall surfaces.The separation layer exists
Forming the gate oxide is influenced to apply stress, second laying to 200 side wall of fin in the process by process environments
500 and first laying 320 can weaken the stress intensity that the separation layer applies 200 side wall of fin.
If the thickness of second laying 500 is blocked up, lead to the second laying on adjacent 200 side wall of the fin
The depth-to-width ratio in region is excessively high between 500, subsequent that the isolation film for covering second laying 500 is formed on the substrate 100,
The filling capacity of the isolation film will be caused poor, influences the formation quality of the isolation film；If second laying 500
Thickness is excessively thin, will affect second laying 500 and imitates to the protection at 220 top of fin second part and sidewall surfaces
Fruit causes 220 surface of fin second part to be oxidized easily during forming the isolation film.In the present embodiment,
Second laying 500 with a thickness of
It is subsequent that the isolation film for covering second laying 500 is formed on the substrate 100, if first laying
The summation of 500 thickness of 320 thickness and the second laying is excessive, and second in the adjacent fin first part 210 will be caused to serve as a contrast
500 spacing of bed course is too small, cause the isolation film fill the second laying 500 in the adjacent fin first part 210 it
Between region ability it is poor, influence the formation quality of the isolation film.Subsequent removal is higher than 210 top of fin first part
Isolation film, form separation layer, the separation layer influenced by process environments to the fin during being subsequently formed gate oxide
200 side wall of portion applies stress, if the summation of 320 thickness of the first laying and 500 thickness of the second laying is too small, institute
The buffering effect for stating the first laying 320 and the second laying 500 is poor, it is difficult to effectively weaken the separation layer 620 to fin 200
The stress intensity that side wall applies.In the present embodiment, the summation of 320 thickness of the first laying and 500 thickness of the second laying
For
In the present embodiment, the material of second laying 500 is amorphous silicon.In other embodiments, second lining
The material of bed course can also be silica, silicon nitride, silicon oxynitride, carbon silicon oxynitride or polysilicon.
With reference to Figure 11, the isolation film 610 for covering second laying 500, the isolation are formed on the substrate 100
Be higher than at the top of film 610 200 top of the fin or with flushed at the top of the fin 200.
The processing step for forming the isolation film 610 includes: to be formed to cover second laying on the substrate 100
500 initial isolation film (not shown), and it is higher than the be located on 220 top of fin second part at the top of the initial isolation film
At the top of two layings；Planarization process is carried out to the initial isolation film, forms the isolation film 610.
In the present embodiment, the material of the isolation film 610 is silicon oxynitride.In other embodiments, the initial isolation
The material of film can also be silicon nitride or silica.
Before forming the isolation film 610, the first laying 320 is covered on 210 side wall of fin first part, it is described
It is covered with the second laying 500 on first laying, 320 surface, 220 top of the fin second part and side wall, thus it is adjacent
The spacing of the second laying 500 on 210 side wall of fin first part is relatively narrow, adjacent 220 side of fin second part
The spacing of the second laying 500 on wall is wider, so the process window for forming the isolation film 610 is larger；Big process window
Mouth is conducive to improve the formation quality of the isolation film 610.
In the present embodiment, the formation process of the initial isolation film includes fluid chemistry gas-phase deposition.The fluid
The technological parameter of chemical vapor deposition process includes: that temperature is 30 DEG C to 190 DEG C, and air pressure is 0.01Torr to 10Torr, technique
Gas includes N (SIH3)3、NH3And O2, the gas flow of the process gas is 20sccm to 10000sccm.
In other embodiments, the formation process of the initial isolation film can also include high-aspect-ratio chemical vapor deposition
Technique.
In the present embodiment, the material of second laying 500 is amorphous silicon, in the process for forming the initial isolation film
In, the material of the oxygen and vapor of introducing second laying 500 easy to oxidize, to make second laying 500
Material be changed into silica.
Due to being covered with the first laying 320,320 table of the first laying on 210 side wall of fin first part
It is covered with the second laying 500 on face, 220 top of the fin second part and side wall, therefore is forming the initial isolation
During film, first laying 320 and the second laying 500 be can be avoided described in the oxygen and steam oxidation of introducing
200 surface of fin thus prevents 200 width of fin to narrow.If the fin is exposed heavy in the fluid chemistry gas phase
Under the process environments of product technique, oxygen and the water vapour fin portion surface easy to oxidize in process environments cause the fin
Width narrows.
In the present embodiment, the top of the isolation film 610 is higher than the second liner being located on 220 top of fin second part
500 surface of layer.
In other embodiments, it can also be padded with second be located at the top of fin second part at the top of the isolation film
Layer top flushes.
In addition, in other embodiments, carrying out that position can also be removed in planarization process step to the initial isolation film
The second laying on fin second part top makes to flush at the top of the isolation film to be formed and at the top of the fin.
With reference to Figure 12, removal is higher than second laying 500 and isolation film 610 at 210 top of fin first part
(referring to Figure 11), remaining isolation film 610 forms separation layer 620.
In the present embodiment, 620 top of the separation layer with flushed at the top of the fin first part 210, the separation layer
620 expose 220 top of fin second part and side wall, to provide spatial position to be subsequently formed gate oxide.
In the present embodiment, second laying 500 at 210 top of fin first part is higher than using dry etch process removal
And isolation film 610.The technological parameter of the dry etch process includes: that etching gas includes CH4And CHF3, wherein CH4's
Gas flow is 8sccm to 500sccm, CHF3Gas flow be 30sccm to 200sccm, chamber pressure be 10mTorr extremely
2000mTorr, radio-frequency power are 100W to 1300W, and it is 80V to 500V that DC self-bias, which sets voltage, and etching gas is passed through the time and is
4s to 500s.
Subsequent 200 top of fin exposed in the separation layer 620 and sidewall surfaces form gate oxide, the separation layer
620 are influenced to apply stress to 200 side wall of fin by process environments during forming gate oxide.If the separation layer
620 thickness are excessive, correspondingly, the volume of the separation layer 620 of 200 two sides of the fin is excessive, so that forming the grid
During oxide layer, the stress that the separation layer 620 applies 210 side wall of fin first part is excessive；If it is described every
620 thickness of absciss layer is too small, and the separation layer insulating property (properties) is poor.In the present embodiment, 620 thickness of separation layer and the fin the
210 height of a part is equal, is
In the present embodiment, 620 width of the separation layer of part 200 two sides of fin is equal, remaining described fin 200
620 width of the separation layer of two sides is unequal.Specifically, the separation layer of 200 two sides of the fin of the central area II
620 width are equal；620 width of separation layer of 200 two sides of the fin of the fringe region I is unequal.
In other embodiments, the spacer width of each fin two sides is unequal.
With reference to Figure 13, gate oxide is formed at 200 top of the fin that the separation layer 620 exposes and sidewall surfaces
700。
In the present embodiment, the gate oxide 700 is formed at 220 top of fin second part and sidewall surfaces.
In the present embodiment, the material of the gate oxide 700 is silica.
In the present embodiment, the gate oxide 700 is formed using thermal oxidation processes.In other embodiments, may be used also
To form the gate oxide using chemical oxidation method or Atomic layer deposition method.
In the present embodiment, the separation layer 620 is sent out by the Effect of Hyperthermic Environment internal structure of the thermal oxidation processes
Changing applies stress to 200 side wall of fin.If the temperature of the thermal oxidation processes is excessively high, will cause it is described every
The stress that absciss layer 620 applies 200 side wall of fin is excessive；If the temperature of the thermal oxidation processes is too low, influence
The formation quality of the gate oxide 700.In the present embodiment, the temperature of the thermal oxidation processes is 800 DEG C~1050 DEG C.
In the present embodiment, 620 width of separation layer of 200 two sides of the fin of the fringe region I is unequal, i.e. edge
620 volume of separation layer of 200 two sides of the fin in region I is unequal, thus the 200 two sides side wall of fin of fringe region I by
The stress intensity of the separation layer 620 arrived is unequal.
There is first laying 320 and the second laying between 210 side wall of the separation layer 620 and fin first part
500, thus first laying 320 and the second laying 500 are applied to 210 side wall of fin first part to separation layer 620
On stress have buffer function, first laying 320 and 500 thickness summation of the second laying are big, be conducive to improve institute
The buffering effect of the first laying 320 and the second laying 500 is stated, thus the stress for being subject to 210 side wall of fin first part
Effect reduces by a certain percentage, to reduce the stress difference that the 200 two sides side wall of fin of fringe region I is subject to, and then avoids side
The fin 200 in edge region I bends.
To sum up, the first laying 320 is formed on 210 side wall of fin first part；In first laying 320
The second laying 500 is formed on surface, 220 top of the fin second part and side wall；Covering is formed on the substrate 100
The isolation film 610 of second laying 500,500 spacing of the second laying on adjacent 220 side wall of fin second part compared with
Greatly, to guarantee that the process window of the isolation film 610 is larger, to improve the formation quality of the isolation film 610；And it is described
First laying 320 and second laying 500 can protect 200 surface of fin, prevent 200 surface of fin from being formed
It is oxidized during isolation film 610.After forming the isolation film 610, removal is higher than 210 top of fin first part
Second laying 500 and isolation film 610, remaining isolation film 610 form separation layer 620, then expose in the separation layer 620
The top of the fin 200 and sidewall surfaces form gate oxide 700, the separation layer 620 is forming the gate oxide 700
During to 200 side wall of fin apply stress, have between the separation layer 620 and 210 side wall of fin first part
There are the first laying 320 and the second laying 500, first laying 320 and 500 thickness summation of the second laying are big, because
And buffering effect is good, can effectively weaken the stress intensity that the separation layer 620 applies 200 side wall of fin, to avoid
The fin 200 bends, and improves the performance of semiconductor structure.
In other embodiments, in the step of forming the separation layer, the fin first part, side, part is also removed
The first laying, the second laying and isolation film on wall.Below with reference to Figure 14 and Figure 15, to the step for forming the separation layer
Suddenly it is described in detail.The step of before forming the separation layer, can refer to previous embodiment, repeat no more.
With reference to Figure 14, removal is higher than second laying 500 and isolation film 610 at 210 top of fin first part,
And also remove the first laying 320, the second laying 500 and isolation film in 210 partial sidewall of fin first part
610 (referring to Figure 11), remaining isolation film 610 forms separation layer 620, and the separation layer 620 exposes the fin second part 220
Side wall and 210 partial sidewall of fin first part.
In the present embodiment, the fin 200 spacing arrangements such as on the substrate 100, therefore central area II is described
620 width of separation layer of 200 two sides of fin is equal；In addition, due to N1 ≠ N2 (referring to Fig. 6), the institute of the fringe region I
620 width of separation layer for stating 200 two sides of fin is unequal.
If the thickness of the isolation film 610 of removal is excessive, correspondingly, 620 thickness of the separation layer is too small, institute is caused
The insulation performance for stating separation layer 620 is poor.In the present embodiment, remove in 210 partial sidewall of fin first part it is described every
From film 610 with a thickness of
With reference to Figure 15, gate oxide is formed at 200 top of the fin that the separation layer 620 exposes and sidewall surfaces
700。
In the present embodiment, in 210 partial sidewall of fin first part, 220 top of the fin second part and side
The gate oxide 700 is formed on wall.
In the present embodiment, the gate oxide 700 is formed using thermal oxidation processes.In other embodiments, may be used also
To form the gate oxide using chemical oxidation method or Atomic layer deposition method.
During forming gate oxide 700, the separation layer 620 is influenced by process environments to the fin
200 side walls apply stress, since 620 width of separation layer of 200 two sides of the fin of the fringe region I is unequal, i.e. institute
The volume for stating separation layer 620 is unequal, therefore the separation layer 620 that the 200 two sides side wall of the fin of fringe region I is subject to
The stress intensity of application is unequal.
There is first laying 320 and the between the separation layer 620 and 210 partial sidewall of fin first part
Two layings 500, since first laying 320 and 500 thickness summation of the second laying are big, thus first laying
320 and second laying 500 separation layer 620 is applied to the stress on 200 side wall of fin buffering effect it is good, can be effective
Weaken the stress intensity that the separation layer 620 applies 200 side wall of fin, and then reduces the fin of fringe region I
The stress difference that 200 two sides side walls are subject to improves semiconductor structure so that the fin 200 of fringe region I be avoided to bend
Performance.
Referring to Fig.1 3, the present invention also provides a kind of semiconductor structure obtained using above-mentioned forming method, the semiconductors
Structure includes: substrate 100 and the fin 200 for protruding from the substrate 100, and the fin 200 includes being located at 100 surface of substrate
Fin first part 210 and the fin second part 220 at the top of the fin first part 210；Positioned at the fin
The first laying 320 on a part of 210 side walls；The second laying 500 positioned at 320 surface of the first laying, and institute
The first laying 320 is stated between the fin first part 210 and second laying 500；Positioned at the substrate 100
Separation layer 620 that is upper and covering 500 surface of the second laying, and 620 top of the separation layer and second laying
500 tops flush；Gate oxide 700 positioned at 200 top of the fin and sidewall surfaces that the separation layer 620 exposes.
In the present embodiment, the substrate 100 includes fringe region I and the center between adjacent edge region I
Domain II has multiple fins 200, the separation layer of 200 two sides of the fin of the central area II on the substrate 100
620 width are equal, and 620 width of the separation layer of 200 two sides of the fin of the fringe region I is unequal.
In the present embodiment, the separation layer 620 is influenced by the process environments for forming the gate oxide 700 to the fin
210 side wall of first part applies stress, and first laying 320 and the second laying 500 are located at the separation layer 620
Between 210 side wall of fin first part, the stress that separation layer 620 applies fin first part 210 can be alleviated.
If the summation of 320 thickness of the first laying and 500 thickness of the second laying is too small, first laying
320 and second laying 500 buffering effect it is poor, it is difficult to effectively weaken the separation layer 620 to 210 side wall of fin first part
The stress intensity of application；If the summation of 320 thickness of the first laying and 500 thickness of the second laying is excessive, correspondingly, phase
The spacing of the second laying 500 is then narrow on adjacent 210 side wall of fin first part, leads to the formation of the separation layer 620
It is of poor quality.In the present embodiment, the summation of 320 thickness of the first laying and 500 thickness of the second laying is
If the ratio of 210 height of fin first part and 220 height of fin second part is excessive, correspondingly,
The volume of the separation layer of 210 two sides of fin first part is then excessive, causes in the mistake for forming the gate oxide 700
Cheng Zhong, the stress difference that the separation layer 620 that the 200 two sides side wall of the fin of fringe region I is subject to applies are excessive.If described
210 height of fin first part and the ratio of 220 height of fin second part are too small, then the thickness of the separation layer 620
It is too small, cause 620 insulating property (properties) of separation layer poor.In the present embodiment, 210 height of fin first part and the fin
The ratio of 220 height of second part is 0.5~1.
In other embodiments, the spacing of the fin of portion central region fin adjacent with two sides is equal, in part
The spacing of the fin in heart district domain fin adjacent with two sides is unequal.
In addition, in other embodiments, it can be unequal with the spacer width of each fin two sides.
To sum up, first laying 320 and second laying, 500 thickness summation are big, and buffering effect is good, can
Effectively weaken the stress intensity that the separation layer 620 applies 200 side wall of fin, to can avoid the institute of fringe region I
It states fin 200 to bend, improves the performance of semiconductor structure.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of method for forming semiconductor structure characterized by comprising
Substrate is provided and protrudes from the fin of the substrate, the fin includes the fin first part and position positioned at substrate surface
Fin second part at the top of the fin first part；
The first laying is formed on fin first part side wall；
The second laying is formed at the top of first laying surface, the fin second part and on side wall；
The isolation film for covering second laying is formed over the substrate, is higher than at the top of the fin at the top of the isolation film
Or it is flushed with the fin top；
Removal is higher than the second laying and isolation film at the top of the fin first part, and remaining isolation film forms separation layer；
At the top of the fin that the separation layer exposes and sidewall surfaces form gate oxide.
2. method for forming semiconductor structure as described in claim 1, which is characterized in that before forming the gate oxide,
The spacer width of the fin two sides is unequal.
3. method for forming semiconductor structure as described in claim 1, which is characterized in that the quantity of the fin be it is multiple,
It is formed before the gate oxide, the spacer width of the part fin two sides is equal, remaining fin two sides
The spacer width is unequal.
4. method for forming semiconductor structure as claimed in claim 3, which is characterized in that the substrate include fringe region and
Central area between adjacent edge region；The spacer width phase of the fin two sides of the central area
Deng the spacer width of the fin two sides of the fringe region is unequal.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the separation layer top and the fin
It is flushed at the top of first part, portion；In the step of forming the gate oxide, in the fin second part that the separation layer exposes
The gate oxide is formed on top and side wall.
6. method for forming semiconductor structure as described in claim 1, which is characterized in that be lower than the fin at the top of the separation layer
At the top of first part, portion；In the processing step for forming the separation layer, also remove in fin first part partial sidewall
The first laying, the second laying and isolation film, expose fin first part partial sidewall；Forming the grid oxygen
In the step of changing layer, formed at the top of the fin first part side wall, fin second part of separation layer exposing and on side wall
The gate oxide.
7. method for forming semiconductor structure as claimed in claim 6, which is characterized in that remove fin first part part
The isolation film on side wall with a thickness of
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the technique step of the isolation film
It suddenly include: to form the initial isolation film for covering second laying over the substrate, and the initial isolation film top is high
At the top of the second laying being located at the top of fin second part；Planarization process is carried out to the initial isolation film, is formed
The isolation film.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the top of the isolation film is higher than position
At the top of the second laying on fin second part top；Alternatively, at the top of the isolation film and on the second top of fin
The second laying at the top of flush.
10. method for forming semiconductor structure as claimed in claim 8, which is characterized in that the formation work of the initial isolation film
Skill includes fluid chemistry gas-phase deposition or high-aspect-ratio chemical vapor deposition process.
11. method for forming semiconductor structure as described in claim 1, which is characterized in that the first laying thickness and
The summation of two laying thickness is
12. the method for forming semiconductor structure as described in claim 1 or 11, which is characterized in that the first laying thickness
And second laying thickness ratio be 0.5~1.
13. method for forming semiconductor structure as described in claim 1, which is characterized in that fin first part height with
The ratio of the fin second part height is 0.5~1.25.
14. method for forming semiconductor structure as described in claim 1, which is characterized in that formed using thermal oxidation processes
The gate oxide.
15. method for forming semiconductor structure as claimed in claim 14, which is characterized in that the temperature of the thermal oxidation processes
Degree is 800 DEG C~1050 DEG C.
16. method for forming semiconductor structure as described in claim 1, which is characterized in that form the work of first laying
Skill step includes: to form the first liner membrane at the top of fin first part side wall, the fin second part and on side wall；
Anti-reflection coating is formed over the substrate, is flushed at the top of the anti-reflection coating with the fin first part top；Removal
First liner membrane at the top of the fin second part and on side wall, remaining first liner membrane form the first liner
Layer；Remove the anti-reflection coating.
17. method for forming semiconductor structure as described in claim 1, which is characterized in that the material of first laying is
Silica, silicon nitride, silicon oxynitride or carbon silicon oxynitride；The material of second laying is silica, silicon nitride, nitrogen oxidation
Silicon, carbon silicon oxynitride, amorphous silicon or polysilicon.
18. a kind of semiconductor structure characterized by comprising
Substrate and the fin for protruding from the substrate, the fin include positioned at the fin first part of substrate surface and positioned at institute
State the fin second part at the top of fin first part；
The first laying on fin first part side wall；
Positioned at the second laying of first laying surface, and first laying be located at the fin first part with
Between second laying；
On the substrate and the separation layer of covering second laying surface, and with described second at the top of the separation layer
It is flushed at the top of laying；
Gate oxide positioned at the fin top and sidewall surfaces that the separation layer exposes.
19. semiconductor structure as claimed in claim 18, which is characterized in that the substrate include fringe region and be located at phase
Central area between adjacent fringe region has multiple fins on the substrate, the fin two sides of the central area
The spacer width is equal, and the spacer width of the fin two sides of the fringe region is unequal.
20. semiconductor structure as claimed in claim 18, which is characterized in that the first laying thickness and the second laying
The summation of thickness isThe ratio of fin first part height and the fin second part height is 0.5
~1.25.
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| US11568121B2 (en) | 2020-06-19 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET semiconductor device grouping |
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| US11568121B2 (en) | 2020-06-19 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET semiconductor device grouping |
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