CN107591399B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107591399B CN107591399B CN201610527859.7A CN201610527859A CN107591399B CN 107591399 B CN107591399 B CN 107591399B CN 201610527859 A CN201610527859 A CN 201610527859A CN 107591399 B CN107591399 B CN 107591399B
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Abstract
A semiconductor structure and method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate; forming a sacrificial layer on the side wall and the top of the fin part; after the sacrificial layer is formed, forming a precursor isolation film on the substrate between the adjacent fin parts, wherein the top of the precursor isolation film is higher than that of the fin parts; annealing the precursor isolating film to convert the precursor isolating film into an isolating film; and removing part of the thickness of the isolation film to expose the top and part of the side wall of the fin part and form an isolation structure. Firstly, forming a sacrificial layer on the side wall and the top of the fin part; in the subsequent process of forming the precursor isolation film, the sacrificial layer is oxidized firstly; therefore, the sacrificial layer can protect the fin portion when the precursor isolation film is formed, oxidation of the fin portion is reduced or avoided, influence on the size of the fin portion can be reduced or avoided, and electrical performance of the semiconductor device is optimized.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the trend toward higher densities of integrated circuits, the devices that make up the circuits are placed more closely in the chip to accommodate the available space on the chip. Accordingly, the density of active devices per unit area of a semiconductor substrate is increasing, and thus effective isolation between devices becomes more important.
The STI (Shallow Trench Isolation) technology has good Isolation effects (e.g., process Isolation and electrical Isolation), and also has advantages of reducing the area occupied by the wafer surface and increasing the integration of the device. Therefore, as the size of integrated circuits decreases, isolation between device active regions is now predominantly by shallow trench isolation structures.
However, the formation process of the prior art isolation structure is liable to have an adverse effect on the electrical properties of the semiconductor device.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a sacrificial layer on the side wall and the top of the fin part; after the sacrificial layer is formed, forming a precursor isolation film on the substrate between the adjacent fin parts, wherein the top of the precursor isolation film is higher than the top of the fin part; carrying out an annealing process on the precursor isolating film, and converting the precursor isolating film into an isolating film; and removing part of the thickness of the isolation film to expose the top and part of the side wall of the fin part and form an isolation structure.
Optionally, the sacrificial layer is made of silicon-rich silicon oxide or amorphous silicon.
Optionally, in the silicon-rich silicon oxide, the atomic percent content of silicon is 50% to 75%.
Optionally, a process of forming the sacrificial layer is an atomic layer deposition process.
Optionally, the sacrificial layer is a silicon-rich oxide layer, and the process parameters of the atomic layer deposition process include: and introducing a precursor containing Si and O into the atomic layer deposition chamber, wherein the process temperature is 80-300 ℃, the pressure is 1-500 mTorr, and the deposition times are 8-50.
Optionally, the thickness of the sacrificial layer is
To
Optionally, the isolation structure is made of silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, the process for forming the precursor isolation film is a flowable chemical vapor deposition process or a high aspect ratio chemical vapor deposition process.
Optionally, the isolation structure is made of silicon oxide, and the flowable chemical vapor deposition process includes: depositing a thin film precursor comprising Si and O on the substrate; and carrying out water vapor annealing treatment on the film precursor to form a precursor isolating film.
Optionally, the process temperature for depositing the film precursor is 50 to 90 ℃; the technological parameters of the water vapor annealing treatment comprise: the annealing temperature is 400 ℃ to 800 ℃, and the annealing time is 15 minutes to 120 minutes.
Optionally, the annealing process is rapid thermal annealing.
Optionally, the parameters of the annealing process include: the annealing temperature is 900 ℃ to 1050 ℃, the annealing time is 10 minutes to 40 minutes, and the pressure is one standard atmospheric pressure.
Optionally, the step of forming the substrate and the fin portion includes: providing an initial substrate; forming a patterned hard mask layer on the initial substrate; etching the initial substrate by taking the hard mask layer as a mask, taking the etched initial substrate as a substrate, and taking the protrusion positioned on the surface of the substrate as a fin part; in the step of forming sacrificial layers on the side walls and the top of the fin portion, the sacrificial layers are also located on the top of the hard mask layer, the side walls and the substrate; in the step of forming a precursor isolation film on the substrate between the adjacent fin parts, the top of the precursor isolation film is higher than the top of the hard mask layer; after the precursor isolation film is converted into the isolation film, before removing the isolation film with partial thickness, the forming method further comprises the following steps: and removing the isolation film higher than the top of the hard mask layer by adopting a planarization process.
Optionally, the process of removing the isolation film with a partial thickness is a dry etching process, a wet etching process, or a process combining the dry etching process and the wet etching process.
Optionally, a wet etching process is used to remove the isolation film with a part of thickness, the solution used in the wet etching process is hydrofluoric acid, the process time is 4 minutes to 200 minutes, and the volume concentration ratio of the hydrofluoric acid is 1:3000 to 1: 500.
Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a substrate and a fin part protruding out of the substrate; the isolation structure is positioned on the substrate between the adjacent fin parts, and the top of the isolation structure is lower than the top of each fin part; and the reaction layer is positioned between the isolation structure and the fin part.
Optionally, the material of the reaction layer is silicon oxide.
Optionally, the thickness of the reaction layer is
To
Optionally, the isolation structure is made of silicon oxide, silicon nitride, or silicon oxynitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
before forming a precursor isolation film, sacrificial layers are formed on the side wall and the top of the fin part; in the subsequent process of forming the precursor isolation film, the sacrificial layer is oxidized firstly; therefore, the sacrificial layer can protect the fin portion when the precursor isolation film is formed, oxidation of the fin portion is reduced or avoided, influence on the size of the fin portion can be reduced or avoided, and electrical performance of the semiconductor device is optimized.
The semiconductor structure of the present invention includes a reaction layer between the isolated structure and the fin. The reaction layer is used for protecting the fin portion in the forming process of the isolation structure, and oxidation of the fin portion is reduced or avoided, so that influence on the size of the fin portion can be reduced or avoided, and further electrical performance of the semiconductor device is optimized.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the formation process of the prior art isolation structure has a bad influence on the electrical performance of the semiconductor device. The reason for this analysis is:
the process for forming the isolation structure mainly comprises the following steps: forming a substrate and a fin part protruding out of the substrate; forming a precursor isolation film on the substrate between the adjacent fin parts; carrying out an annealing process on the precursor isolating film, and converting the precursor isolating film into an isolating film; and removing part of the thickness of the isolation film to form an isolation structure.
However, the fin portion is easily oxidized in the process of forming the precursor isolation film, so that a fin portion material with a partial thickness is consumed, the size of the fin portion is affected, and further the electrical performance of the semiconductor device is easily reduced.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a sacrificial layer on the side wall and the top of the fin part; after the sacrificial layer is formed, forming a precursor isolation film on the substrate between the adjacent fin parts, wherein the top of the precursor isolation film is higher than the top of the fin part; carrying out an annealing process on the precursor isolating film, and converting the precursor isolating film into an isolating film; and removing part of the thickness of the isolation film to expose the top and part of the side wall of the fin part and form an isolation structure.
Before forming a precursor isolation film, sacrificial layers are formed on the side wall and the top of the fin part; in the subsequent process of forming the precursor isolation film, the sacrificial layer is oxidized firstly; therefore, the sacrificial layer can protect the fin portion when the precursor isolation film is formed, oxidation of the fin portion is reduced or avoided, influence on the size of the fin portion can be reduced or avoided, and electrical performance of the semiconductor device is optimized.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a base is provided, and the base includes a substrate 100 and a fin 110 protruding from the substrate 100.
The substrate 100 provides a process platform for the subsequent formation of semiconductor devices.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Specifically, the process steps for forming the substrate 100 and the fin 110 include: providing an initial substrate; forming a patterned hard mask layer 200 on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer 200 as a mask, wherein the etched initial substrate is taken as the substrate 100, and the protrusion on the surface of the substrate 100 is taken as the fin part 110.
In this embodiment, the process of forming the hard mask layer 200 includes: firstly, forming an initial hard mask; forming a graphical photoresist layer on the surface of the initial hard mask; etching the initial hard mask by taking the patterned photoresist layer as a mask to form a hard mask layer 200 on the surface of the initial substrate; and removing the patterned photoresist layer. In other embodiments, the forming process of the hard mask layer can further include: a Self-aligned Double patterning (SADP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (Self-aligned Double patterning) process. The double patterning process includes a LELE (Litho-Etch-Litho-Etch) process or a LLE (Litho-Litho-Etch) process.
In this embodiment, after the substrate 100 and the fin 110 are formed, the hard mask layer 200 on the top of the fin 110 is remained. The hard mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the hard mask layer 200 is used for defining a stop position of the planarization process, so that the top of the fin 110 is protected.
In this embodiment, the top dimension of the fin 110 is smaller than the bottom dimension. In other embodiments, the sidewalls of the fin can also be perpendicular to the substrate surface, i.e., the top dimension of the fin is equal to the bottom dimension.
After the substrate 100 and the fin 110 are formed, the manufacturing method further includes: a liner oxide layer 101 is formed on the surface of the fin 110 for repairing the fin 110. In this embodiment, the liner oxide layer 101 is formed on the sidewalls of the fins 110 and on the substrate 100 between the fins 110.
In this embodiment, the process of forming the pad oxide layer 101 is an oxidation process.
Since the fin 110 is formed by etching the initial substrate, the fin 110 typically has a convex corner and a surface defect. In the oxidation treatment process, because the convex edge part of fin portion 110 is bigger than the surface, and is easier to be oxidized, follow-up getting rid of after liner oxide layer 101, not only the defect layer on fin portion 110 surface is got rid of, and protruding edge part is also got rid of, thereby can make the surface of fin portion 110 is smooth, the crystal lattice quality is improved, avoids the problem of fin portion 110 apex angle point discharge, is favorable to improving fin field effect transistor's performance.
The oxidation treatment may employ an oxygen plasma oxidation process, or a mixed solution oxidation process of sulfuric acid and hydrogen peroxide. It should be noted that the oxidation process also oxidizes the surface of the substrate 100, so that the formed pad oxide layer 101 is also located on the surface of the substrate 100.
In this embodiment, the liner oxide layer 101 is formed by performing an oxidation process on the substrate 100 and the fin 110 by using an ISSG (In-situ steam Generation) oxidation process; since the material of the substrate 100 and the fin 110 is silicon, the material of the correspondingly formed pad oxide layer 101 is silicon oxide.
Referring to fig. 2, a sacrificial layer 300 is formed on the sidewalls and top of the fin 110.
The sacrificial layer 300 is used to protect the fin 110 in a subsequent process, so that oxidation of the fin 110 in the subsequent process can be reduced or avoided.
It should be noted that a hard mask layer 200 is formed on the top of the fin 110, and correspondingly, the sacrificial layer 300 is also located on the top and the sidewalls of the hard mask layer 200. In this embodiment, the sacrificial layer 300 is also located on the substrate 100.
In this embodiment, the material of the sacrificial layer 300 is Silicon Rich Oxide (SRO). Wherein, silicon-rich silicon oxide refers to silicon oxide material with high silicon content. Specifically, the silicon-rich silicon oxide contains silicon in an atomic percentage of 50% to 75%.
In another embodiment, the material of the sacrificial layer may also be amorphous silicon.
It should be noted that the thickness of the sacrificial layer 300 is not too thin, nor too thick. If the thickness of the sacrificial layer 300 is too thin, the protective effect of the sacrificial layer 300 on the fin 110 is not significant enough or the protective effect on the fin 110 is difficult to be achieved in the subsequent process, so that the fin 110 is oxidized too much; due to the limited spacing between adjacent fins 110, if the thickness of the sacrificial layer 300 is too thick, it may easily result in too small a process window for forming isolation structures on the substrate 100 between adjacent fins 110. For this purpose, in this embodiment, the thickness of the sacrificial layer 300 is
To
In this embodiment, the process of forming the sacrificial layer 300 is an atomic layer deposition process. Specifically, the sacrificial layer 300 is a silicon-rich oxide layer, and the process parameters of the atomic layer deposition process include: and introducing a precursor containing Si and O into the atomic layer deposition chamber, wherein the process temperature is 80-300 ℃, the pressure is 1-500 mTorr, and the deposition times are 8-50.
When the process temperature is lower than 80 ℃, the deposition speed of each deposition process is easily caused to be too slow, so that the thickness of the sacrificial layer 300 is thin, or the process time needs to be increased to reach a target thickness value, so that the formation efficiency of the sacrificial layer 300 is reduced; when the process temperature is higher than 300 ℃, thermal decomposition of the precursor is easily caused, so that a phenomenon similar to chemical vapor deposition is introduced, the purity and the step coverage of the sacrificial layer 300 are affected, and the formation quality of the sacrificial layer 300 is finally reduced.
Based on the set process temperature, the chamber pressure and the deposition times are set within reasonable range values, so that the high purity and good step coverage of the sacrificial layer 300 are ensured, the formed sacrificial layer 300 meets a target thickness value, and the formation quality of the sacrificial layer 300 is improved.
Referring to fig. 3, after the sacrificial layer 300 (shown in fig. 2) is formed, a precursor isolation film 400 is formed on the substrate 100 between adjacent fins 110, wherein the top of the precursor isolation film 400 is higher than the top of the fins 110.
The precursor isolation film 400 provides a process foundation for the subsequent formation of isolation structures.
In this embodiment, the precursor isolation film 400 is formed by a Flowable Chemical Vapor Deposition (FCVD) process, so that the subsequently formed isolation structure has a better filling effect at the corner between the substrate 100 and the fin 110. In another embodiment, the precursor isolation film may also be formed by a high aspect ratio chemical vapor deposition process.
In this embodiment, the isolation structure formed subsequently is made of silicon oxide, and correspondingly, the flowable chemical vapor deposition process includes the steps of: depositing a thin film precursor containing Si and O on the substrate 100; and carrying out water vapor annealing treatment on the film precursor to form a precursor isolating film.
It should be noted that, in the process of performing the water vapor annealing treatment on the film precursor, the water vapor annealing treatment also oxidizes the sacrificial layer 300, so that after the precursor isolation film 400 is formed, the sacrificial layer 300 is converted into the reaction layer 350; the material of the sacrificial layer 300 is silicon-rich silicon oxide, and correspondingly, the material of the reaction layer 350 is silicon oxide.
Since the sacrificial layer 300 is oxidized first by the water vapor annealing process, the sacrificial layer 300 may protect the fin 110 when the precursor isolation film 400 is formed, and the oxidation of the fin 110 by the water vapor annealing process is reduced or avoided, so that the influence on the size of the fin 110 may be reduced or avoided.
It should be noted that the annealing temperature of the water vapor annealing treatment is not too low or too high. If the annealing temperature of the water vapor annealing treatment is too low, the precursor isolation film 400 is difficult to form within the process time, or the formation quality of the precursor isolation film 400 is poor; if the annealing temperature of the water vapor annealing process is too high, the sacrificial layer 300 is oxidized to a higher degree by the annealing process, and even the fin portion 110 is easily oxidized.
In this embodiment, the process temperature for depositing the film precursor is 50 to 90 degrees celsius; the technological parameters of the water vapor annealing treatment comprise: the annealing temperature is 400 ℃ to 800 ℃, and the annealing time is 15 minutes to 120 minutes.
It should be noted that the elements contained in the thin film precursor and the material of the reaction layer 350 depend on the material of the subsequently formed isolation structure.
It should be further noted that a hard mask layer 200 is formed on the top of the fin 110, and correspondingly, the top of the precursor isolation film 400 is higher than the top of the hard mask layer 200.
Referring to fig. 4, the precursor isolation film 400 (shown in fig. 3) is subjected to an annealing process 500 to convert the precursor isolation film 400 into an isolation film 410.
In this embodiment, the annealing process is a rapid thermal annealing process. Specifically, the parameters of the annealing process include: the annealing temperature is 900 ℃ to 1050 ℃, the annealing time is 10 minutes to 40 minutes, and the pressure is one standard atmospheric pressure.
In this embodiment, the isolation film 410 is made of silicon oxide. In other embodiments, the material of the isolation film may also be silicon nitride or silicon oxynitride.
Referring to fig. 5 in combination, it should be noted that after the precursor isolation film 400 (shown in fig. 3) is converted into the isolation film 410, the forming method further includes: the isolation film 410 above the top of the hard mask layer 200 is removed using a planarization process.
In this embodiment, a chemical mechanical polishing process is used to remove the isolation film 410 above the top of the hard mask layer 200. After the chemical mechanical polishing process is completed, the height uniformity and the surface flatness of the remaining isolation film 410 are better, so that the thickness value of the isolation film 410 removed in the subsequent process can be better controlled, and the height uniformity and the surface flatness of the subsequently formed isolation structure are better.
Referring to fig. 6, a portion of the thickness of the isolation film 410 (shown in fig. 5) is removed to expose the top and a portion of the sidewalls of the fin 110, thereby forming an isolation structure 420.
The isolation structure 420 serves as an isolation structure of the semiconductor device and is used for isolating adjacent devices.
In this embodiment, the material of the isolation film 410 (shown in fig. 5) is silicon oxide, and correspondingly, the material of the isolation structure 420 is silicon oxide. In other embodiments, the material of the isolation film may also be silicon nitride or silicon oxynitride, and correspondingly, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
It should be noted that, in the present embodiment, the isolation structure 420 is a shallow trench isolation layer.
In this embodiment, a wet etching process is used to remove a portion of the thickness of the isolation film 410. Specifically, the etching solution adopted by the wet etching process is a hydrofluoric acid solution, the process time is 4 minutes to 200 minutes, and the volume concentration ratio of hydrofluoric acid is 1:3000 to 1: 500.
In other embodiments, a dry etching process or a combination of a dry etching process and a wet etching process may be used to remove a portion of the thickness of the isolation film.
It is noted that the ratio of the thickness of the isolation structures 420 to the height of the fins 110 is greater than or equal to 1/4 and less than or equal to 1/2. In the present embodiment, the ratio of the thickness of the isolation structures 420 to the height of the fins 110 is 1/2.
It should be noted that the material of the pad oxide layer 101 is silicon oxide, and the material of the reaction layer 350 is silicon oxide. Therefore, the liner oxide layer 101 and the reaction layer 350 protruding from the isolation structure 420 are removed at the same time of removing a portion of the thickness of the isolation film 410.
It should be further noted that, after the isolation structure 420 is formed, the forming method further includes: the hard mask layer 200 on top of the fins 110 is removed (as shown in figure 5).
In this embodiment, the hard mask layer 200 is removed by a wet etching process. Specifically, the hard mask layer 200 is made of silicon nitride, and correspondingly, the etching solution adopted by the wet etching process is a phosphoric acid solution.
Referring to fig. 6, the present invention also provides a semiconductor structure comprising:
a base including a substrate 100 and a fin 110 protruding from the substrate;
an isolation structure 420 located on the substrate 100 between adjacent fins 110, wherein the top of the isolation structure 420 is lower than the top of the fin 110;
a reaction layer 350 between the isolation structure 420 and the fin 110.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
It should be noted that the reaction layer 350 is formed by oxidation conversion of a silicon-containing film layer under the influence of the formation process of the isolation structure 420; the silicon-containing film layer protects the fin 110 during the formation of the isolation structure 420; the process of forming the isolation structure 420 may reduce or prevent oxidation of the fin 110 by oxidizing the silicon-containing film layer. In this embodiment, the material of the reaction layer 350 is silicon oxide, and the reaction layer 350 is further located between the isolation structure 420 and the substrate 100.
It should be noted that the thickness of the reaction layer 350 is not too thin, nor too thick. If the thickness of the reaction layer 350 is too thin, that is, the thickness of the silicon-containing film layer is too thin, the protection effect of the silicon-containing film layer on the fin 110 is not significant enough or the silicon-containing film layer is difficult to protect the fin 110 during the formation of the isolation structure 420, which may easily cause the fin 110 to be oxidized too much; on the other hand, due to the limited spacing between adjacent fins 110, if the thickness of the reaction layer 350 is too thick, it is likely that the process window for forming the isolation structure 420 on the substrate 100 between adjacent fins 110 is too small. For this reason, in this embodiment, the thickness of the reaction layer 350 is
To
The isolation structure 420 serves as an isolation structure of the semiconductor device and is used for isolating adjacent devices. In this embodiment, the isolation structure 420 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
It should be noted that, in the present embodiment, the isolation structure 420 is a shallow trench isolation layer.
It is noted that the ratio of the thickness of the isolation structures 420 to the height of the fins 110 is greater than or equal to 1/4 and less than or equal to 1/2. In the present embodiment, the ratio of the thickness of the isolation structures 420 to the height of the fins 110 is 1/2.
It should be further noted that the semiconductor structure further includes: and the liner oxide layer 101 is located between the reaction layer 350 and the substrate 100, and is used for repairing the fin portion 110 after the fin portion 110 is formed, so that the surface of the fin portion 110 is smooth, the lattice quality is improved, the problem of tip discharge at the top corner of the fin portion 110 is avoided, and the improvement of the performance of the fin field effect transistor is facilitated. In this embodiment, the material of the pad oxide layer 101 is silicon oxide.
The semiconductor structure of the present invention includes a reaction layer 300 between the isolation structure 420 and the fin 110. The reaction layer 300 is used for protecting the fin 110 during the formation of the isolation structure 420, and reducing or avoiding oxidation of the fin 110, so as to reduce or avoid the influence on the size of the fin, and further optimize the electrical performance of the semiconductor device
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate;
forming a sacrificial layer on the side wall and the top of the fin part;
after the sacrificial layer is formed, forming a precursor isolation film on the substrate between the adjacent fin parts, wherein the top of the precursor isolation film is higher than the top of the fin part; after the precursor isolation film is formed, the sacrificial layer is converted into a reaction layer, and the reaction layer is made of silicon oxide;
carrying out an annealing process on the precursor isolating film, and converting the precursor isolating film into an isolating film;
and removing part of the thickness of the isolation film to expose the top and part of the side wall of the fin part and form an isolation structure.
2. The method of claim 1, wherein the sacrificial layer is made of silicon-rich silicon oxide or amorphous silicon.
3. The method of claim 2, wherein the silicon-rich silicon oxide comprises 50 atomic percent to 75 atomic percent silicon.
4. The method of forming a semiconductor structure of claim 1, wherein the process of forming the sacrificial layer is an atomic layer deposition process.
5. The method of claim 4, wherein the sacrificial layer is a silicon-rich oxide layer, and the atomic layer deposition process comprises the following process parameters: and introducing a precursor containing Si and O into the atomic layer deposition chamber, wherein the process temperature is 80-300 ℃, the pressure is 1-500 mTorr, and the deposition times are 8-50.
6. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer has a thickness of
To
7. The method of claim 1, wherein the isolation structure is made of silicon oxide, silicon nitride, or silicon oxynitride.
8. The method of claim 1, wherein the precursor isolation film is formed by a flowable chemical vapor deposition process or a high aspect ratio chemical vapor deposition process.
9. The method of claim 8, wherein the isolation structure is formed of silicon oxide, and wherein the flowable chemical vapor deposition process comprises: depositing a thin film precursor comprising Si and O on the substrate;
and carrying out water vapor annealing treatment on the film precursor to form a precursor isolating film.
10. The method of claim 9, wherein a process temperature for depositing the thin film precursor is 50 to 90 degrees celsius;
the technological parameters of the water vapor annealing treatment comprise: the annealing temperature is 400 ℃ to 800 ℃, and the annealing time is 15 minutes to 120 minutes.
11. The method of forming a semiconductor structure of claim 1, wherein the annealing process is a rapid thermal annealing process.
12. The method of forming a semiconductor structure of claim 11, wherein the parameters of the annealing process comprise: the annealing temperature is 900 ℃ to 1050 ℃, the annealing time is 10 minutes to 40 minutes, and the pressure is one standard atmospheric pressure.
13. The method of forming a semiconductor structure of claim 1, wherein forming the substrate and fin comprises: providing an initial substrate;
forming a patterned hard mask layer on the initial substrate;
etching the initial substrate by taking the hard mask layer as a mask, taking the etched initial substrate as a substrate, and taking the protrusion positioned on the surface of the substrate as a fin part;
in the step of forming sacrificial layers on the side walls and the top of the fin portion, the sacrificial layers are also located on the top of the hard mask layer, the side walls and the substrate;
in the step of forming a precursor isolation film on the substrate between the adjacent fin parts, the top of the precursor isolation film is higher than the top of the hard mask layer;
after the precursor isolation film is converted into the isolation film, before removing the isolation film with partial thickness, the forming method further comprises the following steps: and removing the isolation film higher than the top of the hard mask layer by adopting a planarization process.
14. The method of claim 1, wherein the process of removing the isolation film with a partial thickness is a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process.
15. The method for forming a semiconductor structure according to claim 14, wherein a wet etching process is used to remove the isolation film with a partial thickness, a solution used in the wet etching process is hydrofluoric acid, a process time is 4 minutes to 200 minutes, and a volume concentration ratio of the hydrofluoric acid is 1:3000 to 1: 500.
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| CN105514021B (en) * | 2014-10-17 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | A method of forming HARP interlayer dielectric layer |
| US9355914B1 (en) * | 2015-06-22 | 2016-05-31 | International Business Machines Corporation | Integrated circuit having dual material CMOS integration and method to fabricate same |
| CN107369643A (en) * | 2016-05-11 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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